The document provides an overview of the MCP23S09 I/O expander with an SPI interface. It describes the device's features such as 8 bidirectional I/O pins, interrupt output pins, and SPI interface. It also covers the device's block diagram, addressing over SPI, interrupt logic and conditions, and SPI timing diagrams. The document is intended to help learn about the working and operation of the MCP23S09 I/O expander.

1. Study On MCP23S09 I/O Expander with SPI Interface Source: Microchip Technology Inc

2. Introduction Purpose To Learn the working and operation of the MCP23S09 SPI Interfaced I/O Expander Device. Outline Features Block Diagram Serial Interface / SPI Addressing Interrupt Logic and Conditions SPI Input output Timings Content 12 pages

3. Features 8-bit remote bidirectional I/O port: I/O pins default to input Open-drain outputs: 5.5V tolerant. 25 mA sink. 200 mA total. High-speed I2C™ interface: ( MCP23009 ) - 100 kHz, 400 kHz, 3.4MHz. Low standby current as low as 1 μA. High-speed SPI interface at 10 MHz ( MCP23S09) Configurable interrupt output pins: Configurable as active-high, active-low or open-drain. Configurable interrupt source: Interrupt-on-change from configured defaults or pin change. Single hardware address pin: (MCP23009) - Voltage input to allow up to eight devices on the bus Polarity inversion register to configure the polarity of the input port data. External reset input.

4. Block Diagram

5. Serial Interface This block handles the functionality of the I2C (MCP23009) or SPI (MCP23S09) interface protocol. The MCP23X09 contains eleven individual registers which can be addressed through the Serial Interface block. The MCP23X09 has the ability to operate in “Byte Mode” or “Sequential Mode”. Byte Mode disables automatic address pointer incrementing. This Mode gives the ability to continually access the same address by providing extra clocks. Sequential Mode enables automatic address pointer incrementing. The MCP23X09 increments its address counter after each byte during the data transfer. The address pointer automatically rolls over to address 00h after accessing the last register.

6. Addressing SPI Devices The MCP23S09 is a slave SPI device. The slave address contains seven fixed bits (no address bits) with the read/write bit filling out the control byte.

7. SPI Addressing Registers

8. Interrupt Logic The INT interrupt output can be configured as “active low”, “active high”, or “open-drain” via the IOCON register. Each pin is individually configurable as follows: • Enable/disable interrupt via GPINTEN • Can interrupt on either pin change or change from default as configured in DEFVAL Both conditions are referred to as Interrupt on Change (IOC). The Interrupt Control Module uses the following registers/bits: • GPINTEN - Interrupt enable register • INTCON - Controls the source for the IOC • DEFVAL - Contains the register default for IOC operation • IOCON (ODR and INTPOL) - configures the INT pin as push-pull, open-drain, and active level (high or low).

9. Interrupt Conditions INTERRUPT-ON-PINCHANGE INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT There are two possible configurations to cause interrupts (configured via INTCON): 1)Pins configured for interrupt-on-pin-change will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs. 2)Pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit.

10. SPI Input/Output Timing SPI INPUT TIMING Diagram SPI OUTPUT TIMING Diagram

11. Typical Performance Curve For SPI Tv Specification

12. Additional Resource For ordering the MCP23S09, please click the part list or Call our sales hotline For additional inquires contact our technical service hotline For more product information go to http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en538921 Newark Farnell