SRAM - Design
and Fabrication
Presented by-
Rinku (170002036)
Nishit Meena (170002038)
Sagar Rangari (170002039)
Outlines
● MOTIVATION
● INTRODUCTION
● SRAM CIRCUIT DESIGN
● EXPERIMENTAL FABRICATION
● FIGURE OF MERIT OF DIFFERENT GENERATION
● APPLICATIONS AND FUTURE SCOPE
MOTIVATION
❖ Recent day’s cache memory sizes are expanded with
advancements and they play an important role in
microchips
❖ SRAM Comprises 50% and more of modern designs
❖ For density, SRAM uses smallest possible devices and
therefore very sensitive to impact of manufacturing
variations
❖ With every era, the sizes of cache memory are increasing
INTRODUCTION
❖ SRAM - Static random access memory
❖ It is type of semiconductor random-access memory
❖ Uses a bistable latch circuit to store the logic
❖ Power consumption varies with frequency of operation
❖ SRAM can be used for high speed memory purpose in
microprocessors
Fig.1 A Static-RAM chip [1]
SRAM CIRCUIT DESIGN
MEMORY CLASSIFICATION
COMPUTER MEMORY
PRIMARY MEMORY SECONDARY MEMORY
HARD DISK
ROM
RAM CD PAN DRIVE FLOPPY DISK
DVD
Features Comparison Between Memory Types
SRAM DRAM
LOW LOW
2 Program voltage
1-8ns 8-50ns
3 Write/Erase time
8ns 50ns
4 Read time
YES
HIGH
10-30ms
0.1us
Hard disk
YES
YES
HIGH
50ns
1us1-
100ms
HIGH
10ms
0.1us
CD FLASH
NO NO
1 Non-Volatility
SRAM
❖ Hold data without external refresh
Fig.2 SRAM Memory Chip
[2]
❖ Simplicity : don’t require external refresh
circuitry
❖ Speed: SRAM is faster than DRAM
❖ Cost: several times more expensive than
DRAM
❖ Size: take up much more space than
DRAM
❖ Power: Consume less power than DRAM
Continued...
➢ A typical SRAM memory made up of six
MOSFETs. Each bit in SRAM is stored on 4
transistors(M1,M2,M3,M4) that forms two
cross- coupled inverter.
➢ This storage cell has two stable states which
are used to denote 0 and 1
➢ Two additional access transistors serve to
control the access to a storage cell during
read and write operation
Fig.3 6-Transistor SRAM Cell [3]
SRAM Read and Write Operation
● For write operation
● Data =1
● Datab=0
● Select=1
● For Read Operation
● Data=1
● Datab=1(Forcefully)
● Select=1
Fig. 4 Write Operation [4]
Fig. 5 Read Operation [4]
SRAM FABRICATION
● 32,42 - Pull up
transistors
● 34,44 - Pull down
transistors
● 50,52 - NMOS
● 58 - Word line
● 54 - Bit line
● 56 - Complimentary
bit line
❏ Fig. 6 Shows the schematic diagram of one bit 6-T SRAM structure
❏ This structure is repeated over and over to form matrix of complex SRAM
IC’s
Fig. 6 [5]
● 60,62,66,68 -
Masks used for
different
purpose, placed
over one
another
● 64 - One bit of
SRAM array
❏ Fig 7 and 8 shows the relative positions of mask to be placed over one
another
❏ Perfect positioning of masks is crucial to make better quality SRAM IC’s
Fig. 8 [5]
Fig. 7 [5]
● 102 - Substrate
● 104 - Isolation
Region
● 106 - High-K gate
insulator (Hafnium
oxide)
● 108 - Another
Insulator (Titanium
Nitride)
● 110 - Dummy gate
electrode material
(Polycrystalline
silicon)
❏ Fig. 9 shows the relative positioning of one bit SRAM cell w.r.t. all masks
❏ Fig. 10 shows the cross sectional view taken along line X-X in Fig.7
❏ Basic steps of device fabrication such as oxidation, diffusion, ion implantation,
photolitiogyaphy etc are followed
Fig. 9 [5]
Fig. 10 [5]
● 116 -
Insulator
(Silicone
nitride)
● 118 -
Insulator
(SiO2)
● 120 - Hard
mask
material
❏ Two different type of insulating materials are deposited (Fig. 11)
❏ Hard mask material is deposited over dummy electrodes for selective etching
(Fig. 12)
Fig. 11 [5] Fig. 12 [5]
● 122 - Intergate
mask
● 124 - Spacer-cut
mask
❏ Intergate and Spacer-cut masks are used for patterning ‘Hard mask layer’, which
then can be used for selective etching
❏ Fig.14 shows the relative positioning of intergate and spacer-cut mask w.r.t original
arrangement
Fig. 14 [5]
Fig. 13 [5]
● 130 - Metal
Silicide
● 132 - Fill
material
(Poly-
crystalline
Si)
❏ After selective etching sharp-cornered structure is obtained (Fig.15)
❏ Implementation of metal silicide and polycrystalline Si
❏ After planarizing Fig.16 is obtained
Fig. 16 [5]
Fig. 15 [5]
● 136 - Hard
mask layer
● 142 - Gate
electrode
material
● 150,152 -
Real Gate
electrodes
● 154 -
Source
drain
contacts
❏ Hard mask layer is patterned (Fig.17), which then used for selective etching
❏ Using this Hard mask layer various connections are established, e.g. -
common gate connection between pull-up and pull-down transistors
❏ After planarizing Fig.18 is obtained
Fig. 18 [5]
Fig. 17 [5]
CHARACTERISTICS
❖ SRAM is more expensive, but faster and significantly less power hungry than
DRAM
❖ It is therefore used where either bandwidth or low power ,or both, are
principal considerations
❖ SRAM is also easier to control and generally more truly random access than
modern types of DRAM
❖ Due to a more complex internal structure, SRAM is less dense than DRAM
and is therefore not used for high-capacity, low-cost applications such as the
main memory in personal computers
FIGURES OF MERIT OF
DIFFERENT GENERATIONS
➢ The first solid state memory chip
➢ It is a 64-bit SRAM
➢ It applied the newly developed Schottky Bipolar technology
April 1969.
Fig. 19 Intel 3101 [6].
➢ The first MOS memory chip
➢ A 256-bit SRAM
➢ Produced in with Silicon gate MOS technology
➢ It gave intel the edge it needed to produce high density memories
July 1969
Fig. 20 Intel 1101
[7]
Fig. 21 Intel Core 2 Duo E6300
Processor [8]
Fig. 22 Latest Intel Core i9-9900T
Processor ( 16M Cache, Up to 4.40 GHz )
[9]
➢ Modern SRAM’s are generally integrated inside microprocessors
Fig. 23 SRAM
Scaling Trend [10]
➢ SRAM trends shows cell area reduced by half every two years
APPLICATIONS AND
FUTURE TRENDS OF
WORK
Non Volatile SRAMs are the future of SRAMs for the following
reasons :-
➢ It provides write times as fast as 20ns .
➢ It provides unlimited write cycles .
➢ It instantly captures data on power loss .
➢ Eliminates the need for a backup battery .
Activities of Non Volatile SRAMs
➢ RAID Controller Cards: These are data storage devices used to manage and
improve the performance of hard disk drivers and solid-state drivers
➢ Programmable Logic Controllers (PLCs): These are computer control systems
used to automate industrial manufacturing equipment
➢ Network Routers: It uses nvSRAM to store critical configuration data so that
they can quickly recover after a power outage
➢ Electronic Gaming Machines: nvSRAM is replacing volatile memories in this
application to eliminate batteries and improve performance
Fig. 24 RAID Controller Card
[11]
Fig. 25 Programmable Logic
Controller [12]
Fig. 26 Network
Router [13]
Fig. 28 Electronic Gaming
Machine [14]
Random Transaction Rate (RTR) - Random Transaction Rate
(RTR) is the number of fully random read or write transactions
a memory can perform every second.
➢ Cypress's QDR-IV SRAM provides RTR up to 2132 MT/s
➢ This level of performance is critical to enable the next
generation of high performance systems
Fig. 29 RTR [15]. Fig. 39 QDR SRAM
[15].
FUTURE SCOPE
❏ To decrease the power dissipation
❏ Density of SRAMs in embedded application
❏ Reduction of leakage in a SRAM cell
Sources
● [1]https://en.m.wikipedia.org/wiki/Static_random-access_memory
● [2]
https://encrypted-tbn0.gstatic.com/images?q=tbn%3AANd9GcTt6M5kR4jsgp9At1BE3orl2vgMXElW-ii
Cs-4blQYRSMQo2VP6
● [3]https://commons.wikimedia.org/wiki/File:6t-SRAM-cell.png
● [4]https://www.slideshare.net/tipusultan3150/sram-dram
● [5]http://www.freepatentsonline.com/20130193516.pdf
● [6]https://newsroom.intel.com/news/intel-at-50-intels-first-product-3101/
● [7]
https://commons.wikimedia.org/wiki/File:Intel_1101_1a.jpghttps://commons.wikimedia.org/wiki/File:Intel_1101_1a.
● [8]https://en.wikipedia.org/wiki/Conroe_(microprocessor)#Conroe
● [9]https://hexus.net/tech/news/cpu/133988-intel-core-i9-9900t-tested-multiple-times-geekbench-4/
● [10]https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/5/
● [11]https://www.esaitech.com/lsi-logic-ser523-6-port-raid-controllercard.html
● [12]https://images.app.goo.gl/p2bwpxSDR9uNsNuG6
● [13]https://www.lifewire.com/how-routers-work-816456
● [14]
http://www.emissourian.com/local_news/county/electronic-gaming-machines-in-use-in-franklin-county-not-regulated/
THANK YOU

Static RAM -Design and Its Fabrication.pptx

  • 1.
    SRAM - Design andFabrication Presented by- Rinku (170002036) Nishit Meena (170002038) Sagar Rangari (170002039)
  • 2.
    Outlines ● MOTIVATION ● INTRODUCTION ●SRAM CIRCUIT DESIGN ● EXPERIMENTAL FABRICATION ● FIGURE OF MERIT OF DIFFERENT GENERATION ● APPLICATIONS AND FUTURE SCOPE
  • 3.
    MOTIVATION ❖ Recent day’scache memory sizes are expanded with advancements and they play an important role in microchips ❖ SRAM Comprises 50% and more of modern designs ❖ For density, SRAM uses smallest possible devices and therefore very sensitive to impact of manufacturing variations ❖ With every era, the sizes of cache memory are increasing
  • 4.
    INTRODUCTION ❖ SRAM -Static random access memory ❖ It is type of semiconductor random-access memory ❖ Uses a bistable latch circuit to store the logic ❖ Power consumption varies with frequency of operation ❖ SRAM can be used for high speed memory purpose in microprocessors Fig.1 A Static-RAM chip [1]
  • 5.
  • 6.
    MEMORY CLASSIFICATION COMPUTER MEMORY PRIMARYMEMORY SECONDARY MEMORY HARD DISK ROM RAM CD PAN DRIVE FLOPPY DISK DVD
  • 7.
    Features Comparison BetweenMemory Types SRAM DRAM LOW LOW 2 Program voltage 1-8ns 8-50ns 3 Write/Erase time 8ns 50ns 4 Read time YES HIGH 10-30ms 0.1us Hard disk YES YES HIGH 50ns 1us1- 100ms HIGH 10ms 0.1us CD FLASH NO NO 1 Non-Volatility
  • 8.
    SRAM ❖ Hold datawithout external refresh Fig.2 SRAM Memory Chip [2] ❖ Simplicity : don’t require external refresh circuitry ❖ Speed: SRAM is faster than DRAM ❖ Cost: several times more expensive than DRAM ❖ Size: take up much more space than DRAM ❖ Power: Consume less power than DRAM
  • 9.
    Continued... ➢ A typicalSRAM memory made up of six MOSFETs. Each bit in SRAM is stored on 4 transistors(M1,M2,M3,M4) that forms two cross- coupled inverter. ➢ This storage cell has two stable states which are used to denote 0 and 1 ➢ Two additional access transistors serve to control the access to a storage cell during read and write operation Fig.3 6-Transistor SRAM Cell [3]
  • 10.
    SRAM Read andWrite Operation ● For write operation ● Data =1 ● Datab=0 ● Select=1 ● For Read Operation ● Data=1 ● Datab=1(Forcefully) ● Select=1 Fig. 4 Write Operation [4] Fig. 5 Read Operation [4]
  • 11.
  • 12.
    ● 32,42 -Pull up transistors ● 34,44 - Pull down transistors ● 50,52 - NMOS ● 58 - Word line ● 54 - Bit line ● 56 - Complimentary bit line ❏ Fig. 6 Shows the schematic diagram of one bit 6-T SRAM structure ❏ This structure is repeated over and over to form matrix of complex SRAM IC’s Fig. 6 [5]
  • 13.
    ● 60,62,66,68 - Masksused for different purpose, placed over one another ● 64 - One bit of SRAM array ❏ Fig 7 and 8 shows the relative positions of mask to be placed over one another ❏ Perfect positioning of masks is crucial to make better quality SRAM IC’s Fig. 8 [5] Fig. 7 [5]
  • 14.
    ● 102 -Substrate ● 104 - Isolation Region ● 106 - High-K gate insulator (Hafnium oxide) ● 108 - Another Insulator (Titanium Nitride) ● 110 - Dummy gate electrode material (Polycrystalline silicon) ❏ Fig. 9 shows the relative positioning of one bit SRAM cell w.r.t. all masks ❏ Fig. 10 shows the cross sectional view taken along line X-X in Fig.7 ❏ Basic steps of device fabrication such as oxidation, diffusion, ion implantation, photolitiogyaphy etc are followed Fig. 9 [5] Fig. 10 [5]
  • 15.
    ● 116 - Insulator (Silicone nitride) ●118 - Insulator (SiO2) ● 120 - Hard mask material ❏ Two different type of insulating materials are deposited (Fig. 11) ❏ Hard mask material is deposited over dummy electrodes for selective etching (Fig. 12) Fig. 11 [5] Fig. 12 [5]
  • 16.
    ● 122 -Intergate mask ● 124 - Spacer-cut mask ❏ Intergate and Spacer-cut masks are used for patterning ‘Hard mask layer’, which then can be used for selective etching ❏ Fig.14 shows the relative positioning of intergate and spacer-cut mask w.r.t original arrangement Fig. 14 [5] Fig. 13 [5]
  • 17.
    ● 130 -Metal Silicide ● 132 - Fill material (Poly- crystalline Si) ❏ After selective etching sharp-cornered structure is obtained (Fig.15) ❏ Implementation of metal silicide and polycrystalline Si ❏ After planarizing Fig.16 is obtained Fig. 16 [5] Fig. 15 [5]
  • 18.
    ● 136 -Hard mask layer ● 142 - Gate electrode material ● 150,152 - Real Gate electrodes ● 154 - Source drain contacts ❏ Hard mask layer is patterned (Fig.17), which then used for selective etching ❏ Using this Hard mask layer various connections are established, e.g. - common gate connection between pull-up and pull-down transistors ❏ After planarizing Fig.18 is obtained Fig. 18 [5] Fig. 17 [5]
  • 19.
    CHARACTERISTICS ❖ SRAM ismore expensive, but faster and significantly less power hungry than DRAM ❖ It is therefore used where either bandwidth or low power ,or both, are principal considerations ❖ SRAM is also easier to control and generally more truly random access than modern types of DRAM ❖ Due to a more complex internal structure, SRAM is less dense than DRAM and is therefore not used for high-capacity, low-cost applications such as the main memory in personal computers
  • 20.
    FIGURES OF MERITOF DIFFERENT GENERATIONS
  • 21.
    ➢ The firstsolid state memory chip ➢ It is a 64-bit SRAM ➢ It applied the newly developed Schottky Bipolar technology April 1969. Fig. 19 Intel 3101 [6].
  • 22.
    ➢ The firstMOS memory chip ➢ A 256-bit SRAM ➢ Produced in with Silicon gate MOS technology ➢ It gave intel the edge it needed to produce high density memories July 1969 Fig. 20 Intel 1101 [7]
  • 23.
    Fig. 21 IntelCore 2 Duo E6300 Processor [8] Fig. 22 Latest Intel Core i9-9900T Processor ( 16M Cache, Up to 4.40 GHz ) [9] ➢ Modern SRAM’s are generally integrated inside microprocessors
  • 24.
    Fig. 23 SRAM ScalingTrend [10] ➢ SRAM trends shows cell area reduced by half every two years
  • 25.
  • 26.
    Non Volatile SRAMsare the future of SRAMs for the following reasons :- ➢ It provides write times as fast as 20ns . ➢ It provides unlimited write cycles . ➢ It instantly captures data on power loss . ➢ Eliminates the need for a backup battery .
  • 27.
    Activities of NonVolatile SRAMs ➢ RAID Controller Cards: These are data storage devices used to manage and improve the performance of hard disk drivers and solid-state drivers ➢ Programmable Logic Controllers (PLCs): These are computer control systems used to automate industrial manufacturing equipment ➢ Network Routers: It uses nvSRAM to store critical configuration data so that they can quickly recover after a power outage ➢ Electronic Gaming Machines: nvSRAM is replacing volatile memories in this application to eliminate batteries and improve performance
  • 28.
    Fig. 24 RAIDController Card [11] Fig. 25 Programmable Logic Controller [12] Fig. 26 Network Router [13] Fig. 28 Electronic Gaming Machine [14]
  • 29.
    Random Transaction Rate(RTR) - Random Transaction Rate (RTR) is the number of fully random read or write transactions a memory can perform every second. ➢ Cypress's QDR-IV SRAM provides RTR up to 2132 MT/s ➢ This level of performance is critical to enable the next generation of high performance systems Fig. 29 RTR [15]. Fig. 39 QDR SRAM [15].
  • 30.
    FUTURE SCOPE ❏ Todecrease the power dissipation ❏ Density of SRAMs in embedded application ❏ Reduction of leakage in a SRAM cell
  • 31.
    Sources ● [1]https://en.m.wikipedia.org/wiki/Static_random-access_memory ● [2] https://encrypted-tbn0.gstatic.com/images?q=tbn%3AANd9GcTt6M5kR4jsgp9At1BE3orl2vgMXElW-ii Cs-4blQYRSMQo2VP6 ●[3]https://commons.wikimedia.org/wiki/File:6t-SRAM-cell.png ● [4]https://www.slideshare.net/tipusultan3150/sram-dram ● [5]http://www.freepatentsonline.com/20130193516.pdf ● [6]https://newsroom.intel.com/news/intel-at-50-intels-first-product-3101/ ● [7] https://commons.wikimedia.org/wiki/File:Intel_1101_1a.jpghttps://commons.wikimedia.org/wiki/File:Intel_1101_1a. ● [8]https://en.wikipedia.org/wiki/Conroe_(microprocessor)#Conroe ● [9]https://hexus.net/tech/news/cpu/133988-intel-core-i9-9900t-tested-multiple-times-geekbench-4/ ● [10]https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/5/ ● [11]https://www.esaitech.com/lsi-logic-ser523-6-port-raid-controllercard.html ● [12]https://images.app.goo.gl/p2bwpxSDR9uNsNuG6 ● [13]https://www.lifewire.com/how-routers-work-816456 ● [14] http://www.emissourian.com/local_news/county/electronic-gaming-machines-in-use-in-franklin-county-not-regulated/
  • 32.