Hafiz Khan has over 20 years of experience in test and product engineering for semiconductor companies. He has extensive experience developing test programs, debugging silicon, and characterizing products on various automatic test equipment. Khan aims to contribute to an aggressive semiconductor environment from post-design to production by leveraging his hands-on expertise in testability, characterization, and qualification.

1. Hafiz Khan
2916 Woods Court, San Jose, CA. 95148
Ph # (408) 205 3894
Email hafizkhan@sbcglobal.net
US Citizen
Objective
Seeking a senior position in the fields of test/product engineering in an aggressive semiconductor
environment where I can contribute from post design to production through my extensive hands
on test and product expertise.
Strengths
Broad technical background in analog and digital semiconductors. ATE Wafer Sort and Final Test
Development, Test Characterization, Qualification. Detailed knowledge and direct work experience
of Testability. Hands on work experience on Verigy 83K/93K, Credence Quartet, Teradyne,
Catalyst, LTX RF ATEs. Have taught in house classes and courses to a large number of test and
product engineers on developing and debugging ATE test programs, tester architecture, hardware,
and methodologies. Extensive project and people management experience in corporate and start-up
environments.
Experience
2014 - 2016, Netronome Corporation, Santa Clara. CA
Network Flow Processors Test development, Product Characterization and Qualification of
Netronome’s first and second generation high speed high count ARM Microengines with multiple
Serdes and DRRs interfaces for Servers and Cloud Applications. Support of TSMC 28nm and Intel
22nm technologies for product development including Verigy test hardware, wafer sort probe cards,
ATE test code and test patterns debugging and yield enhancement.
2007 - 2014, Tilera Corporation, San Jose. CA
Worked on Test development, Product Characterization and Qualification of Tilera’s 36, 64 and 72
Microprocessors on a single chip with Networking, Serdes, DDRs and multiple other features.
Responsibilities include designing ATE final test hardware, wafer sort probe cards, writing ATE test
programs for final test and wafer sort, debugging test patterns, debugging silicon, doing full
characterization and qualification, NPI. Supplier management. Local and off shore production
support.
2005 - 2006, Greenfield Networks, Sunnyvale. Ca
Worked on Test development, Product Characterization and Qualification of Advanced High Speed
Networking Packet Processors with a large number of Serdes and Memory Interfaces. Developed
and debugged Wafer Sort and Final Test Programs on Verigy 93K. Designed FT/WS hardware and
brought to full functionality. Developed AC /DC Characterization programs on ATE. Generated and
debugged Full Scan ATPG, Memory Bist, Serdes Bist and Boundary Scan and Characterization test
patterns.
2003 - 2005, Zeevo, Santa Clara. Ca
Developed, debugged and brought to production Wafer Sort and Final Test for RF Wireless and
Mixed Signal Digital and RF devices on Teradyne Catalyst and LTX CX ATEs Developed AC

2. timings/DC Characterization programs on ATE. Converted and debugged Full Scan, Ram Bist and
ARM processor test patterns.
2000 - 2003, Silicon Image, Sunnyvale Ca.
Worked on High Speed 1.6G-3G Serdes, SATA, Serial Link, Integrated Panel Controllers, PHY,
Mixed Signals, PLL, LVDS, TMDS Testing and Characterization on Agilent 83K/93K ATEs.
Applications in Networking and Mass Storage. Responsible for defining Design for Testability. New
ATE test methodologies. Debugged and developed test and Characterization programs and test
patterns. Jitter Measurements, Performed Yield Improvement, Process Correlation, Test Time
Reduction. Guided lab staff on bench characterization. Worked with customers to resolve their
system correlation and implementation issues.
1996 - 2000, AMD, Sunnyvale Ca.
Microprocessors K6 family. Defined Testability. Supported all technical aspects from design phase
to production. Developed ATE test programs. Implemented Full Scan, Ram Bist, AT speed
functional testing. Debugged all levels of silicon. Performed full digital and analog characterization
of multiple revs of K6 processors on Teradyne J973 ATE.
1993 - 1996, LSI Logic, Fremont, Ca.
Test program Development with new test methodologies for custom ASIC designs on Credence
Quartet ATEs. Enhanced full Scan fault coverage, Iddq, Critical path measurements, Yield
Improvement, and Test time reduction.
Education
MS EE. Montana State University USA
MS Physics. Montana State University USA