Saurabh Chakravarty is seeking a position as a Design Engineer. He has 2.2 years of experience in VLSI industry including 1.4 years as a Design Engineer at Sankalp Semiconductor Pvt Ltd working on SRAM block layout in 28nm technology. He also has 10 months of intern experience at ST Microelectronics working on CAD view generation and characterization. He has knowledge of Cadence tools, memory architecture, and scripting languages like Perl and SKILL.

1. SAURABH CHAKRAVARTY
B-152, Sector-50 Mobile:
08800739426 Swarna Jayanati Rail Nagar
chakravarty.saurabh1@gmail.com
Noida –UP (201301)
OBJECTIVE:
To associate myself with an esteemed organization and to accept the challenges in the job by
utilizing my education, analytical skills more meaningfully and work hard towards achieving the
goals of the organization.
 2.2 years of overall experience in VLSI industry including 1.4 years of experience in
Sankalp Semiconductor Pvt Ltd as a Design Engineer and 10 months experience at ST
Microelectronics as an intern.
 Worked on CAD view generation & characterization with ST Microelectronics as a
client.
 Worked on Memory compiler layout (SRAM) as a part of training in Sankalp
Semiconductor Pvt Ltd.
 Good understanding of Memory Architecture, bitcell Analysis & different memory
blocks.
 Basic knowledge of layout design in 28 nm technology.
 Hands on experience in Cadence tool and Scripting languages, Perl & SKILL.
Job Post: Design Engineer (IC1)
Sankalp semiconductor Private Limited (2014 to present)
SRAM block layout
Technology: 28nm CMOS; 256*16*CM4 memory design.
Role:
PROFESSIONAL SNAPSHOT
POSITION DESCRIPTION & PROJECTS

2. • Worked on memory layouts for the 256*16*CM4 design.
o Leaf cells – NAND, inverter.
o Global control IO blocks, Sense Amplifier.
o The layouts were pitch matched with the 6T bitcell.
Packaging of PLL IPs & PMB Blocks.
Technologies: 14nm FDSOI, 28nm FDSOI, 32nm CMOS, 40nm CMOS, 90nm CMOS.
Roles:
Basic Understanding of PLL & PMB Blocks.
Generation of Core Views and Derived Views.
Understanding of SPEC & LEF file.
Generation and Validation of various physical views like LEF, abstract, cdl, gds,
Synopsys LAYOUT/FRAM and Synopsys Technology File (.lib).
Characterization & Validation of generated views.
Master of Technology – VLSI Design
VIT University, Vellore with an aggregate of 8.51/10, 2013
Bachelor of Technology – Electronics & Communication
Rai Foundation College, RGPV University, Bhopal with an aggregate of 82 %, 2009
Higher Secondary School – (Maths + Biology)
D.A.V Public School, CBSE Board with an aggregate of 71%
Senior Secondary School
D.A.V Public School, CBSE Board with an aggregate of 72 %
 Tools: Cadence-Virtuoso Schematic Editor caliber – LVS, DRC, Eldo, EZwave
 Languages: Basics of PERL & SKILL.
SCHOLASTICS
TECHNICAL SKILLS

3.  Operating Systems: Windows, Linux.
 Best Promising Fresher award for the year 2014, by Sankalp Semiconductor Pvt Ltd.
 Customer Delight Award in the year 2015, for outstanding Performance in ST
Microelectronics Pvt Ltd (client).
 1st
prize winner in National level Paper Presentation at UG level held at TIT, Bhopal
 Certificate of participation in National level volleyball organized at TIT ,Bhopal
 1st
,2nd
,3rd
Prize holder in various competitions like painting,calligraphy,essay competition
etc. in school level.
 Appreciation certificate from UNICEF and World Wildlife Fund(WWF) in school level.
Languages known : English, Hindi, Bengali
Sex : Male
Marital Status : Single
Nationality : Indian
Permanent Address : Ward #6 Jawahar Nagar, BTI Road, Ambikapur (C.G)-497001
Local Address : B-152, Sector-50, Swarna Jayanati Rail Nagar, Noida U.P -201301.
I hereby declare that the information furnished above is true to the best of my knowledge
and I am willing to furnish the necessary documents if needed.
Place:
ACHIEVEMENTS
PERSONAL DETAILS

4. Date: Saurabh Chakravarty