Clark Shepard is an electrical engineer seeking a position where he can develop novel and sustainable product test and manufacturing solutions. He has over 15 years of experience in product and test development at Freescale Semiconductor and Motorola, where he led teams to improve quality, meet schedules, and address design issues. Some of his accomplishments include developing low-cost test solutions, analyzing testability features, improving yield, and specifying internal timing constraints to test parts at full speed.

1. Clark Shepard
Home Phone: 512-291-0491 E-mail:clarkgshepard@gmail.com
Mobile Phone: 512-423-7688
4408 Reynosa Drive Austin Texas 78739
Career Objective
My passion is working for a company where I can develop novel and sustainable product
test and final manufacturing solutions that enable providing compelling solutions to meet
the customer's needs.
Education: Electrical Engineer University of Colorado,Boulder, Colorado
Key Skills:
Agilent 93000 Team Building Demonstrated Self Starter
Teradyne J971 and Ultraflex Requirements Analysis Recognized Innovator
Unix and Linux High Speed Bus Testing Device Characterization
Design for Testability Communicates Clearly Leadership
Test Hardware Definition Cost Containment New Product Introduction
and Validation Root Cause Analysis Device Validation
Statical Data Analysis Spec Compliance Performance Analysis
Leadership Verification Requirements
Project Development Quality Improvement Documentation
Yield Improvement Off Shore Transfers
Work Experience
Sr. Product and Test Development Engineer
Freescale Semiconductor, Inc., Austin, Texas01/2004 to 02/2009
Analyzed the testability features for the next generation of communications processor, resulting
in a plan to correlate both I/O BIST to external bus specs and at-speed scan to functional speed.
Characterized both short and long term PLL clock jitter using the Linux based Agilent 93000
ATE with a novel method. Pinpointed the part's state when it failed to the lead PLL designer by
measuring the variation of a single clock edge vs. the variation of all of the clock edges while
under test. This lead to locating package induced noise coupling as the root cause.
Devised a low cost solution to package and evaluate a test vehicle, by reusing a previously
designed custom package and test hardware developed for a product which was no longer being
produced. This provided a quick path to delivering critical prototype parts to analyzed the new
circuitry while saving over 95% over traditional custom package and test hardware designs.

2. Clark Shepard clarkgshepard@gmail.com
Analyzed the I/O specs proposed the first DDR2 controller in the group, and found that the
design targets used to synthesize the memory interface would not work with several industry
standard memories.
Focused a global cross functional team of design, applications, test, quality and final
manufacturing engineers to address the design disconnects with the I/O specs resulting in
changes to the design requirements. The team's efforts resulted in meeting the company's cost
and time to market goals, while providing a product which worked with low cost standard
memories.
Developed the internal test strategy for a new DDR2/3 interface. This interface used a unique
adaptable delay chain to find the center of data into the part. The test solution involved verifying
the part met all bus specs, as well as using a special structural test of a delay chain to detect any
overlooked faults by observing the signal at the end of the chain transitioned as expected.
Sr. Product Engineer
Motorola Inc., Austin, Texas01/1996 to 01/2004
Drove higher product quality through a partnership with the design team to implement DFT
methods using both memory BIST and Mux-D Flip Flop Scan. Worked closely with the project
management team to justify the small slip to the project design schedule to implement the
changes. As a result, the overall project schedule goals were completed on time by reducing back
end functional test pattern development and debug time.
Specified the need to implement internal timing constraints which required all paths between
flip fops would pass at the full clock speeds under structural testing. This greatly improved the
device validation by synthesizing all of the paths to meet speed, allowing solid scan test patterns
under full clock speed on first silicon.
Developed a plan, specified the requirements, and validated that an internally generated clock
driven scan test mode, matched the functional speed for a part. The clock's function used a slow
internal clock to shift scan data into the scan chains, but provided at-speed clocking of the logic
under test. This eliminated the need for engineering intense efforts to write functional patterns to
find speed paths. The method also extended the useful life for lower cost, slower test equipment
while still testing the part at it's rated speed.
PROFESSIONAL ASSOCIATIONS
Computer, Power & Energy, Power Electronics Societies of the IEEE.
Member of IEEE Standards Association