1. Area(s) of Interest: Digital and Analog VLSI Design, Compact Modeling of Devices for
Circuit Simulation, Standard Cell Characterization, STA.
Educational Qualifications Year Board/Institution CGPA* / %
M.Tech. (Microelectronics & VLSI) 2015
Indian Institute of Technology,
Roorkee
7.342
B.Tech. ( Electronics & Communication
Engineering)
2011
Jaipur Engineering College and
Research Center,Jaipur
66.02
Senior Secondary 2006 D.A.V. Jaipur 57.6
Secondary 2004 D.A.V. Jaipur 85
*on a scale of 10
RESEARCH PUBLICATION
1. Mohit Sharma, S. Maheshwaram, Om. Prakash, A. Bulusu, A.K. Saxena and S.K. Manhas,
"Compact model for vertical silicon nanowire based device simulation and circuit design,” IEEE
ISOCC-2015 Gyeongju, KOREA (Accepted)
2. Om. Prakash, Mohit Sharma, S. Maheshwaram, A. Bulusu, A.K. Saxena and S.K. Manhas, "A
unified verilog – A compact model for lateral SiNW FET incorporating parasitic for circuit simulation,”
ASP-DAC 2015 Tokyo, JAPAN (Communicated ).
PROJECTS
IIT ROORKEE
1. Compact Model for Vertical Silicon Nanowire Based Device Simulation and Circuit Design
( July 17, 2014 to June 30, 2015)
(a) Verilog-A Model: Verilog-A based compact model for Vertical Silicon Nanowire(VNW) is
developed which include all physical effects, device parasitic and work for both long and short
channel. Model is well calibrated with TCAD at device and circuit level for 15nm Technology node.
The developed model is used to simulate and study circuits based on VNW at 15 nm node.
(b) Standard Cell Library Development: VNW based Standard cells at 15nm node of basic
gates are developed. For creating standard cells based on VNW, sizing is done by changing the
number of nanowires for equal rise and fall time, compared to CMOS in which it is done using
change in width or adding parallel transistor. Standard cells Library include cells for Low power
applications, High Performance, Low Vt and High Vt Cells.
(c) Standard Cell Library Characteriztion: Timing parmeters, Power Parameters, Input
capacitance were characterized. Single input switching (SIS) is used while characterizing. All the
parameters are stored in 2D LUTs. All the simulation are done in H SPICE.
Mohit Sharma
M.Tech. (Microelectronics and VLSI)
Intern (Synopsys India Pvt. ltd)
Ltd)Phone – 07409959555, 8769444195
Email: mohitshrm25@gmail.com Indian Institute of Technology Roorkee

2. Jaipur Engineering College and Research Centre. (November 10,2010 to March 15,2011)
2. IR Remote Controlled Based Code Lock System
This is a microcontroller based embedded system. Secret code is transmitted via TV remote. Using
TSOP receiver the signals are received, demodulated and fed to microcontroller and checks
whether the code is correct or not. Depending on code LCD displays a code and relevant action is
taken.
INTERNSHIP INFORMATION
Bharti Hexacom Ltd. Jaipur
Basic GSM concept with network function (May 18,2010 to June 18,2010)
Industrial training on GSM concept which included comprehensive study of cellular mobile
Communication and their practical application in industry.
SKILLS AND ACHIEVEMENTS
Software Packages
Computer Languages
HSPICE, Origin, Xilinx, Waveview
Verilog-A, Verilog, C
Courses taken Digital and Analog VLSI design, CAD for VLSI, MOS device physics and
Modelling, Semiconductor Materials and devices.
Languages Known
Extra-Curricular
English (SRW) , Hindi (SRW)
Represented school at national level at an inter-school football tournament
Stood first in marathon at IIT ROORKEE.
Participated in MARKET BONANZA share trading competition at
renaissance (JECRC).
PERSONAL DETAILS
Father's Name: H P Sharma
Date of Birth: February 5, 1989
Gender: Male
Contact No: 07409959555
Category:GEN
Permanent Address: 10/69 Chitrakoot Scheme,
Ajmer Road, Jaipur-302021 (Rajasthan).
Current Address: 10/69 Chitrakoot Scheme, Ajmer
Road, Jaipur-302021 (Rajasthan).
REFERENCES
Dr. Sanjeev Manhas
Associate Professor
IIT Roorkee
samanfec@iitr.ac.in
Dr. A.K. Saxena
Professor, IIT Roorkee
kumarfec@iitr.ac.in