Resume
- 1. Yi-Hau Chen 3F-1, No.42,Minglun Rd., Gushan Dist., Kaohsiung City 804, Taiwan fallthink@garfield.cse.nsysu.edu.tw 0905-123-600 EDUCATION: National Sun Yat-Sen University Kaohsiung, Taiwan Master of Computer Science and Information Engineering 2013 – 2016 GPA: 3.16 / 4 National Pingtung University Pingtung, Taiwan Bachelor of Computer Science 2009 – 2013 GPA: 3.64 / 4 Honors: Presidential Award, Excellent Project SKILLS: Languages: Mandarin (Native), Taiwanese (Native), English Tools: C++、 C#、 C、 Java、 Python、 Verilog、 RTL、Synopsys、 FPGA PUBLICATION: “Hierarchical Multipartite Function Evaluation,” IEEE Trans. Computers, VOL. 66, NO. 1, JANUARY 2017 PRESENT PROJECT: Hierarchical Multipartite Function Evaluation Description: Function evaluation is an important arithmetic computation in many signal processing applica- tions, such as special function units in modern graphics processing units (GPUs). Hardware implementations of function valuation usually consists of lookup tables (LUT) and some simple arithmetic units of multipliers and/or adders. LUT usually takes a significant portion of total area cost, especially when function evaluators are allowed to compute several different arithmetic functions with shared arithmetic units where evaluation of each function needs separate LUT. In this thesis, we focus on the category of table-lookup-andaddition (TA) function evaluators that are composed of two types of LUT: table of initial values (TI) and table of offset values (TO), followed by a multi-operand adder. It has been shown that multipartite table method (MP) has significant improvement over prior similar designs such as symmetric bipartite table methods (SBTM) and symmetric table addition methods (STAM) for applications with low-to-medium precision require- ments. This thesis presents an extension of MP, called hierarchical multipartite (HMP), which
- 2. further reduces totaltable size by applying several levels of table decompositions. Furthermore, we perform the bit-width optimization by jointly considering the impacts of all error sources dur- ing the search of best table decompositions, leading to more efficient hardware design. Besides, a new lossless decomposition of TI is presented, resulting in additional saving of table size without incurring any extra errors. Experimental results show that the proposed design can efficiently re- duce the total area cost in ASIC and FPGA implementations. Related Techniques: bipartite table methods, multipartite table methods, table-based function evaluation, arithmetic units, lossless compression, VLSI. PAST PROJECTS: Reversible Information Hiding Description: Using the Haar Wavelet Transformation transform images from the space domain to the fre- quency domain. Then, using the histogram-based reversible data hiding method with checkerboard method hide the message to the image. The method is reversible information hid- ing, and remove the encrypted message can recover the original image. Related Techniques: haar wavelet transform, frequency domain, histogram-based, checkerboard , reversible, overflow. Instant Messaging Description: Using the socket class in JAVA implement Instant Messaging and learn the spirit of the object- oriented. Finally the software which has a simple window of the interface can do instant messag- ing and the ability to send files to others and session with multi-person. Related Techniques: JAVA, object-oriented, socket, real-time, thread, deadlock. Genetic Algorithm (GA) Description: Using genetic algorithms solve NP-Complete problems, such as simple polynomials, various com- plex conditions of inequalities, and the travel salesman problem (TSP). Related Techniques: C, NP-Complete program, optimization.