This document describes the design and implementation of binary coded decimal (BCD) digit adders and multipliers on an FPGA platform. Specifically, it proposes a correction-free BCD digit adder that avoids the need for a correction circuit, improving speed and efficiency. It also proposes a BCD digit multiplier based on the Wallace tree architecture. The designs are described in VHDL, simulated, synthesized using Quartus II, and compared. Results show the correction-free BCD adder has the fastest delay and lowest power compared to other proposed adders. The BCD Wallace tree multiplier also achieves better performance than an array-based multiplier design.
A High performance unified BCD adder/SubtractorPrasanna Kumar
Improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary
addition/subtraction without any extra hardware
High Speed radix256 algorithm using parallel prefix adderIJMER
A finite impulse response (FIR) filter computes its output using multiply and accumulate
operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is
implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any
multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only
two partial product rows are obtained in RB form for each input and coefficient multiplications. These
two partial product rows are added using carry free RB addition. Finally the RB output is converted back
to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier
architecture for FIR filter is compared with computation sharing multiplier (CSHM)
A High performance unified BCD adder/SubtractorPrasanna Kumar
Improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary
addition/subtraction without any extra hardware
High Speed radix256 algorithm using parallel prefix adderIJMER
A finite impulse response (FIR) filter computes its output using multiply and accumulate
operations. In the present work, a FIR filter based on novel higher radix-256 and RB arithmetic is
implemented. The use of radix-256 booth encoding reduces the number of partial product rows in any
multiplication by 8 fold. In the present work inputs and coefficients are considered of 16-bit. Hence, only
two partial product rows are obtained in RB form for each input and coefficient multiplications. These
two partial product rows are added using carry free RB addition. Finally the RB output is converted back
to natural binary (NB) form using RB to NB converter. The performance of proposed multiplier
architecture for FIR filter is compared with computation sharing multiplier (CSHM)
FPGA based Real-time Automatic Number Plate Recognition System for Modern Lic...IJERA Editor
This paper proposes a real-time number plate recognition technique which involves localizing the number plate from a rear view image of a vehicle, processing it using image processing and image enhancement techniques to segment and extract the characters in the number plate which are in turn matched against a set of stored templates for an accurate character recognition process. The entire system is developed on a FPGA to achieve real-time processing.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A Pipelined Fused Processing Unit for DSP Applicationsijiert bestjournal
This paper designs a processing element for FFT pr ocessor capable of operating on 32-bit double precision floating point numbers. Pipelining is performed on the computational elements of the DSP processor to enhance the throug hput. The performance of the Processing unit is increased by using the concept of fused arc hitecture on the sub modules � the dot product unit and the add sub unit. Pipelining incre ases the speed of the CE of the processor while fused operations claim area optimization. The DSP applications involve FFT Processors that make use of the butterfly operation s consisting of multiplications,additions,and subtractions of complex valued data (data is sp lit into real part and the imaginary part). The radix-2 and radix-4 butterflies are designed us ing fused architecture. The fused FFT butterflies are to be 20 percent speedier and 30 pe rcent smaller in area compared with the conventional method. The processing unit covers alm ost all the computations necessary for the processor.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Realization of Direct Digital Synthesis in Cordic AlgorithmIJASRD Journal
Nowadays the modern communication system and software defined radio-based applications needs Trans receiver consisting of fully programmable circuit which performs modulation and demodulation process. The method which does not need memory for realizing modulators and demodulators is CORDIC algorithm. The CORDIC algorithm is a versatile algorithm which calculates only adder and shifter operations instead of using multiplier. So, this algorithm is mostly used for VLSI and digital signal processing. The main concept used in this project is Direct Digital Synthesis (DDS) which generates the analog waveform in digital format based on CORDIC algorithm approach .This paper focuses on analysis and simulation of Binary phase shift keying (BPSK), Binary amplitude shift keying (BASK), Binary frequency shift keying (BFSK), Quadrature phase shift keying (QPSK) modulation scheme using DDS based on CORDIC algorithm instead of ROM look up table which greatly reduce the number of slices and no of look up tables. The whole simulation is done on Modelsim and Xilinx-ISE using Verilog descriptive language and these modulation schemes are implemented on Spartan-3 FPGA kit.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of QSD Number System Addition using Delayed Addition TechniqueKumar Goud
Abstract: Quaternary number system is a base-4 numeral system. Using Quaternary Signed Digit (QSD) number system may also execute carry free addition, borrow free subtraction and multiplication. The QSD number system wants a different group of prime modulo based logic elements for each arithmetic operation. In this work we extend this QSD addition to Delayed addition in place of carry free addition. Carry free addition generates intermediate carry and intermediate sum, in this carry propagation is required to generate intermediate sum. To reduce carry propagation we evaluated delayed addition. This delayed addition reduces carry propagation and improves arithmetic calculations. We present both QSD and Floating –point single precision addition using delayed addition. The design work is carried by using Verilog HDL in ISE.
Keywords: QSD, DA, CFA and Floating-Point.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN OF RADIX-8 BOOTH MULTIPLIER USING KOGGESTONE ADDER FOR HIGH SPEED ARIT...eeiej_journal
This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced.
FPGA based Real-time Automatic Number Plate Recognition System for Modern Lic...IJERA Editor
This paper proposes a real-time number plate recognition technique which involves localizing the number plate from a rear view image of a vehicle, processing it using image processing and image enhancement techniques to segment and extract the characters in the number plate which are in turn matched against a set of stored templates for an accurate character recognition process. The entire system is developed on a FPGA to achieve real-time processing.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A Pipelined Fused Processing Unit for DSP Applicationsijiert bestjournal
This paper designs a processing element for FFT pr ocessor capable of operating on 32-bit double precision floating point numbers. Pipelining is performed on the computational elements of the DSP processor to enhance the throug hput. The performance of the Processing unit is increased by using the concept of fused arc hitecture on the sub modules � the dot product unit and the add sub unit. Pipelining incre ases the speed of the CE of the processor while fused operations claim area optimization. The DSP applications involve FFT Processors that make use of the butterfly operation s consisting of multiplications,additions,and subtractions of complex valued data (data is sp lit into real part and the imaginary part). The radix-2 and radix-4 butterflies are designed us ing fused architecture. The fused FFT butterflies are to be 20 percent speedier and 30 pe rcent smaller in area compared with the conventional method. The processing unit covers alm ost all the computations necessary for the processor.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Realization of Direct Digital Synthesis in Cordic AlgorithmIJASRD Journal
Nowadays the modern communication system and software defined radio-based applications needs Trans receiver consisting of fully programmable circuit which performs modulation and demodulation process. The method which does not need memory for realizing modulators and demodulators is CORDIC algorithm. The CORDIC algorithm is a versatile algorithm which calculates only adder and shifter operations instead of using multiplier. So, this algorithm is mostly used for VLSI and digital signal processing. The main concept used in this project is Direct Digital Synthesis (DDS) which generates the analog waveform in digital format based on CORDIC algorithm approach .This paper focuses on analysis and simulation of Binary phase shift keying (BPSK), Binary amplitude shift keying (BASK), Binary frequency shift keying (BFSK), Quadrature phase shift keying (QPSK) modulation scheme using DDS based on CORDIC algorithm instead of ROM look up table which greatly reduce the number of slices and no of look up tables. The whole simulation is done on Modelsim and Xilinx-ISE using Verilog descriptive language and these modulation schemes are implemented on Spartan-3 FPGA kit.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of QSD Number System Addition using Delayed Addition TechniqueKumar Goud
Abstract: Quaternary number system is a base-4 numeral system. Using Quaternary Signed Digit (QSD) number system may also execute carry free addition, borrow free subtraction and multiplication. The QSD number system wants a different group of prime modulo based logic elements for each arithmetic operation. In this work we extend this QSD addition to Delayed addition in place of carry free addition. Carry free addition generates intermediate carry and intermediate sum, in this carry propagation is required to generate intermediate sum. To reduce carry propagation we evaluated delayed addition. This delayed addition reduces carry propagation and improves arithmetic calculations. We present both QSD and Floating –point single precision addition using delayed addition. The design work is carried by using Verilog HDL in ISE.
Keywords: QSD, DA, CFA and Floating-Point.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN OF RADIX-8 BOOTH MULTIPLIER USING KOGGESTONE ADDER FOR HIGH SPEED ARIT...eeiej_journal
This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced.
FPL'2014 - FlexTiles Workshop - 8 - FlexTiles DemoFlexTiles Team
Slides presented at the FlexTiles Workshop at FPL'2014.
Presentation #8: FlexTiles Demo
FlexTiles is a heterogeneous many-core platform reconfigurable at run-time developed within an FP7 project.
Небольшой рассказ про то, как правильно готовить стажировки, зачем нужны летние школы и кто такие интерны, если это не сериал про врачей.
Горячие темы:
- Чего можно добиться от студента, если вывезти его в лес?
- Сколько нужно junior-ов, чтобы свести к нулю работу одного senior-а?
- Почему руководителю программы обучения должен жать руку Куклачёв?
Декабрь 2013, HappyDev, Омск.
Performance Analysis of OSTBC MIMO Using Precoder with ZF & MMSE EqualizerIJERA Editor
In this paper, a bit error rate analysis is presented for multiple-input–multiple-output (MIMO) system with finite-bit feedback is considered in PSK modulation technique, where a transmit signal consists of a rotational precoder followed by an orthogonal space–time block code (OSTBC) which achieve full diversity when a linear receiver, such as, zeroforcing (ZF) or minimum mean square (MMSE), is used. By choosing different parameters, codes with different symbol rates and orthogonally can be obtained .In this paper, we compare the performance of a family of space-time codes. Simulations show how the precoders obtained by our proposed criterion and method perform better bit error rate reduction compared to the existing ones.
Find the right support for any issue related to Canon Printer. You simply need to call at our Toll Free number and our accomplished specialists would go to you promptly.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of High Speed Low Power 16 Bit BCD Multiplier Using Excess-3 C...IJMTST Journal
The paper mainly concentrates on the development of the new architecture for BCD parallel multiplier that
exploits some properties of two different redundant BCD codes to speed up its computation: the redundant
BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In this we have developed a 16
bit BCD multiplier using some new techniques to reduce significantly the latency and area of previous
representative high-performance implementations. The key role plays by the Partial product generation in
parallel using a signed-digit radix-10 recoding of the BCD multiplier with the digit set [-5, 5], and a set of
positive multiplicand multiples (1X, 2X, 3X, 4X, 5X) coded in XS-3.By using the above approach of encoding
there are several advantages like mainly it is a self-complementing code, so that a negative multiplicand
multiple can be obtained by just inverting the bits of the corresponding positive one. Also, the available
redundancy allows a fast and simple generation of multiplicand multiples in a carry-free way and finally, the
partial products can be recoded to the ODDS representation by just adding a constant factor into the partial
product reduction tree. Since the ODDS uses a similar 4-bit binary encoding as non-redundant BCD,
conventional binary VLSI circuit techniques. We had developed a new approach of BCD addition for the final
stage. The above developed architecture of 4X4 has been synthesized a RTL model and given better
performance compared to old version multipliers.
High –Speed Implementation of Design and Analysis by Using Parallel Prefix Ad...IOSRJECE
The binary adder is the critical element in most digital circuit designs including the digital signal processors (DSP) and microprocessor data unit path. As such as extensive research continues to be focused on improving the power, delay, improvement of the adder. The design and analysis of the parallel prefix adders (carry select adders) is to be implemented by using Verilog. In VLSI implementations, parallel prefix adders are very high speed performance. Binary adders are one of the most essential logic elements within a digital system. Therefore, binary addition is essential that any improvement in binary addition can result in a performance boost for any computing system and hence, help improve the performance of the entire system. Parallel-prefix adders (also known as carry-tree adders) are known to have the best performance in VLSI designs. This paper investigates (the Kogge-Stone, sparse Kogge-Stone, Ladner fischer adder, Brent-Kung adder) and compares them to the simple Ripple Carry Adder (RCA) for high number of binary bits.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
A digital calibration algorithm with variable amplitude dithering for domain-...VLSICS Design
The pseudorandom noise dither (PN dither) technique is used to measure domain-extended pipeline
analog-to-digital converter (ADC) gain errors and to calibrate them digitally, while the digital error
correction technique is used to correct the comparator offsets through the use of redundancy bits. However,
both these techniques suffer from three disadvantages: slow convergence speed, deduction of the amplitude
of the transmitting signal, and deduction of the redundancy space. A digital calibration algorithm with
variable-amplitude dithering for domain-extended pipeline ADCs is used in this research to overcome these
disadvantages. The proposed algorithm is implemented in a 12-bit, 100 MS/s sample-rate pipeline ADC.
The simulation results illustrate both static and dynamic performance improvement after calibration.
Moreover, the convergence speed is much faster.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
Design and implementation of Closed Loop Control of Three Phase Interleaved P...IJMTST Journal
A single-phase, three-level, single-stage power-factor corrected AC/DC converter operated under closed
loop manner is presented. That operates with a single controller to regulate the output voltage and the input
inductor act as a boost inductor to have a single stage power factor correction with good output response. The
paper deals with a new single stage three level ac-dc converter which performs both power factor correction
and voltage regulation in a single stage. The proposed converter has two separate controllers, one for power
factor correction and the other for regulating the output voltage. A comprehensive review of the existing single
stage topologies has been carried out. Then the operating principle, control scheme and the design of the new
converter are presented. The proposed converter is having an input power factor close to unity and better
voltage regulation compared to the conventional ac-dc converter topologies. Proposed topology is evaluated
through Matlab/Simulink platform and simulation results are conferred.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
GenAISummit 2024 May 28 Sri Ambati Keynote: AGI Belongs to The Community in O...
Q044067780
1. Prof. R. P. Sarnaik et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.77-80
www.ijera.com 77 | P a g e
Implementation of Binary Coded Decimal Digit Adders and
Multipliers on Fpga Platform
Prof. R. P. Sarnaik (Assistant Prof.)*, Dr. S. A. Ladhake (Principal) **
*(Department of Electronics & Telecommunication, SGBAU, Amravati)
**(Sipna College Of Engineering & Technology, SGBAU, Amravati)
Abstract
Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is
represented by a fixed number of bits. The main problem in existing decimal adders is the need of correction
circuit as the result is in binary form which increases delay & area. In this paper, we propose a high speed BCD
adder and multiplier without need of correction circuit. The Decimal carry-save adders (CSAs) are used to
design BCD digit adders which consist less area, low power and high speed performance. BCD Multiplier is
design using Wallace Tree Architecture, explaining the use of half and full adders for addition of intermediate
product terms obtained after the multiplication of two nibbles (4 bits).In this paper, correction free BCD Adder
is efficient one. FPGAs provide an efficient hardware platform that can be employed for accelerating decimal
algorithms. These designs are described and simulated using VHDL hardware description language Modelsim
Simulator SE 6.3f. BCD Adders & BCD Multipliers are synthesized with the help of Altera Quartus II 9.1 sp2.
Implementation results and comparison with existing designs are provided.
Keywords – BCD Adders, BCD Multiplier, Decimal Adders, Decimal Carry-Save Adders, Wallace Tree
I. Introduction
Binary calculations are not suitable for
commercial, banking, and business applications due
to the unacceptable inexact decimal to binary
conversion errors they produce. In [12] a real
example shows the extreme effect of these wrong
approximations, where it stated that if a
communication company approximates a 5% sales
tax on an item (such as a $0.70 telephone call), the
yearly loss is over than a $5 million. Software
solution to the fractional approximation problem for
decimal arithmetic is somewhat slower one.
Compared to hardware speeds, the performance of
existing decimal arithmetic software libraries is very
poor. Software solution is slower than a hardware
implementation by 100 to 1000 times [4].
Nowadays, decimal arithmetic is
implemented using software while binary arithmetic
is usually implemented by the hardware. Further, the
survey showed that 55% of the numeric data
columns, used by 51 major organization’s databases,
were decimal data types and 43.7% were integer
types which could have been stored as decimals. In
spite of this, currently, decimal floating-point
arithmetic is not supported by any microprocessors.
Decimal floating-point coprocessor could be included
in the machines that handle these calculations to
speed up these applications.
In order to convey the growing evolution of
the decimal arithmetic, efficient decimal algorithms
have to be investigated. Decimal digit adders and
decimal digit multipliers are key components of any
decimal hardware to support decimal arithmetic
applications. Therefore, efficient BCD digit units to
be used in high performance decimal hardware
accelerators. Two main contributions of this work
can be highlighted: proposing two new BCD digit
adders and proposing one new BCD digit multiplier.
These designs are described and simulated using
VHDL hardware description language and
implemented on an FPGA.
II. Related Work
In general for binary addition the long carry
chain of BCD adder slows down the addition
operation. The decimal addition is having delay
problem if BCD range exceeds. To produce BCD
digit product multiplier & multiplicand used a Look
Up Table. But for wide range of digits these Look Up
Table is inefficient.
To improve the BCD adders and BCD
multipliers speed as well as inefficiency, designers
have proposed several enhancements as follows
a) Direct decimal addition provides fast operation
[1]. In this, the designer provides technique for
new high-speed area-optimized correction-free
BCD digit adders that can be employed in
different decimal applications.
b) Decimal speculative addition gives efficient
binary multiplication [3]. In this, the linearity of
carry propagation interferes with parallel
execution using a tree representation.
RESEARCH ARTICLE OPEN ACCESS
2. Prof. R. P. Sarnaik et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.77-80
www.ijera.com 78 | P a g e
c) Conditional speculative decimal addition having
low latency and less hardware requirements [6].
Designer preferred the (Q-T) carry tree
implementation over their parallel prefix carry tree
implementation for their proposed adder.
For high performance decimal floating point
units are used to improve speed and Optimize area
using recoding algorithm by generating partial
products. The parallel generation of partial products
is performed using signed digit radix-10 or radix-5
recodings of multipliers [6] & [8]. The partial
products is implemented in a tree structure based on a
decimal multi operand carry-save addition algorithm
that uses unconventional (non BCD) decimal-coded
number systems.
The proposed a parallel serial decimal
multiplier architecture which provides parallel serial
proposal to reduce complexity and it exploits
overlapping update to speed up pipeline [7]. The
values of the Digit Products in the successive
columns of the product array are added in binary and
converted in decimal. Their decimal alignment
generates a set of three or four serial decimal
numbers whose sum is the product.
We are using Direct Boolean expressions BCD digit
adder’s major approach which is the fastest among
other proposed adders [1]. The proposed Correction
free BCD digit adder increases the speed by applying
correction-free addition techniques [11]. Also two
new BCD digit adders and one new BCD digit
multiplier are included in paper for the purpose of
speeding up decimal arithmetic applications over
FPGAs [8] & [9].
2.1 Direct Boolean Expressions BCD Digit Adder
Design a direct BCD digit adder using a four
bit input, five bit output combinational logic. The
four bit inputs are the two BCD input digits A and B
plus the decimal carry input Cin and the five bit
outputs are the BCD digit of the decimal sum S plus
the decimal carry out Cout. For example, to add (6 + 7
= 13), this operation is translated to (0110 + 0111 =
10011) BCD. The output result (10011) BCD is the
BCD representation of the decimal number 13. The
most significant bit is the decimal carry output
generated from the addition operation, while the
other bits are the BCD summation digit. The truth
table for all output logic functions is constructed for
all possible combinations of the inputs. Since the
inputs are nine bits, the number of possible
combinations is 24
= 16. Many of these combinations
are valid since 4-bit number can take any value from
0 to (15)10. In the case when the input is not valid,
the output is set to don’t care. Table 1 consist the two
input BCD digits are assumed to be A = a3a2a1a0
and B = b3b2b1b0. The output consists of the BCD
digit sum S = s3s2s1s0 and the decimal carry output.
This adder is designed to support both
binary and decimal additions. A binary carry look-
ahead adder (CLA) is used to add two input
operands, which are either binary or decimal
numbers. The result of the binary CLA is the correct
result for binary inputs, but it needs to be corrected
for decimal inputs.
Fig1: Conventional BCD Adder
Table 1: BCD Adder
Inputs Outputs
Cin a3 a2 a1
a0
b3 b2 b1
b0
Cout s3 s2 s1
s0
0 0110 1000 1 0100
1 1001 1001 1 1001
0 1100 0001 - ----
2.2 Correction Free BCD Digit Adder
Fig 2: Correction free BCD adder
The internal architecture of the FPGA
device is used in the synthesis/implementation to
optimized speed/area. Traditionally BCD addition is
usually carried out with two stages of binary addition
(one adder for addition of the two decimal operands
and the second adder for adding correction value) and
an intermediate stage for correction logic
computation. In the first stage, the two decimal
operands are added using a 4-bit binary adder. The
correction that is performed in the second addition
stage is required whenever the result of first addition
stage is greater than 9 = (1001) BCD. The correction
3. Prof. R. P. Sarnaik et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.77-80
www.ijera.com 79 | P a g e
is performed by adding (0110)2 to the result of the
first stage sum using another 4-bit binary adder (the
second addition stage). The correction logic increases
delay and area. The decimal value of A, B, and S can
be used to obtain their 8421 BCD representation. In
general, we can write A =a3a2a1a0, B = b3b2b1b0,
and S =s3s2s1s0, where ai, bi, and si € {0, 1}, i € {0,
1, 2, 3}. A and B can be expressed in terms of two
integers m = a3a2a1 and n = b3b2b1 as: A = 2 × m+
a0 and B = 2 × n + b0. If the two input decimal
digits A and B are 9= (1001)BCD and 8 =
(1000)BCD (last row of Table 1), respectively, then
we have: m = (100)2 = 4 , n = (100)2 = 4 and Z=
z3z2z1z0 0 = 2 × (n + m) = 2 × (4 + 4) = (16)10.This
means that the decimal carry z3 is 1 and the even
decimal digit z2 z1 z0 0 = (6)10 = (0110 )BCD. Since
the produced decimal digit is always even, only
z3z2z1z0 are forwarded to Stage2 of the BCD digit
adder. For finding the Boolean expression, first we
have to make a truth table for different combinations
of the input starting from(0000) to (1001).
Table 2: Correction Free BCD Digit Adder
Inputs Outputs
Cin a3 a2 a1
a0
b3 b2 b1
b0
Cout s3 s2 s1
s0
0 1111 0001 1 0000
0 1001 1001 1 1000
0 1111 1011 1 1010
2.3 Direct Boolean Expressions BCD Digit
Multiplier
Fig.3 BCD Digit Multiplier
In proposed BCD digit multiplier, word
“direct” means no need for neither “first finding the
binary multiplication result and then converting the
product to a BCD form” [9] nor “any recoding
process” [5].Instead, we have used a simplified
Boolean expressions to perform the “direct”
functionality. In this case, the two operands are two
decimal digits A = a3a2a1a0 and B = b3b2b1b0 and
the output P = A × B is 8 bit P7P6P5P4P3P2P1P0
(two BCD digits). Since the input is 8 bits wide, the
number of combinations in the truth table is 28
= 256.
Among all these combinations only 100
combinations are valid and the rest are invalid. All
outputs for the invalid combinations in the truth table
are set to don’t care. If the output functions depend
on more than six variables from the input variable
then it needs hierarchy of LUTs to be implemented.
An example on this is P1 which depends on all the
eight input variables. On the other hand, some
functions depend only on two variables like P0 or
four variables like P7. This means that these two
outputs consumes a single 6-input LUT each.
Wallace tree multiplier consists of three step
process, in the first step, the bit product terms are
formed after the multiplication of the bits of
multiplicand and multiplier, in second step, the bit
product matrix is reduced to lower number of rows
using half and full adders, this process continues till
the last addition remains, in the final step, final
addition is done using adders to obtain the result .
Table 3 : BCD Multiplier
(A)BCD (B)BCD P(p7p6p5p4p3p2p1)
0000 1001 00000000
1000 0010 00010110
1001 1001 10000001
1010 0001 XXXXXXXX
III. 3. Experimental Results And
Comparisons
All our proposed designs were described
using VHDL hardware description language, and
simulated to ensure correct functionality. They were
then synthesized with Altera Quartus II 9.1 sp2 tool
and then simulated in Modelsim Simulator SE 6.3f.
Synthesis results of our BCD digit adders &
multipliers are shown in Table 4 & 5. These results
show that our Correction free BCD digit adder is the
fastest among other proposed adders.
Table 4 : BCD Adder
Adders Delay(ns) Total Thermal
Power
Dissipiation (mW)
Direct BCD
Adder
15.087 71.29
Correction
Free BCD
Adder
15.000 68.54
4. Prof. R. P. Sarnaik et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.77-80
www.ijera.com 80 | P a g e
Table 5 : BCD Multiplier
Multipliers Delay(ns) Total Thermal
Power
Dissipiation (mW)
Array
Multiplier
19.224 68.55
BCD
Wallace
Multiplier
17.913 68.54
IV. Conclusion
The different designers have proposed
several enhancements for high speed area
optimization .But, In this paper, We have studied and
implemented Direct BCD Addition approach for this.
The correction-free BCD digit adders are used which
provides correction-free addition techniques. In this
paper, two new BCD digit adders and one new BCD
digit multipliers are designed to speed up decimal
arithmetic applications over FPGA.
References
[1]. M. S. Schmookler and A. Weinberger,
“High speed decimal addition,” IEEE
Transactions on Computers, vol. 20, pp.
862–866, 1971.
[2]. R. H. Larson, “Medium speed multiply,”
IBM Technical Disclosure Bulletin, p. 2055,
1973.
[3]. H. Wetter W. Bultmann, W. Haller and A.
Worner, “Binary and decimal adder unit,”
2001.
[4]. M.F. Cowlishaw, “Decimal Floating-Point:
Algorism for Computers,” Proc. 16th IEEE
Symp. Computer Arithmetic, pp. 104-111,
July 2003.
[5]. E. M. Schwarz, “Decimal multiplication
with efficient partial product generation,” in
Proceedings of the 17th IEEE Symposium on
Computer Arithmetic, Washington, DC,
USA, 2005, ARITH ’05, pp. 21–28, IEEE
Computer Society.
[6]. A. V´azquez and EAntelo, “Conditional
speculative decimal addition,” Nancy,
France, 2006.
[7]. L. Dadda. Parallel decimal multipliers: a
hybrid approach. AlaRI Internal Report,
2006.
[8]. A. Va´zquez, E. Antelo, and P. Montuschi,
“A New Family of High-Performance
Parallel Decimal Multipliers,” Proc. 18th
IEEE Symp. Computer Arithmetic, pp. 195-
204, June 2007.
[9]. G. Jaberipur and A. Kaivani, “Binary-coded
decimal digit multipliers,” IET Computers
and Digital Techniques, vol. 1, no. 4, pp.
377–381, 2007.
[10]. N. H. Tuli´c, “Fpga implementations of
decimal arithmetic cells,” M.S. thesis,
Jordan University of Science and
Technology, May 2009.
[11]. Inc.xilinx,“Vertix5datasheet”,http://www.
xilinx.com/support/documentation/datasheet
s/ds100.pdf.
[12]. IBMCorporation,“DecimalFAQ,”
http://www2.hursley.ibm.com/decimal/decifaq1.html.
’