This document discusses preventing data loss during asynchronous clock domain crossings in physical implementation. It describes how unconstrained placement and routing of control signals can cause delays that violate setup times. A methodology is proposed to group and constrain related logic in the physical design to reduce delays. Applying placement constraints and guides was shown to successfully reduce net lengths for mux select and FIFO empty signals by over 50%.
This thesis presents a simulation based analysis of these protocols. We used the combination of EIGRP&IS-IS, RIP&IS-IS routing protocols on the Hybrid network in order to reveal the advantage of one over the other as well as the robustness of each protocol combination and how this is measured.
This SON tutorial is part of the 3GPP Self-Organizing Networks series (#3GPPSONSeries). In this part we will look at ANR or Automatic Neighbour Relationship. As part of ANR functionality, the base station asks the UE to report the cells even if the cells are not in the list of neighbouring cells. These ‘detected cells’ reported by the UE is used by the base station to maintain an updated neighbouring cells list.
All our #3G4G5G slides and videos are available at:
Videos: https://www.youtube.com/3G4G5G
Slides: https://www.slideshare.net/3G4GLtd
5G Page: https://www.3g4g.co.uk/5G/
Free Training Videos: https://www.3g4g.co.uk/Training/
This thesis presents a simulation based analysis of these protocols. We used the combination of EIGRP&IS-IS, RIP&IS-IS routing protocols on the Hybrid network in order to reveal the advantage of one over the other as well as the robustness of each protocol combination and how this is measured.
This SON tutorial is part of the 3GPP Self-Organizing Networks series (#3GPPSONSeries). In this part we will look at ANR or Automatic Neighbour Relationship. As part of ANR functionality, the base station asks the UE to report the cells even if the cells are not in the list of neighbouring cells. These ‘detected cells’ reported by the UE is used by the base station to maintain an updated neighbouring cells list.
All our #3G4G5G slides and videos are available at:
Videos: https://www.youtube.com/3G4G5G
Slides: https://www.slideshare.net/3G4GLtd
5G Page: https://www.3g4g.co.uk/5G/
Free Training Videos: https://www.3g4g.co.uk/Training/
VERIFICATION OF FOUR PORT ROUTER FOR NETWORK ON CHIPEditor IJMTER
The focus of this Paper is the actual implementation of Network Router and verifies the
functionality of the four port router for network on chip using the latest verification methodologies,
Hardware Verification Languages and EDA tools and qualify the IP for synthesis and implementation.
This Router design contains three output ports and one input port, it is packet based Protocol. This Design
consists Registers and FIFO. For larger networks, where a direct-mapped approach is not feasible due to
FPGA resource limitations, a virtualized time multiplexed approach was used. Compared to the provided
software reference implementation, our direct-mapped approach achieves three orders of magnitude
speedup, while our virtualized time multiplexed approach achieves one to two orders of magnitude
speedup, depending on the network and router configuration.
In the last few years, video streaming facilities over TCP or UDP, such as YouTube, Facetime, Daily-motion, Mobile video calling have become more and more popular. The important
challenge in streaming broadcasting over the Internet is to spread the uppermost potential quality,
observe to the broadcasting play out time limitation, and efficiently and equally share the offered
bandwidth with TCP or UDP, and additional traffic types. This work familiarizes the Streaming
Media Data Congestion Control protocol (SMDCC), a new adaptive broadcasting streaming
congestion management protocol in which the connection’s data packets transmission frequency is
adjusted allowing to the dynamic bandwidth share of connection using SMDCC, the bandwidth share
of a connection is projected using algorithms similar to those introduced in TCP Westwood. SMDCC
avoids the Slow Jump phase in TCP. As a result, SMDCC does not show the pronounced rate
alternations distinguishing of modern TCP, so providing congestion control that is more appropriate
for streaming broadcasting applications. Besides, SMDCC is fair, sharing the bandwidth equitably
among a set of SMDCC connections. Main benefit is robustness when packet harms are due to
indiscriminate errors, which is typical of wireless links and is becoming an increasing concern due to
the emergence of wireless Internet access. In the presence of indiscriminate errors, SMDCC is also
approachable to TCP Tahoe and Reno (TTR). We provide simulation results using the ns3 simulator
for our protocol running together with TCP Tahoe and Reno.
REAL TIME WEB BASED SYSTEM FOR OBSERVING SAG AT SUBSTATIONIJCSEA Journal
The paper describes the designing of web based system for transmission of GPS measurements so that power system operator may monitor overhead conductor sag of power transmission line at substation in real time. The testing results of transmission of GPS measurements from 11KV power transmission line to substation have also been discussed in detail. Raw GPS measurements are not so accurate that these are usable for overhead conductor sag evaluation. The estimated GPS altitude measurements obtained using signal processing techniques such as Least Square Parameter Estimation(LSPE) and Haar Wavelet Transform (HWT) with LSPE are also presented in this paper.
Protocol based QoS Estimation of OFDM-WIMAX Networkidescitation
The assortment of a suitable routing protocol is a key issue while scheming of a
scalable and competent WIMAX network. This work emphasizes on the investigation of
different routing protocols and to evaluate the superlative routing protocol in our proposed
fading resistant OFDM-WIMAX network. The proposed work is investigated with respect
to QoS parameters such as throughput, average delay, end to end delay (Uplink/Downlink),
packet jittering, packet dropped (Uplink/Downlink). The obtained simulative results prop
up the influence of different routing protocols such as OSPF, IS-IS, RIP and IG RP used in
different scenarios.
Versatile Low Power Media Access for Wireless Sensor NetworksMichael Rushanan
Media access control in wireless sensor networks must be small, efficient, and energy conscious. This presentation presented the findings of a paper from Berkley, "Versatile Low Power Media Access for Wireless Sensor Networks," where the authors present just such a MAC implementation called, BMAC. The presentation was delivered to a graduate students at Johns Hopkins University enrolled in Embedded Systems and Wireless Sensor Networks.
Soft Real-Time Guarantee for Control Applications Using Both Measurement and ...CSCJournals
In this paper, we present a probabilistic admission control algorithm over switched Ethernet to support soft real-time control applications with heterogeneous periodic flows. Our approach is purely end host based, and it enables real-time application-to-application QoS management over switched Ethernet without sophisticated packet scheduling or resource reservation mechanisms in Ethernet switches or middleware on end hosts. In designing the probabilistic admission control algorithm, we employ both measurement and analytical techniques. In particular, we provide a new and efficient method to identify and estimate the queueing delay probability inside Ethernet switches for heterogeneous periodic flows with variable message size and period. We implement the probabilistic admission control algorithm on the Windows operating system, and validated its efficacy through extensive experiments.
ROLE OF DIGITAL SIMULATION IN CONFIGURING NETWORK PARAMETERSDeepak Shankar
Selecting the right Ethernet standard and configuring all the network devices in the embedded systems accurately is an extremely hard and rigorous job. The configuration depends on the topology, workloads of the connected devices, processing overhead at the switches, and the external interfaces. Network calculus, mathematical models and analytical techniques provide worst case execution time (WCET), but their probability of activity is extremely wide. This leads to overdesign which leads to higher costs, power consumption, weight, and size. Simulating the network is the best way to measure the throughput of the entire system. Digital system simulation provides better latency and throughput accuracy, but the accuracy is still limited because it does not consider the latency associated with the network OS, cybersecurity processing and scheduling. In many cases, these factors can reduce the throughput by 20-40%.
In this paper, we will present our research on modeling the entire Ethernet network, including the workloads, network flow control, scheduling, switch hardware, and software. To substantially increase the coverage and compare topologies, we have developed a set of benchmarks that provides coverage for different combination of deterministic, rate-constrained, and best effort traffic. During the presentation, we will cover the benchmarks, the list of attributes required to accurately model the traffic, nodes, switches, and the scheduler settings. We will also look at the statistics and reports required to make the configuration decision. In addition, we will discuss how the model must be constructed to study the impact of future requirements, failures, network intrusions, and security detection schemes.
Key Takeaways:
1. Learn how to efficiently use network simulation to design Ethernet systems
2. Develop a reusable benchmark and associated statistics to test different configurations
3. The role and impact of the CDT slots, guard band, send slope, idle slope, shuffle scheduling, flow control and virtual channels
VERIFICATION OF FOUR PORT ROUTER FOR NETWORK ON CHIPEditor IJMTER
The focus of this Paper is the actual implementation of Network Router and verifies the
functionality of the four port router for network on chip using the latest verification methodologies,
Hardware Verification Languages and EDA tools and qualify the IP for synthesis and implementation.
This Router design contains three output ports and one input port, it is packet based Protocol. This Design
consists Registers and FIFO. For larger networks, where a direct-mapped approach is not feasible due to
FPGA resource limitations, a virtualized time multiplexed approach was used. Compared to the provided
software reference implementation, our direct-mapped approach achieves three orders of magnitude
speedup, while our virtualized time multiplexed approach achieves one to two orders of magnitude
speedup, depending on the network and router configuration.
In the last few years, video streaming facilities over TCP or UDP, such as YouTube, Facetime, Daily-motion, Mobile video calling have become more and more popular. The important
challenge in streaming broadcasting over the Internet is to spread the uppermost potential quality,
observe to the broadcasting play out time limitation, and efficiently and equally share the offered
bandwidth with TCP or UDP, and additional traffic types. This work familiarizes the Streaming
Media Data Congestion Control protocol (SMDCC), a new adaptive broadcasting streaming
congestion management protocol in which the connection’s data packets transmission frequency is
adjusted allowing to the dynamic bandwidth share of connection using SMDCC, the bandwidth share
of a connection is projected using algorithms similar to those introduced in TCP Westwood. SMDCC
avoids the Slow Jump phase in TCP. As a result, SMDCC does not show the pronounced rate
alternations distinguishing of modern TCP, so providing congestion control that is more appropriate
for streaming broadcasting applications. Besides, SMDCC is fair, sharing the bandwidth equitably
among a set of SMDCC connections. Main benefit is robustness when packet harms are due to
indiscriminate errors, which is typical of wireless links and is becoming an increasing concern due to
the emergence of wireless Internet access. In the presence of indiscriminate errors, SMDCC is also
approachable to TCP Tahoe and Reno (TTR). We provide simulation results using the ns3 simulator
for our protocol running together with TCP Tahoe and Reno.
REAL TIME WEB BASED SYSTEM FOR OBSERVING SAG AT SUBSTATIONIJCSEA Journal
The paper describes the designing of web based system for transmission of GPS measurements so that power system operator may monitor overhead conductor sag of power transmission line at substation in real time. The testing results of transmission of GPS measurements from 11KV power transmission line to substation have also been discussed in detail. Raw GPS measurements are not so accurate that these are usable for overhead conductor sag evaluation. The estimated GPS altitude measurements obtained using signal processing techniques such as Least Square Parameter Estimation(LSPE) and Haar Wavelet Transform (HWT) with LSPE are also presented in this paper.
Protocol based QoS Estimation of OFDM-WIMAX Networkidescitation
The assortment of a suitable routing protocol is a key issue while scheming of a
scalable and competent WIMAX network. This work emphasizes on the investigation of
different routing protocols and to evaluate the superlative routing protocol in our proposed
fading resistant OFDM-WIMAX network. The proposed work is investigated with respect
to QoS parameters such as throughput, average delay, end to end delay (Uplink/Downlink),
packet jittering, packet dropped (Uplink/Downlink). The obtained simulative results prop
up the influence of different routing protocols such as OSPF, IS-IS, RIP and IG RP used in
different scenarios.
Versatile Low Power Media Access for Wireless Sensor NetworksMichael Rushanan
Media access control in wireless sensor networks must be small, efficient, and energy conscious. This presentation presented the findings of a paper from Berkley, "Versatile Low Power Media Access for Wireless Sensor Networks," where the authors present just such a MAC implementation called, BMAC. The presentation was delivered to a graduate students at Johns Hopkins University enrolled in Embedded Systems and Wireless Sensor Networks.
Soft Real-Time Guarantee for Control Applications Using Both Measurement and ...CSCJournals
In this paper, we present a probabilistic admission control algorithm over switched Ethernet to support soft real-time control applications with heterogeneous periodic flows. Our approach is purely end host based, and it enables real-time application-to-application QoS management over switched Ethernet without sophisticated packet scheduling or resource reservation mechanisms in Ethernet switches or middleware on end hosts. In designing the probabilistic admission control algorithm, we employ both measurement and analytical techniques. In particular, we provide a new and efficient method to identify and estimate the queueing delay probability inside Ethernet switches for heterogeneous periodic flows with variable message size and period. We implement the probabilistic admission control algorithm on the Windows operating system, and validated its efficacy through extensive experiments.
ROLE OF DIGITAL SIMULATION IN CONFIGURING NETWORK PARAMETERSDeepak Shankar
Selecting the right Ethernet standard and configuring all the network devices in the embedded systems accurately is an extremely hard and rigorous job. The configuration depends on the topology, workloads of the connected devices, processing overhead at the switches, and the external interfaces. Network calculus, mathematical models and analytical techniques provide worst case execution time (WCET), but their probability of activity is extremely wide. This leads to overdesign which leads to higher costs, power consumption, weight, and size. Simulating the network is the best way to measure the throughput of the entire system. Digital system simulation provides better latency and throughput accuracy, but the accuracy is still limited because it does not consider the latency associated with the network OS, cybersecurity processing and scheduling. In many cases, these factors can reduce the throughput by 20-40%.
In this paper, we will present our research on modeling the entire Ethernet network, including the workloads, network flow control, scheduling, switch hardware, and software. To substantially increase the coverage and compare topologies, we have developed a set of benchmarks that provides coverage for different combination of deterministic, rate-constrained, and best effort traffic. During the presentation, we will cover the benchmarks, the list of attributes required to accurately model the traffic, nodes, switches, and the scheduler settings. We will also look at the statistics and reports required to make the configuration decision. In addition, we will discuss how the model must be constructed to study the impact of future requirements, failures, network intrusions, and security detection schemes.
Key Takeaways:
1. Learn how to efficiently use network simulation to design Ethernet systems
2. Develop a reusable benchmark and associated statistics to test different configurations
3. The role and impact of the CDT slots, guard band, send slope, idle slope, shuffle scheduling, flow control and virtual channels
A fundamental problem before carriers today is to optimize network cost
and performance by better resource allocation to traffic demands. This is especially
important with the packet infrastructure becoming a critical business resource.
The key to achieving this is traffic engineering (TE), the process of
systematically putting traffic where there is capacity, and backbone
capacity management, the process of ensuring that there is enough network
capacity to meet demand, even at peak times and under failure conditions,
without significant queue buildups.
In this talk, we first focus on the TE techniques and approaches used
in the networks of two large carriers: Global Crossing and
Sprint, which represent the two ends of the traffic engineering spectrum.
We do so by presenting a snapshot of their TE philosophy, deployment strategy,
and network design principles and operation.
We then present the results of an empirical study of backbone traffic
characteristics that suggests that Internet traffic is not self-similar at
timescales relevant to QoS. Our non-parametric approach requires minimal
assumptions (unlike much of the previous work), and allows
us to formulate a practical process for ensuring QoS using backbone
capacity management.
(This latter work is joint with Thomas Telkamp, Global Crossing Ltd. and Arman
Maghbouleh, Cariden Technologies, Inc.)
ASIC DESIGN OF MINI-STEREO DIGITAL AUDIO PROCESSOR UNDER SMIC 180NM TECHNOLOGYIlango Jeyasubramanian
- Designed and analyzed a complete MSDAP with optimized convolution computation by only shifts and adds using power-of-2 coefficients. Synthesized the chip through high level architecture design (C Program), Logic synthesis (Synopsys Design Compiler) and Physical Synthesis (Synopsys IC compiler).
- Achieved a low power consumption of 3.1438mW at 29.186Mhz clock frequency, with core utilization of 70% and chip area of 1.29mm2.
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONcscpconf
As the demand for Internet expands significantly in numbers of users, servers, IP addresses,
switches and routers, the IP based network architecture must evolve and change. The design
of domain specific processors that require high performance, low power and high degree of
programmability is the bottleneck in many processor based applications. This paper describes
the design of ethernet packet processor for system-on-chip (SoC) which performs all core
packet processing functions, including segmentation and reassembly, packetization
classification, route and queue management which will speedup switching/routing
performance. Our design has been configured for use with multiple projects ttargeted to a
commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.
Congestion control is a technique used to regulate network traffic and prevent network congestion.
It works by monitoring network conditions and adjusting the amount of data being sent to avoid overloading the network.
The most common congestion control
algorithms are:
TCP Congestion Control
Leaky Bucket
Random Early Detection
Ensuring the Adaptive Path for the Routing in 5g Wireless Network
Prevention of Data Loss in physical implementation of FIFOs and Data Synchronizers
1. Prevention of Data Loss in Physical
Implementation of FIFOs and Data Path
Synchronizers
Ramesh Rajagopalan (rameraja@cisco.com), Cisco Systems Inc, San Jose, CA
Ajay Bhandari (ajayb@cisco.com), Cisco Systems Inc, San Jose, CA
Namit Gupta (namit@atrenta.com), Atrenta Inc, San Jose, CA
2. Introduction: Asynchronous control and data bus domain crossings
Network switching ASICs have a multitude of IPs with different clock domains,
at varying speeds that interface with a variety of buses and I/Os.
Signals that cross clock boundaries create clock domain crossings (CDCs).
Asynchronous crossings have no relationship between the sending and receiving
clocks . This poster discusses only issues related to asynchronous clock domain
crossings.
Multi-flop synchronizers are used for a control signal’s asynchronous domain
crossing to avoid meta-stability.
In an asynchronous data bus transfer, the data is set up; then, a control signal
that is synchronized with the destination domain enables data capture at the
destination register. This relies on data to be stable when an enable is asserted.
This requirement is addressed in logic design by extending the data pulse for a
required number of cycles of destination clock so that the data is held when the
enable is asserted.
3. Data loss issue and its prevention by logic design
In an asynchronous data bus transfer, each valid transition on the source
data should get captured in the destination domain to prevent data loss.
To prevent data loss in a fast-to-slow clock domain data crossing:
1) Data must be held long enough to be registered by the destination flop.
2) Data should not change when the control (qualifier) signal that gates
or enables the data crossing is active.
Logic design ensures that
1) the data is held long enough by extending the data pulse for the time
it takes to latch the data at the destination.
2) data is allowed to change only after receiving feedback from the
destination domain after latching the current data.
4. Impact on physical design implementation of data path synchronizers
During physical implementation of a data path synchronizer, the control
signals from the source domain to the destination domain are timing-wise
unconstrained in their path from the multi-flop synchronizers to the
enable/mux-select or AND-based qualifiers.
The unconstrained standard cell placement and detailed routing of the
control path might result in a sub-optimal placement of the cells and scenic
routing .
As the technology node advanced, the RC interconnect values have
increased by several folds especially for the lower routing layers.
Higher net delay values could be seen for the control signal used as a
synchronized enable at the qualifying gate of the domain crossing .
6. Delay due to physical implementation impacting data transfer across
Clock Domains
The impact of the large interconnect delay on the falling edge of the control signal is illustrated.
The extended active enable signal would result in latching an unknown value of the data at the
destination domain. A similar issue occurs due to the delay in the rising edge of the control signal
as well.
7. Need for a methodology to mitigate data loss due to physical
implementation
To mitigate the large physical net delay in the control signal, logic designers could
introduce one more synchronizer register in the destination domain before sending
the feedback to source domain to enable the data change to the next value.
Such logic design-based solutions that introduce additional latencies would work for a
given ratio of fast-to-slow clocks, with the control path delay due to physical
implementation not exceeding one cycle of the destination clock.
However, for designs:
1) that need to handle varying fast to slow clock ratios (as high as 10:1) based on
different operating modes or due to use of the power reduction mode in the design, or
2) that are intolerant to any additional latency, or
3) that use very high layout utilization and are subject to local routing congestion,
it would be better to physically constrain the control signal paths to place and route
them within the allowed delay
8. Physical design methodology to mitigate data loss due to physical delay
in enabling the fast-to-slow data crossings
Physical Design methodology to be followed:
3)Identify the destination register and the enable that gates the data crossing
The SpyGlass® CDC tool in a CrossingInfo.rpt lists the “mux-select synchronizers”,
“enable synchronizers”, “AND gate-based synchronizers” and
“FIFOs” (with read pointer and write pointer instances).
2) Using this information create an “instance group” of cells in the control path.
Make this instance group into a soft guide for placement purposes in the Cadence EDI tool
3) During cell placement, set the soft guide effort level to high to increase the degree
of closeness between placement of the control path logic listed under a given soft guide.
4) For improved results, pre-place the enable gating logic and fix it prior to
incremental placement to get the cells in the soft guide placed near the fixed logic.
Also, set a higher net weight on nets that need to be shorter.
5) Create a max delay constraint from the last synchronizer register to the pin where
the control gates the data crossings.
6) Report timing for the control signal path (as an unconstrained path) and the analyze
the actual delays for potential data loss.
9. Mux select control path :
Reduction in net length/delay with suggested physical design methodology
Logic View of Mux select control path
Physical view - 1.5 mm long Mux select control Net length reduced to 130microns after
path (Before using the suggested physical design using suggested physical methodology
methodology)
10. FIFO empty signal logic :
Reduction in net length/delay by applying suggested physical design methodology
Logical view – FIFO empty logic
Physical view - 430 microns long FIFO Net length reduced to 120 microns after
empty signal path (Before using the using suggested physical methodology
suggested physical design methodology)
11. Conclusion, Limitations and Future Work
CONCLUSION:
Prevention of data loss in a fast-to-slow clock domain data crossing
needs to be addressed at both the logical and physical levels.
The critical aspect is the implementation of a control path in a data
synchronizer within the delay limit
. Physical design techniques such as creating a soft guide for placement
of control path logic proved to be very useful in bringing some guidance
on the otherwise unconstrained control path.
LIMITATIONS
No single frame work or tool to infer destination domain registers and
qualifier gates of CDC logic and create physical placement groups.
FUTURE WORK
Automation of the generation of the placement constraints is slated to be
done in near future.