Pk lab 5
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This document outlines the process for analyzing pharmacokinetic data using one and two compartment models. Equations are given for calculating parameters like elimination rate constant, area under the curve, volume of distribution from intravenous bolus concentration over time data. Several example problems are included to show how
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The document discusses compartment modeling and one compartment open models. It describes how the body can be represented as a single well-mixed compartment and outlines the assumptions of compartmental models. It then covers one compartment open models for intravenous bolus administration, intravenous infusion, and extravascular administration. For intravenous bolus administration, the elimination phase can be characterized by parameters like elimination rate constant, half-life, and clearance. Intravenous infusion allows for constant rate input into the compartment. Extravascular administration models absorption as either zero-order or first-order kinetics.
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Assignment 1 Description Marks out of Wtg() Due date .docx
Assignment 1
Description Marks out of Wtg(%) Due date
Assignment 1 200 20 28 August 2015
Part A: Comparators and Switching (5%)
(1) Signal limit detector
Use a 339 comparator, a single 74LS02 quad NOR gate and a +5V power supply only to
design a circuit which will detect when a voltage goes outside the range +2.5V to +3.5V
and such that an LED lights and stays lit. Provide a manual reset to extinguish the LED.
Design hints
1. The circuit has an analog input and a digital output so some form of comparator circuit
is required. There are two thresholds so two comparators are required, with the analog
input applied to both. This arrangement is sometimes known as a window detector.
2. Arrange the output of the comparators to be +5V logic levels, and combine the two
outputs logically to produce one signal which is for example, high for out-of-range, and
low for within-range.
3. Latch the change from in-range to out-of-range.
Design procedure
1. Start at the output and work backwards.
2. Select a latch circuit (flip-flop) and determine what combinations of inputs are needed to
latch and then reset it, ensuring that the LED is connected correctly with regard to both
logic and current flow.
3. Determine the logic needed to combine two comparator outputs in such a way as to
correctly operate the latch.
4. Choose comparator outputs which will correctly drive the logic. Remember that the
reference voltage at the input of the comparator may be at either the + or – input.
5. Choose resistors to provide the correct reference voltages.
Note: You will need to consult data for both the 74LS02 and the 339 (see data sheets).
Test
It is strongly recommended that you assemble and test your circuit.
(2) MOSFET Switching
Find out information on the operation of, and configuring of, MOSFETs to be used in
switching circuits. In particular note the differences between BJTs and MOSFETs in this
role. Draw up a table to highlight the differences and hence the pros and cons on each
device for particular situations (eg. Switching high-to-low or low-to-high (ie. P or N type),
high or low current switching, low or high voltage switching).
Consider the following BJT switching circuit. Analyse the operation of the circuit to
understand the parameters involved. Choose suitable replacement MOSFETs to be used
ELE2504 – Electronic design and analysis 2
instead of the output switching BJTs in the given circuit. Include any necessary circuit
changes for the new devices to operate so as to maintain the circuit’s required parameters.
Where Vcc = 12V and Relay resistance = 15Ω .
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reference notes455647_1_EE460-Project-131.pdfKing Fahd Un.docx
reference notes/455647_1_EE460-Project-131.pdf
King Fahd University of Petroleum and Minerals
Department of Electrical Engineering
EE Power Electronics Project
Design of a DC Chopper
I. Design of an AC/DC converter with the following the specifications:
AC supply voltage VS = 230 V (rms), 60 Hz.
The DC output voltage V01(dc) = 48 V.
The ripple factor of the output voltage RFV 5%.
II. Design of step-down DC chopper with the following specifications:
Switching (or chopping) frequency, fs = 20 kHz.
Dc input supply voltage VS = 48 V dc, where as the source available is an ac with 230 V
(rms).
Load resistance R = 5 .
The DC output voltage V02(dc) = 12 V.
The peak-to-peak output ripple voltage, VC 2.5%.
The peak-to-peak inductor ripples current, IL 5%.
III. Calculation for both circuits:
(a) Determine the values of Le and Ce for the output LC-filter.
(b) Determine the (peak and rms) voltage ratings and the (average, rms, and the peak) current for
all components and devices.
(c) Verify your design calculation by using Pspice simulation.
Design AC/DC
Circuit
Design DC-DC
Chopper Circuit
AC 5
Output Load
The project will be due on Sunday December 22, 2013.
reference notes/455647_2_DC-20Converters-Design (1).pdf
....-ju"ncv
O.
214 Chapter 5 Dc-Dc Converters
Example 5.10
A buck converter is shown in Figure 5.29. The input voltage is V, == 110 V, the average load
age is Va == 60 V, and the average load current is la == 20 A. The chopping u
1 == 20 kHz. The peak-to-peak ripples are 2.5% for load voltage, 5% for load current, and
for filter Le current. (a) Determine the values of L" L, and Ceo Use PSpice (b) to verify the
suits by plotting the instantaneous capacitor voltage vc, and instantaneous load current iL ;
(c) to calculate the Fourier coefficients and the input current is. The SPICE model pax'ameters
the transistor are IS == 6.734f, BF = 416.4, BR == 0.7371, CJC == 3.638P, CJE::
TR == 239.5N, TF = 30L2P, and that ofthe diode are IS :: 2.2E-15, BV = 1800V, IT ==
Solution
V, = 110 V, va = 60 V, I. == 20 A.
ay: == 0.025 x Va = 0.025 x 60 = 1.5 V
Va 60
R==-=-=311
10 20
From Eq. (5.48),
Va 60
k = - = - = 05455
V, 110 .
From Eq. (5.49),
Is = kla = 0.5455 x 20 == 10.91 A
alL = 0.05 x I. :: 0.05 x 20 == 1 A
M = 0.1 x 10 == 0.1 x 20 == 2 A
8. From Eq. (5.51), we get the value of L.:
VaWs - Va) 60 X (110 - 60)
Le = MIV, = 2 x 20 kHz x 110 = 681.82 ~H
From Eq. (5.53) we get the value of Ce:
2c == ,11
e ,lV, X 81 1.5 x 8 X 20 kHz == 8.33 ~F
L4
+
+
Vs 110 V
FIGURE 5.29
o~-----------+----------~--------~Buck converter.
5.12 Chopper Circuit Design 215
Vs
L
8
v, OV
O~----------------------------*-------~~------~
(a) Circuit
Vgj
2ov~______________1~________-L____--'
o 27.28 IlS SOIlS
(b) Control voltage
FIGURE 5.30
Buck chopper for PSpice simulation.
Assuming a linear rise of load current i ...
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Similar to Pk lab 5
Assignment 1 Description Marks out of Wtg() Due date .docx
Assignment 1
Description Marks out of Wtg(%) Due date
Assignment 1 200 20 28 August 2015
Part A: Comparators and Switching (5%)
(1) Signal limit detector
Use a 339 comparator, a single 74LS02 quad NOR gate and a +5V power supply only to
design a circuit which will detect when a voltage goes outside the range +2.5V to +3.5V
and such that an LED lights and stays lit. Provide a manual reset to extinguish the LED.
Design hints
1. The circuit has an analog input and a digital output so some form of comparator circuit
is required. There are two thresholds so two comparators are required, with the analog
input applied to both. This arrangement is sometimes known as a window detector.
2. Arrange the output of the comparators to be +5V logic levels, and combine the two
outputs logically to produce one signal which is for example, high for out-of-range, and
low for within-range.
3. Latch the change from in-range to out-of-range.
Design procedure
1. Start at the output and work backwards.
2. Select a latch circuit (flip-flop) and determine what combinations of inputs are needed to
latch and then reset it, ensuring that the LED is connected correctly with regard to both
logic and current flow.
3. Determine the logic needed to combine two comparator outputs in such a way as to
correctly operate the latch.
4. Choose comparator outputs which will correctly drive the logic. Remember that the
reference voltage at the input of the comparator may be at either the + or – input.
5. Choose resistors to provide the correct reference voltages.
Note: You will need to consult data for both the 74LS02 and the 339 (see data sheets).
Test
It is strongly recommended that you assemble and test your circuit.
(2) MOSFET Switching
Find out information on the operation of, and configuring of, MOSFETs to be used in
switching circuits. In particular note the differences between BJTs and MOSFETs in this
role. Draw up a table to highlight the differences and hence the pros and cons on each
device for particular situations (eg. Switching high-to-low or low-to-high (ie. P or N type),
high or low current switching, low or high voltage switching).
Consider the following BJT switching circuit. Analyse the operation of the circuit to
understand the parameters involved. Choose suitable replacement MOSFETs to be used
ELE2504 – Electronic design and analysis 2
instead of the output switching BJTs in the given circuit. Include any necessary circuit
changes for the new devices to operate so as to maintain the circuit’s required parameters.
Where Vcc = 12V and Relay resistance = 15Ω .
ELE2504 – Electronic design and analysis 3
Part B: Transistor amplifier design (6%)
Design and test a common emitter amplifier using the circuit shown and the selected
specifications.
Specifications
Get your own spec ...
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This document describes the theory and experimental procedure of a single stage BJT amplifier. It discusses the three common configurations of BJT amplifiers: common emitter, common base, and common collector. The experiment aims to differentiate the configurations, measure DC and AC parameters, and observe the voltage gain differences between common emitter and common collector circuits. Key results showed the common emitter configuration amplified the signal as expected, while the common collector configuration did not amplify and had a voltage gain close to unity.
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This document describes the design of an operational amplifier (op-amp) with specific gain and slew rate specifications. The design process involves choosing an architecture, then designing the transistor sizes and compensation network. An existing two-stage op-amp architecture is adapted. Transistor widths and lengths are calculated to meet the gain of 20,000 V/V and slew rate of 20 MV/sec. The schematic is drawn and simulated. The output is as expected but cannot drive the load, so an output buffer is added to minimize delay for larger loads.
506 267-276
This document describes testing of a boost rectifier for a back-to-back converter used in a doubly fed induction generator wind energy system. The design of the back-to-back converter components is explained, including selection of IGBT switches, DC link capacitor, and driver circuits. A 1 kW prototype was fabricated in the laboratory. Testing was performed on the rectifier sections and showed the boosting was obtained as required. A microcontroller was used to generate PWM pulses to control the IGBTs in the boost rectifier. Experimental results demonstrated boosting of the rectified voltages for various input voltages and pulse widths.
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The first sample paper contains three sections with questions about transducers, their working principles, characteristics and applications. The second sample paper similarly has three sections focusing on bioamplifiers, electrodes, and principles of measurement for parameters like blood flow and oxygen levels.
The third sample paper is a full question paper with six sections covering topics like biomedical signals, transducers, instrumentation amplifiers, electrodes, pressure and flow measurement techniques, and applications of Wheatstone bridge and potentiometer. Diagrams and calculations are required. The emphasis is on understanding principles of measurement and
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This document provides information about electronics and components such as the cathode ray oscilloscope (CRO), semiconductor diodes, and transistors. It contains:
1) An explanation of the uses and working principle of the CRO, including how to measure voltages and time intervals using the CRO.
2) Details on semiconductor properties and the p-n junction, including how diodes are used for rectification in half-wave and full-wave rectifier circuits.
3) The terminals and functions of transistors, as well as symbols for n-p-n and p-n-p transistors.
Proceeding - PANIC
The document summarizes a proposed experiment called TREK at the J-PARC facility in Japan. The experiment aims to search for violations of time reversal symmetry by measuring the transverse muon polarization (PT) in stopped kaon (K+) decays with high precision (10-4). An active polarimeter will be used to stop muons from K+ decays and detect the asymmetry in positron emissions to extract the T-violating parameter PT, which is predicted to be very small in the Standard Model but could indicate new physics if measured to be non-zero. The upgraded TREK detector design, including an active scintillating fiber target, electromagnetic calorimeter, tracking chambers, and active muon polarimeter, is described
Two stage op amp design on cadence
This report details the design of a two-stage operational amplifier (op-amp) in Cadence. It begins with hand calculations of component parameters. A schematic is plotted and simulated for DC and AC analysis. The initial design does not meet specifications, so component parameters are modified through several iterations until specifications are met. Finally, geometry optimization using Mosek in MATLAB is presented, though long calculation times prevented results. The report demonstrates the op-amp design process from initial calculations through simulation and optimization to meet specifications.
Ee395 lab 2 - loren - victor - taylor
This lab report examines two multi-stage BJT amplifier circuits (cascade and cascode) through simulation, calculation, and physical experimentation. Hand calculations, PSpice simulation, and experimental results showed close agreement for voltages, currents, and gains. The cascade circuit used one NPN and one PNP transistor in common-emitter configurations. The cascode used two NPN transistors in a transconductance amplifier followed by a current buffer. Both circuits demonstrated voltage and current amplification as intended. Minor discrepancies between simulation, calculation and experiment were due to component tolerances and measurement errors.
reference notes455647_1_EE460-Project-131.pdfKing Fahd Un.docx
reference notes/455647_1_EE460-Project-131.pdf
King Fahd University of Petroleum and Minerals
Department of Electrical Engineering
EE Power Electronics Project
Design of a DC Chopper
I. Design of an AC/DC converter with the following the specifications:
AC supply voltage VS = 230 V (rms), 60 Hz.
The DC output voltage V01(dc) = 48 V.
The ripple factor of the output voltage RFV 5%.
II. Design of step-down DC chopper with the following specifications:
Switching (or chopping) frequency, fs = 20 kHz.
Dc input supply voltage VS = 48 V dc, where as the source available is an ac with 230 V
(rms).
Load resistance R = 5 .
The DC output voltage V02(dc) = 12 V.
The peak-to-peak output ripple voltage, VC 2.5%.
The peak-to-peak inductor ripples current, IL 5%.
III. Calculation for both circuits:
(a) Determine the values of Le and Ce for the output LC-filter.
(b) Determine the (peak and rms) voltage ratings and the (average, rms, and the peak) current for
all components and devices.
(c) Verify your design calculation by using Pspice simulation.
Design AC/DC
Circuit
Design DC-DC
Chopper Circuit
AC 5
Output Load
The project will be due on Sunday December 22, 2013.
reference notes/455647_2_DC-20Converters-Design (1).pdf
....-ju"ncv
O.
214 Chapter 5 Dc-Dc Converters
Example 5.10
A buck converter is shown in Figure 5.29. The input voltage is V, == 110 V, the average load
age is Va == 60 V, and the average load current is la == 20 A. The chopping u
1 == 20 kHz. The peak-to-peak ripples are 2.5% for load voltage, 5% for load current, and
for filter Le current. (a) Determine the values of L" L, and Ceo Use PSpice (b) to verify the
suits by plotting the instantaneous capacitor voltage vc, and instantaneous load current iL ;
(c) to calculate the Fourier coefficients and the input current is. The SPICE model pax'ameters
the transistor are IS == 6.734f, BF = 416.4, BR == 0.7371, CJC == 3.638P, CJE::
TR == 239.5N, TF = 30L2P, and that ofthe diode are IS :: 2.2E-15, BV = 1800V, IT ==
Solution
V, = 110 V, va = 60 V, I. == 20 A.
ay: == 0.025 x Va = 0.025 x 60 = 1.5 V
Va 60
R==-=-=311
10 20
From Eq. (5.48),
Va 60
k = - = - = 05455
V, 110 .
From Eq. (5.49),
Is = kla = 0.5455 x 20 == 10.91 A
alL = 0.05 x I. :: 0.05 x 20 == 1 A
M = 0.1 x 10 == 0.1 x 20 == 2 A
8. From Eq. (5.51), we get the value of L.:
VaWs - Va) 60 X (110 - 60)
Le = MIV, = 2 x 20 kHz x 110 = 681.82 ~H
From Eq. (5.53) we get the value of Ce:
2c == ,11
e ,lV, X 81 1.5 x 8 X 20 kHz == 8.33 ~F
L4
+
+
Vs 110 V
FIGURE 5.29
o~-----------+----------~--------~Buck converter.
5.12 Chopper Circuit Design 215
Vs
L
8
v, OV
O~----------------------------*-------~~------~
(a) Circuit
Vgj
2ov~______________1~________-L____--'
o 27.28 IlS SOIlS
(b) Control voltage
FIGURE 5.30
Buck chopper for PSpice simulation.
Assuming a linear rise of load current i ...
Title of the ReportA. Partner, B. Partner, and C. Partner.docx
Title of the Report
A. Partner, B. Partner, and C. Partner
Abstract
The report abstract is a short summary of the report. It is usually one paragraph (100-200 words) and should include
about one or two sentences on each of the following main points:
1. Purpose of the experiment
2. Key results
3. Major points of discussion
4. Main conclusions
Tip: It may be helpful if you complete the other sections of the report before writing the abstract. You can basically
draw these four main points from them.
example: In this experiment a very important physical effect was studied by measuring the dependence of a quantity
V of the quantity X for two different sample temperatures. The experimental measurements confirmed the quadratic
dependence V = kX2 predicted by Someone’s first law. The value of the mystery parameter k = 15.4 ± 0.5 s was
extracted from the fit. This value is not consistent with the theoretically predicted ktheory = 17.34 s. This discrepancy
is attributed to low efficiency of the V -detector.
1. Introduction
This section is also often referred to as the purpose or
plan. It includes two main categories:
Purpose: It usually is expressed in one or two sen-
tences that include the main method used for accomplish-
ing the purpose of the experiment.
Ex: The purpose of the experiment was to determine
the mass of an ion using the mass spectrometer.
Background and theory: related to the experiment.
This includes explanations of theories, methods or equa-
tions used, etc.; for the example above, you might want to
explain the theory behind mass spectrometer and a short
description about the process and setup you used in the
experiment. It is important to remember that report needs
to be as straightforward as possible. You should comprise
only as much information as needed for the reader to un-
derstand the purpose and methods. Your should also pro-
vide additional information such as a hypothesis (what is
expected to happen in the experiment based on the theory)
or safety information. The main focus of the introduction
mainly focuses on supporting the reader to understand the
purpose, methods, and reasons for these particular meth-
ods.Purpose of the experiment
Example:
Calculation of the pressure coefficient Cp
From the lectures notes, Cp can be obtained by the eq.
(1)
− Cp =
P − P∞
1
2 ∗ ρ ∗ U2∞
(1)
Where P and P∞ are respectively the local pressure and
the atmosphere pressure far away. U∞ is the wind velocity
Preprint submitted to supervisor March 4, 2020
of the wind tunnel.
Calculation of the lift coefficient CL
First, the expression for the pressure force acting nor-
mal to the chord line is given in the lecture notes as eq.(2),
Cn =
∮
Cp(−n̂ ∗ ŷ)dl, (2)
with Cp the coefficient of lift and n̂ the unit normal
vector pointing out of the surface, ŷ is the unit vector in
the direction normal to the chord line. dl is the length of an
infinitesimal line element. Similarly, the axial component
can be express as eq.(3)
Ca ...
cosmic-ray-detection(2)
Cosmic rays originate from outside Earth's atmosphere and are detected using scintillators coupled to photomultiplier tubes (PMTs). The authors characterized each PMT by measuring detection rates while varying threshold levels and applied voltages to determine optimal operating parameters. Threshold scans revealed the minimum voltage required to detect particles above noise, while voltage scans showed detection peaks used to set the high voltage for each PMT. Statistical analysis accounted for measurement uncertainties. Data acquisition software converted pulse readings to binary for computer analysis, with words identifying run numbers and detection channels. Overall, adjusting PMT thresholds and voltages improved the quality of cosmic ray energy data collected.
Electric Circuits Lab Series RC Circuits Phase Angle, Phase Lag.docx
Electric Circuits Lab
Series RC Circuits: Phase Angle, Phase Lag, and Capacitors as Integrators
I.
Objectives:
After completing this lab experiment using, you should be able to:
1. Understand the effect of frequency on capacitive reactance.
2. Measure the impedance of an RC circuit.
3. Measure the phase angle and phase lag of an RC circuit using the oscilloscope.
4. Draw the impedance and voltage phasor diagrams.
5. Understand how a capacitor integrates current.
II.
Parts List:
1. Resistor 100 Ω, 1 kΩ, 6.8 kΩ
2. Capacitors 0.1 µF, 0.01 µF
III.
Procedures:
Part I:
1.
Connect the following circuit.
Figure 1: RC Circuit
2.
Connect one DMM across the resistor and one DMM across the capacitor. Set both DMMs to read AC voltage.
Measure the voltage drop across each component. Record the result in
Table 1.
3. Use Ohm’s law to
calculate the current flowing through the resistor. Since the circuit in Figure 1 is a series RC circuit, the same current will flow through the capacitor and the resistor.
Record the result in
Table 1.
Total current, I =
4.
Calculate the capacitive reactance using Ohm’s law. Record the result in
Table 2.
Capacitive Reactance, XC =
5. Now,
calculate the capacitive reactance value using the equation below.
Record the result in
Table 1 under Computed Reactance, XC.
Capacitive Reactance,
Capacitor C1
Voltage across, R
846 mV
Voltage across, C
583 mV
Total Current, I
0.846 mA
Capacitive Reactance, XC
686 Ω
Computed Reactance, XC
Table 1: Calculated and measured values
6.
Adjust the function generator frequency following the steps in
Table 2. Use the DMM to
measure the voltage across the resistor and the capacitor.
Record your measurements below.
Frequency (in Hz)
VR
(measured)
VC
(measured)
I =
(calculated)
XC =
(calculated)
XC =
(calculated)
300
983 mV
186 mV
0.983 mA
189 Ω
1k
846 mV
583 mV
0.846 mA
686 Ω
3k
884 mV
468 mV
0.884 mA
529 Ω
5k
953 mV
302 mV
0.953 mA
317 Ω
7k
975 mV
221 mV
0.975 mA
227 Ω
9k
985 mV
174 mV
0.985 mA
177 Ω
11k
990 mV
145 mV
0.990 mA
147Ω
13k
993 mV
121 mV
0.993 mA
122 Ω
15k
994 mV
105 mV
0.994 mA
106 Ω
Table 2: Calculated and measured values
7.
Plot the graph for
Frequency vs. VC.
(Use Excel or Word to Create the Plot)
Plot 1: Frequency vs. VC
Part II:
8.
Build the circuit shown in Figure 2.
Figure 2: Series RC Circuit
9.
Set the source voltage amplitude to
1.5 Vp and
frequency to
500 Hz.
10.
Connect Channel .
L-24(DK&SSG)(PE) ((EE)NPTEL) (4 files merged).pdf
This document discusses the SEPIC converter, a type of DC-DC converter. It begins by reviewing the basic Buck converter topology. It then describes how modifying the basic Boost converter by placing the load across the diode results in a Boost-Buck converter. However, this has the drawback of reversing the output polarity. The document then explains that interchanging the diode with the filter inductor in this modified Boost converter results in the SEPIC converter topology, which maintains the correct output polarity while providing Buck-Boost operation. Key features of the SEPIC converter are that it is a single-switch topology that can output a voltage greater than, less than, or equal to the input voltage.
EE452_Flyback Convert
This document describes the design of a DC/DC flyback converter project. It details the initial specifications of the converter including an input voltage of 10V DC and adjustable output voltage range of 5-15V DC. It outlines the preliminary calculations done to determine component values for the open-loop design. Simulation results are presented showing the converter can operate in buck and boost modes. The design of the closed-loop controller using a type 2K compensator is described and simulation waveforms are shown verifying stable voltage regulation. Hardware test plans are laid out to characterize the open-loop and closed-loop performance of the built converter.
DESIGN OF TWO-STAGE OP AMPS.pdf
The document outlines the design procedure for a two-stage operational amplifier (op amp) in CMOS technology. It begins by listing the design inputs and outputs. It then describes the steps in designing a CMOS op amp including determining the topology, compensation method, and transistor sizes. The document provides equations for analyzing key parameters of a two-stage op amp like gain, bandwidth, and common-mode range. It concludes with an example design problem demonstrating how to use the outlined procedure to design an op amp that meets given specifications.
Ijmsr 2016-14
The Journal of MC Square Scientific Research is published by MC Square Publication on the monthly basis. It aims to publish original research papers devoted to wide areas in various disciplines of science and engineering and their applications in industry. This journal is basically devoted to interdisciplinary research in Science, Engineering and Technology, which can improve the technology being used in industry. The real-life problems involve multi-disciplinary knowledge, and thus strong inter-disciplinary approach is the need of the research.
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Pk lab 5
- 1. Biopharmaceutics and PK Lab 5 Calculation of PK parameters using one and two compartment model: IV bolus. Dr Sameh Rabea
- 2. Remember For 1st order kinetic one-compartment the equation will be: Cp= (Cp) 0 e –kt Where: Cp: Y ; (Cp) 0 : intercept; t: X; k: -slope x 2.303; Slope= (logC2 – logC1)/t2-t1. Or Ke = ln (C1/C2)/t2-t1 The PK model: I.V. Central Ke injection Compartment Out. AUC= Cp0/ Ke Vdc= Dose/ Cp0. t ½= 0.693/ Ke.
- 3. For 1storder kinetic two-compartment the equation will be: Cp= A e –αt + B e –βt Where A: intercept of line 1 and B intercept of line 2; α: distribution rate constant and β: elimination rate constant.
- 4. The PK model: I.V. in Central K12 Peripheral Compartment Compartment inj. K 21 K2 Cp0= A + B K2 = Cp0 / ( A/ α + B/ β ) K12= A.B (β- α) 2 / Cp0 (A β + B α) K21= A β + B α / Cp0 .
- 5. AUC= A/α + B/β . t ½= 0.693/ β. Vd c= Dose/Cp0= Dose/ A+B. Vd area= Dose/AUC. β Vd ss = Vdc + (K12/K21) Vdc Vd tissue= Vd area – Vdc. Therefore: Vd area> Vd ss > Vdc> Vd tissue. But Vd ss is not affected by elimination, so its represents true volume of distribution. CL = Vdc. Ke or CL= Vdc. Β.
- 6. Problem # 1 A patient received 500 mg cefepime I.V bolus injection and numerous blood samples were drawn as the following:
- 7. Plotting Data Time (hr) Conc.( µ/ml) 0.5 38.2 1 21.6 2 11.6 4 5.0 8 1.4 12 0.2
- 8. A- Test the order of this data. B- Write your model Calculate as many PK parameter as possible.
- 9. Problem # 2 A patient received 300 mg I.V. dose of a drug. Several blood samples were collected and the following plasma concentrations were obtained:
- 10. Plotting Data Time (hr) Conc.( µ/ml) 0.2 5.6 0.4 4.6 0.6 3.8 0.8 3.2 1 2.8 2 1.8 3 1.35 4 1.2 5 1.06 24 0.0
- 11. Test the order of this data. Write the model. Calculate PK parameters.
- 12. Problem # 3 A patient received 350 mg I.V bolus dose of drug. Several blood samples were collected and the following plasma concentrations were obtained:
- 13. Plotting Data Time (hr) Conc. (µg/ml) 0.5 20.8 1 13.8 1.5 10 2 7.9 3 5.3 6 2.9 8 2 10 1.4
- 14. A- Draw diagrammatic presentation describing PK model , and write your equation.
- 15. Calculate the following PK parameters: A: B: α: β (Ke): t1/2 : AUC: Vdc: Vd area: