The document details a research project on Class-G headphone amplifiers as part of a Ph.D. thesis at the University of Pavia. It discusses various amplifier classes, focusing on the Class-G architecture, its implementation in 65nm CMOS technology, performance comparisons, and design considerations for improved specifications. The findings indicate that the Class-G amplifier demonstrates lower power consumption and meets stringent market requirements for signal-to-noise ratio and total harmonic distortion.

1. Università di Pavia - Dipartimento di Elettronica
Dottorato di Ricerca in Microelettronica - XXIII Ciclo
Class-G Headphones Amplifier
Ph.D. Candidate: Alex Lollio
TUTORE:
CHIAR.MO PROF. RINALDO CASTELLO
COORDINATORE:
CHIAR.MO PROF. FRANCO MALOBERTI

2. 1/28
Headphone audio amplifiers
Target application
Modern cellular phones incorporates music playback and
users may wish to use this feature for many hours
Typical operating conditions
Key objectives:
VHV • Single ended
• Low distortion
• RL = 32/16 Ω
• BW = 20Hz–20kHz
VIN • PO,MAX > 40mW (on • Low noise
16 Ω)
-VHV • High efficiency

3. Outline
• Headphone amplifier
(Class-AB, Class-D, Class-G PROs and CONs)
• Class-G headphone driver
(architecture, switching principle, distortion analysis)
• Prototype in 65nm CMOS technology
(implementation, results, comparison)
• Class G improved version
(new SNR Spec, proposed solution, results and comparison)
• Conclusions

4. Outline
• Headphone amplifier
(Class-AB, Class-D, Class-G PROs and CONs)
• Class-G headphone driver
(architecture, switching principle, distortion analysis)
• Prototype in 65nm CMOS technology
(implementation, results, comparison)
• Class G improved version
(new SNR Spec, proposed solution, results and comparison)
• Conclusions

5. 2/28
Headphone audio amplifiers
Alternative topologies
 Class AB (Linear amplifier)
PROs: Best linearity
No EMI problems
CONs: Low efficiency
Typically the preferred solution in headphone application
 Class D (Switching amplifier)
PROs: Best efficiency
CONs: Less linearity than class AB
EMI problems
Emerging solution in headphone application

6. 3/28
Headphone audio amplifiers
Alternative topologies
 Class G: It is a linear amplifier which uses two voltage supply
rails which switches to the appropriate voltage as required by
the instantaneous output voltage
VHV VHV
VLV VLV
VOUT VOUT
VIN -VLV
-VLV -VHV
-VHV
PROs: High efficiency but less than class D
High linearity but less than class AB
No EMI problems
CONs: It needs two voltage supply rails

7. 4/28
Class G
alternative topologies
 Series topology  Parallel topology
(classical) VHV
VHV • Two output
• Only one VLV
VLV stages work in
output stage
parallel
• Switches RL
are in series • No switches in
with the series with the
RL
power power transistors
transistors
• It needs a careful
switching circuit
-VLV
design
-VLV -VHV
-VHV This is the adopted solution

8. 5/28
Class G: working principle
VHV
Iout[A] HV stage
Iout[A] iHV LV stage
VLV
iLV iLV
t t
iHV iLV
iHV iLV
Switching
point
-VLV
-VHV
For Vout below the switching point the low voltage stage is active.
For Vout above the switching point both the low voltage and high voltage
stages drive the load (in different moments).

9. 6/28
Class G: switching distortion
Compared to class AB, class G has an additional source of
distortion.
Distortion
zoom in
Switching point
Distortion caused by the
Up to the switching point
the class G linearity is the switching
same as a class AB
9

10. 7/28
Class G: critical design choices
Switching point
• Switching point equal to VLV
level: (efficiency=78%)
Switching point
To achieve high far from the low
efficiency, it must be voltage supply
as close as possible
to the low voltage
supply
• Switching strategy: to minimize the distortion, switching must be as
smooth as possible
The implemented current based switching enables low distortion and
high efficiency

11. Outline
• Headphone amplifier
(Class-AB, Class-D, Class-G PROs and CONs)
• Class-G headphone driver
(architecture, switching principle, distortion analysis)
• Prototype in 65nm CMOS technology
(implementation, results, comparison)
• Class G improved version
(new SNR Spec, proposed solution, results and comparison)
• Conclusions

12. 8/28
Overall amplifier architecture
Main path R2
• Three stage
CM2 Switching opamp with
stage differential input
gm2 and single ended
-gm3L
output.
R1
gm1 • The two
VOUT identical second
R1 stages, gm2, and
R2 gm2 -gm3H RL
the third stages,
gm3L and gm3H,
CM1 CM2 work in parallel.
• Only the low voltage stage gm3L is supplied by the low voltage rail
±VLV. The rest of the circuit is supplied by the high voltage rail ±VHV

13. 9/28
Amplifier architecture: main path
VHV VLV
First stage
VHV Floating
battery
-VLV RL
-VHV VO
VHV
-VHV
Input pairs 13
gm1

14. 10/28
Amplifier architecture: main path
Second stage
VHV VLV
VHV Floating
battery
-VLV RL
-VHV VO
VHV
gm2
-VHV
14
Floating battery ref: Renirie, Langen, Huijsing, 1995

15. 11/28
Amplifier architecture: main path
LV stage
VHV gm3L VLV
VHV Floating
battery
-VLV RL
-VHV VO
VHV
HV stage -VHV
gm3H Third
15
stage

16. 12/28
Amplifier architecture: switching stage
conceptual schematic
PMOS VLV - VTH VO
VHV switching VLV
stage
VHV Floating
battery
-VLV RL
-VHV VO
VHV
NMOS -VHV
switching VO -VLV + VTH
stage

17. 13/28
Amplifier architecture: switching stage
conceptual schematic
PMOS VLV - VTH VO
VHV switching VLV
stage
VHV Floating
battery
-VLV RL
-VHV VO
VHV
-VHV
VO -VLV + VTH

18. 14/28
Switching principle details
VHV
VLV
iJL • Switching point sensing is in
voltage domain.
VHV
LV stage A differential pair compares the
output voltage to the switching
point voltage VLV-VTH
-VLV VOUT • The switching between the
VHV high voltage and low voltage
iJH output stage is current based.
VOUT
The switching circuit injects all
VLV - VTH its bias current into the gate of
the MOS to be switched off.
IBIAS HV stage
PMOS switching stage
-VHV

19. 15/28
Output currents during switching
Vout[V]
VLV • When VOUT is lower than the
VLV -VTH switching point (VLV-VTH) the
switching circuit enables the LV stage
and disables the HV stage
• When VOUT is higher than the low
t voltage supply VLV only the HV stage
Iout[A] drives the load
Output currents
iHV
iLV • When VOUT is between VLV-VTH and
VLV both stages drive the load
t

20. 16/28
Switching distortion:
Amplifier model during the switching
• We use a simplified linear model of the amplifier during the switching.
R2
CM1
CM2 This current is
used to
R1 represent the
VOUT disturbance
gm1 gm2 -gm3
generated by
RL
R1 R2 the switching
iJ stage.
Where

21. Outline
• Headphone amplifier
(Class-AB, Class-D, Class-G PROs and CONs)
• Class-G headphone driver
(architecture, switching principle, distortion analysis)
• Prototype in 65nm CMOS technology
(implementation, results, comparison)
• Class G improved version
(new SNR Spec, proposed solution, results and comparison)
• Conclusions

22. 17/28
Chip micrograph
• 65nm CMOS process
(1.8V analog transistors)
• 0.14mm2 active area per
channel
• Voltage supplies:
High voltage rail ±1.4V
Low voltage rail ±0.35V
• Switching point 50mV under
the low voltage supply
• Max load capacitance 1nF

23. 18/28
Measurement results:
Power dissipation versus output power
Fin=1kHz
RL=32Ω
23

24. 19/28
Measurement results:
THD+N and efficiency versus output power
• Sinusoidal
input signal (fin=1kHz)
• About 6dB extra distortion due to switching

25. 20/28
Performance summary and
comparison with literature
JSSC 09 ESSCIRC 06 ISCAS 09
This work
Parameter (Class AB) (Class AB) (Class D)
(Class G)
[1] [2] [3]
Technology 65nm 130nm 65nm 0.13um
±1.4V ±1V
Supply voltage 2.5V 3.6V
±0.35V ±0.6V
Quiescent power (per
0.41mW 1.2mW 12.5mW 1.8mW
channel)
Peak load power (16Ω) 90mW 40mW 53.5mW 50mW
-80dB @ -84dB @ -68dB @ -80dB @
THD+N @ PRMS (32Ω)
16mW 10mW 27mW (16Ω) 10mW
92dB (un-
SNR A-weighted 101dB - 96dB
weighted)
[1] Vijay Dhanasekaran, JSCC ‘09 [2] P. Bogner, ESSCIRC ’06
[3] Pillonet, ISCAS ‘09

26. 21/28
Performance comparison with products
This work MAX9725 TPA6141 LM48824
Parameter
(Class G) (Class AB) (Class G) (Class G)
1.4V with two 3.6V with 1 3.6V with 1
1.5V with one
Supply voltage charge pumps + 1 charge pump + charge pump +
charge pump
buck 1 buck 1 buck
Quiescent power (per 0.41mW + 0.3mW
1.57mW 2.16mW 1.62mW
channel) (2 CPs + 1 buck)
PSUP @ PL=0.1mW 0.87mW + 0.4mW - 4.5mW 3.24mW
PSUP @ PL=0.5mW 1.63mW + 0.6mW - 7.2mW 5.58mW
Peak load power 90mW 70mW
50mW 50mW 74mW
(16Ω) (CPs RON=2.5Ω)
THD+N @ PRMS
-80dB @ 16mW -84dB @12mW -80dB @20mW -69dB@20mW
(32Ω)
SNR A-weighted 101dB 92dB 105dB 102dB

27. Outline
• Headphone amplifier
(Class-AB, Class-D, Class-G PROs and CONs)
• Class-G headphone driver
(architecture, switching principle, distortion analysis)
• Prototype in 65nm CMOS technology
(implementation, results, comparison)
• Class G improved version
(new SNR Spec, proposed solution, results and comparison)
• Conclusions

28. 22/28
New Spec: increase the SNR of 10dB
3-stages improved performance
where
Aim: Classical approach:
increase the SNR increase gM1 and consequently CM1
ISCC ‘10 3-stages improved
SNR @ 1VRMS 100dB 110dB
Big
CM1 15pF 260pF area
CM2 4x18pF 4x18pF
PQ 0.41mW 0.55mW

29. 23/28
4-stages Feed Forward (FF) solution
• The additional stages
increase the open loop
gain of the amplifier at
low frequencies
• The stage gM11
dominates the noise
performance
Additional stages
Ref: A. Bosi et all. VDSL2 Analog Front End, ISSCC, 2009

30. 24/28
4-stages Feed Forward (FF) solution
• The amplifier cuf off
High frequency is gM1/CM1
freq path
• The GLOOP shows a
zero at
Low
freq path
High freq path gM1
Low freq path gM11/sC · gM12

31. 25/28
4-stages FF: GLOOP plot
Audio BW (20Hz-20kHz)
4-stages FF solution:
1. gM11 determines the noise performances
2. More open-loop gain in the audio BW

32. 26/28
4-stages FF: Less capacitors sizes
3-stages improved performance: Big
area
4-stages FF:
gM11 determines the noise performance
Audio BW (20Hz-20kHz)

33. 27/28
4-stages FF: Less switching distortion
3-stages: 4-stages FF:
Switching Switching
distortion distortion
4-stages FF shows higher switching distortion compression
We can reduce gM2 saving power consumption
We can reduce CM2 saving area
3-stages 4-stages FF
gM2 200uA/V 55uA/V We saved
additional 52pF
CM2 4x18pF 4x5pF
THD@1kHz -82dB -85dB

34. 28/28
Performance summary
3-stages
ISCC ‘10 4-stages FF
improved
SNR@1VRMS 100dB 110dB 110dB
CTOT 87pF 332pF 101pF
PQ 0.41mW 0.55mW 0.6mW
THD@1kHz -82dB -82dB -85dB
Conclusion:
The adopted solution shows the same performance as the 3-stages
one using 1/3 of total capacitors area paying only 10% of additional
power consumption.

35. Outline
• Headphone amplifier
(Class-AB, Class-D, Class-G PROs and CONs)
• Class-G headphone driver
(architecture, switching principle, distortion analysis)
• Prototype in 65nm CMOS technology
(implementation, results, comparison)
• Conclusions

36. Conclusions
• A class-G headphone driver has been presented. It shows 50%
less power consumption than the best competitor.
• The class-G improved version satisfies the most aggressive
market requirements (110dB of SNR and better than 80dB of
THD)
• The class-G improved version will be integrated in Dec 2010 into
a novel Marvell audio codec

37. Publications
• Marvell Patent Ref No. MP3391:
A. Lollio, G. Bollati, R. Castello, “CIRCUITS AND METHODS
FOR AMPLIFYING SIGNALS”
• A. Lollio, G. Bollati, R. Castello, “Class-G Headphone Driver in
65nm CMOS Technology”, Proc. ISSCC 2010, San Francisco,
7-11 Feb. 2010, pp.84-85
• A. Lollio, G. Bollati, R. Castello, “A Class-G Headphone
Amplifier in 65nm CMOS Technology” IEEE J. Solid-State
Circuits, vol. 45, no. 12, Dec. 2010.

38. Activities Summary
Seminari organizzati dal dottorato (3.8 CFU)
Scuole di Dottorato (12 CFU)
Corso Elementi di Elettronica di Potenza (5 CFU)
Corso di Misure Elettriche (5 CFU)
Tutorato di Elettronica (2 CFU)
Presentazione a Congresso Internazionale: ISSCC2010 (3 CFU)
Pubblicazione su rivista internazionale: JSSC2010 (4 CFU)
Presentazioni annuale sull’attività di ricerca svolta (1.5 CFU)
Totale CFU: 36.3

39. Buck and CPs:
Power consumption estimation (per channel)
2 Charge pumps PQ -> 0.2mW
1 Buck (80% efficiency), PL=0 Pdiss -> 0.1mW
1 Buck (80% efficiency), PL=0.1mW Pdiss -> 0.2mW
1 Buck (80% efficiency), PL=0.5mW Pdiss -> 0.4mW
Total power consumption
PQ -> 0.2mW+0.1mW = 0.3mW
PL=0.1mW -> 0.2mW+0.2mW = 0.4mW
PL=0.5mW -> 0.2mW+0.4mW = 0.6mW

40. Measurement results:
THD+N versus frequency
RL=32Ω
BW= 20Hz – 20 kHz

41. Measurement results:
Spectrum at different output power
PO=1mW PO=20mW
Fin=1kHz Fin=1kHz
41

42. References
[1] Vijay Dhanasekaran; Jose Silva-Martinez; Edgar Sanchez-Sinencio, "Design of
Three-Stage Class-AB 16Ohm Headphone Driver Capable of Handling Wide
Range of Load Capacitance," Solid-State Circuits, IEEE Journal of , vol.44, no.6,
pp.1734-1744, Jun 2009.
[2] P. Bogner, H. Habibovic and T. Hartig, ‘‘A High Signal Swing Class AB Earpiece
Amplifier in 65nm CMOS Technology,’’ Proc. ESSCIRC, pp.372-375, 2006.
[3] Pillonet, G., et al,”A 0.01% THD, 70dB PSRR Single Ended Class D using
variable hysteresis control for Headphone Amplifiers”, ISCAS 2009 pp.1181-1184.
[4] Maxim, ‘‘1V, Low-Power, DirectDrive, Stereo Headphone Amplifier with
Shutdown,’’ Rev. 3; 8/08, accessed on Jul. 7, 2009 < http://datasheets.maximic.
com/en/ds/MAX9725.pdf>
[5] Texas Instrument, ‘‘Class-G Directpath Stereo Headphone Amplifier,’’ 3/09,
accessed on Jul. 7, 2009 < http://focus.ti.com/lit/ds/symlink/tpa6141a2.pdf>
[6] National Semiconductor ”Class G Headphone Amplifier with I2C Volume Control,”
August 31,2009, accessed on Jan. 25, 2010
< http://www.national.com/ds/LM/LM48824.pdf >