power amplifier btech level content

1. POWER AMPLIFIERS

2. What is an amplifier?
• An amplifier is an electronic device that increases the voltage, current, or
power of a signal. Amplifiers are used in wireless communications and
broadcasting, and in audio equipment of all kinds. They can be categorized
as either weak-signal amplifiers or power amplifiers.

3. What is a Power Amplifier?
• A power amplifier (PA) converts a low-power signal to a higher power one.
Two common examples are audio amplifiers, used to drive loudspeakers
and headphones, and RF power amplifiers, such as those used in the final
stage of a transmitter.
• Power amplifiers are divided into classes based on the amplifier’s
characteristics. Classes A, AB, B, and C depend on their conduction angle,
which is the number of degrees in a cycle during which the amplifying
device conducts. Classes D and E are switching amplifiers. Classes D, DG,
and H are also common audio amplifiers that are similar to Class AB but use
different techniques to improve efficiency. Here we will be studying only
about A, B and AB stages.
https://www.analog.com/en/design-center/glossary/power-
amplifier.html

4. Introduction to “Output Stage”
• The role of an output stage is to provide power gain. It should have high
input impedance and low output impedance.
• An important function of the output stage is to provide the amplifier with a
low output resistance so that it can deliver the output signal to the load
without loss of gain. Since the output stage is the final stage of the amplifier,
it usually deals with relatively large signals. Thus the small-signal
approximations and models either are not applicable or must be used with
care. Nevertheless, linearity remains a very important requirement. In fact, a
measure of goodness of the design of the output stage is the total harmonic
distortion (THD) it introduces. This is the rms value of the harmonic
components of the output signal, excluding the fundamental, expressed as a
percentage of the rms of the fundamental.
https://wiki.analog.com/university/courses/electronics/electronics-lab-
13a

5. Total Harmonic Distortion
• THD is defined as the ratio of the equivalent root mean square (RMS)
voltage of all the harmonic frequencies (from the 2nd harmonic on) over the
RMS voltage of the fundamental frequency (the fundamental frequency is
the main frequency of the signal, i.e., the frequency that you would identify if
examining the signal with an oscilloscope). Equation 1 shows the
mathematical definition of THD (note that voltage is used in this equation,
but current could be used instead).

6. CLASSIFICATIONOF OUTPUT STAGES
• Output stages are classified according to the collector current waveform that
results when an input signal is applied.
• The class A stage, whose associated waveform is shown in figure, is biased at a
current Ic greater than the amplitude of the signal current, Îc.Thus the transistor
in a class A stage conducts for the entire cycle of the input signal; that is, the
conduction angle is 360° .

7. • In contrast, the class B stage, whose associated waveform is shown in figure, is
biased at zero dc current.Thus a transistor in a class B stage conducts for only half
the cycle of the input sine wave, resulting in a conduction angle of 180°

8. • An intermediate class between A and B, appropriately named class AB, involves
biasing the transistor at a nonzero dc current much smaller than the peak current
of the sine-wave signal. As a result, the transistor conducts for an interval slightly
greater than half a cycle

9. Class A Output Stage.
• Because of its low output resistance, the emitter follower is the most popular class
A output stage. Here we consider its large-signal operation.
Fig 1. :An emitter follower (Q1) biased
with a constant current I supplied by
transistor Q2.

10. • Figure 1 shows an emitter follower Q1 biased with a constant current I supplied by
transistor Q2 . Since the emitter current iE1 = I + iL , the bias current I must be
greater than the largest negative load current; otherwise, Q1 cuts off and class A
operation will no longer be maintained.
• The transfer characteristic of the emitter follower of Fig. 1 is described by
where vBE1 depends on the emitter current iE1 and thus on the load current iL.

11. Transfer Characteristics
Fig.2:Transfer characteristic of the emitter follower in Fig. 1.

12. Comments on the transfer
characteristics(fig.2)
• If we neglect the relatively small changes in vBE1, the linear transfer curve shown
in Fig. 2 results. As indicated, the positive limit of the linear region is determined
by the saturation of Q1; thus
vOmax =VCC –VCE1sat
In the negative direction, depending on the values of I and RL, the limit of the linear region
is determined either by Q1 turning off ( ) or by Q2 saturating
( )
The absolutely lowest (most negative) output voltage is that given by Eq. (11.4) and is
achieved provided the bias current I is greater than the magnitude of the corresponding
load current,

13. Maximum signal waveforms in the classA
output stage of Fig. 1.
• Consider the operation of the emitter-follower circuit of Fig. 1 for sine-wave input.
Neglecting VCEsat, we see that if the bias current I is properly selected, the output
voltage can swing from −VCC to +VCC with the quiescent value being zero, as
shown in Fig. (a).

14. • Figure (b) shows the corresponding waveform of vCE1 =VCC − vO

15. • Now, assuming that the bias current I is selected to allow a maximum negative
load current ofVcc/RL , that is I =Vcc/ RL.
• the collector current of Q1 will have the waveform shown in Fig. (c)

16. • Finally, Fig (d) shows the waveform of the instantaneous power dissipation in Q1
where, pD1 = vCE1 iC1

17. Points to be noted about emitter follower
biased circuit.
• The maximum power dissipation will occur when vO = −VCC, for in this case vCE1 is a
maximum of 2VCC (fig b) and pD1 = 2VCC I.
• A far more dangerous situation occurs at the other extreme of RL—specifically, RL
= 0. In the event of an output short circuit, a positive input voltage would
theoretically result in an infinite load current.
• The power dissipation in Q2 also must be taken into account in designing an
emitter follower output stage. Since Q2 conducts a constant current I, and the
maximum value of vCE2 is 2VCC, the maximum instantaneous power dissipation in Q2
is 2VCC I.This maximum, however, occurs when vO =VCC, a condition that would not
normally prevail for a prolonged period of time.

18. Power conversion efficiency of classA
output stage.
• The power-conversion efficiency of an output stage is defined as
• For the emitter follower of Fig. 1, assuming that the output voltage is a sinusoid with the
peak valueV_cap, the average load power will be
• Since the current in Q2 is constant (I), the power drawn from the negative supply isVCC I.
The average current in Q1 is equal to I, and thus the average power drawn from the
positive supply isVCCI.Thus the total average supply power is PS = 2VCCI
• Equations above can be combined to yield
• maximum efficiency is obtained when

19. • The maximum efficiency attainable is 25%. Because this is a rather low figure, the
class A output stage is rarely used in high-power applications (>1W). Note also
that in practice the output voltage swing is limited to lower values to avoid
transistor saturation and associated nonlinear distortion.Thus the efficiency
achieved in practice is usually in the 10% to 20% range.

20. CLASS B OUTPUT STAGE

21. A class B output stage.
Fig. 2
• It consists of a
complementary pair of
transistors (an npn and a
pnp) connected in such a
way that both cannot
conduct simultaneously

22. Circuit operation of Class B output stage
• When the input voltage vI is zero, both transistors are cut off and the output
voltage vO is zero. As vI goes positive and exceeds about 0.5V, QN conducts and
operates as an emitter follower. In this case vO follows vI (i.e., vO = vI − vBEN) and QN
supplies the load current. Meanwhile, the emitter–base junction of QP will be
reverse-biased by theVBE of QN, which is approximately 0.7V.Thus QP will be cut off.
• If the input goes negative by more than about 0.5V, QP turns on and acts as an
emitter follower. Again vO follows vI (i.e., vO = vI + vEBP), but in this case QP supplies
the load current and QN will be cut off.
• We conclude that the transistors in the class B stage of Fig. 2 are biased at zero
current and conduct only when the input signal is present.The circuit operates in a
push–pull fashion: QN pushes (sources) current into the load when vI is positive, and
QP pulls (sinks) current from the load when vI is negative.

23. Transfer Characteristics of Class B o/p stage
• A sketch of the transfer characteristic of the class B stage is shown in Fig. 3. Note
that there exists a range of vI centered around zero where both transistors are cut
off and vO is zero.This dead band results in the crossover distortion illustrated in
Fig. 4 for the case of an input sine wave.
Fig 3

24. Illustrating how the dead band in the class B
transfer characteristic results in crossover
distortion.
The effect of crossover distortion will be most
pronounced when the amplitude of the input
signal is small. Crossover distortion in audio power
amplifiers gives rise to unpleasant sounds.
Fig 4

25. Power-Conversion Efficiency
• To calculate the power-conversion efficiency, η, of the class B stage, we neglect
the crossover distortion and consider the case of an output sinusoid of peak
amplitudeV_capo .The average load power will be
• The current drawn from each supply will consist of half-sine waves of peak
amplitude (V_capo/RL .Thus the average current drawn from each of the two
power supplies will beV_capo/pi*RL. It follows that the average power drawn from
each of the two power supplies will be the same,
---eqn 1.1
---eqn 1.2

26. • and the total supply power will be
• Thus the efficiency will be given by
---eqn 1.4
---eqn 1.3

27. • It follows that the maximum efficiency is obtained when V_capo is at its maximum.
This maximum is limited by the saturation of QN and QP toVCC −VCEsat =VCC. At this
value of peak output voltage, the power-conversion efficiency is
• This value is much larger than that obtained in the class A stage (25%). Finally, we
note that the maximum average power available from a class B output stage is
obtained by substitutingV_capo =Vcc in Eq. (1.1)
---Eqn 1.5
---eqn 1.6

28. Power Dissipation
• Unlike the class A stage, which dissipates maximum power under quiescent
conditions (vO = 0), the quiescent power dissipation of the class B stage is zero.
When an input signal is applied, the average power dissipated in the class B stage
is given by PD = PS – PL
• Substituting for PS from Eq. (1.3) and for PL from Eq. (1.1) results in
---eqn 1.7

29. • From symmetry we see that half of PD is dissipated in QN and the other half in QP.
Thus QN and QP must be capable of safely dissipating 1/2PD watts. Since PD depends
onV_capo , we must find the worst-case power dissipation, PDmax. Differentiating Eq.
(1.7) with respect toV_capo and equating the derivative to zero gives the value of
V_capo that results in maximum average power dissipation as
• Substituting this value in Eq. (1.7) gives
• Thus,
---eqn 1.8
---eqn 1.9
---eqn 1.10

30. • At the point of maximum power dissipation, the efficiency can be evaluated by
substituting forV_capo from Eq. (1.8) into Eq. (1.4); hence, . Figure 5 shows a
sketch of PD (Eq. 1.7) versus the peak output voltageV_capo. Curves such as this are
usually given on the data sheets of IC power amplifiers.
Fig 5: Power dissipation of the class B output stage versus amplitude of the output sinusoid.

31. Observations from figure 5
• An interesting observation follows from Fig. 5: Increasing V_capo beyond 2Vcc/pi
decreases the power dissipated in the class B stage while increasing the load
power.The price paid is an increase in nonlinear distortion as a result of
approaching the saturation region of operation of QN and QP.Transistor saturation
flattens the peaks of the output sine waveform. Unfortunately, this type of
distortion cannot be significantly reduced by the application of negative feedback
and thus transistor saturation should be avoided in applications requiring lowTHD.

32. Reducing Crossover Distortion
Fig 6: Class B circuit with an op amp connected in a negative-feedback loop to reduce crossover distortion.
The crossover distortion of a class B output stage can be reduced substantially by
employing a high-gain op amp and overall negative feedback, as shown in Fig. 6

33. • The ±0.7-V dead band is reduced to volt, where A0 is the dc gain of the op amp.
Nevertheless, the slew-rate limitation of the op amp will cause the alternate
turning on and off of the output transistors to be noticeable, especially at high
frequencies. A more practical method for reducing and almost eliminating
crossover distortion is found in the class AB stage, which will be studied in the next
section.

34. Single-Supply Operation
• The class B stage can be operated from a single power supply, in which case the
load is capacitively coupled, as shown in Fig. 7. Note that to make the formulas
derived in Section “Power Dissipation” directly applicable, the single power supply
is denoted 2VCC
Fig 7:Class B output stage operated with a single power
supply

35. CLASSAB OUTPUT STAGE

36. • Crossover distortion can be virtually eliminated by biasing the complementary
output transistors at a small nonzero current.The result is the class AB output
stage shown in Fig. 8
Fig. 8 : Class AB output stage. A bias
voltageVBB is applied between the bases
of QN and QP, giving rise to a bias current
IQ given by Eq. (1.11).

37. • A bias voltageVBB is applied between the bases of QN and QP. For vI = 0, vO = 0, and a
voltageVBB/2 appears across the base–emitter junction of each of QN and QP.
Assuming matched devices,
---Eqn 1.11
• The value ofVBB is selected to yield the required quiescent current IQ.

38. Circuit Operation
• When vI goes positive by a certain amount, the voltage at the base of QN increases
by the same amount and the output becomes positive at an almost equal value
• The positive vO causes a current iL to flow through RL, and thus iN must increase;
that is,
--eqn 1.12
--eqn 1.13

39. • The increase in iN will be accompanied by a corresponding increase in vBEN (above the
quiescent value ofVBB/2). However, since the voltage between the two bases remains
constant atVBB, the increase in vBEN will result in an equal decrease in vEBP and hence in iP.
The relationship between iN and iP can be derived as follows:
• Thus, as iN increases, iP decreases by the same ratio while the product remains constant.
Equations (1.14) and (1.13) can be combined to yield iN for a given iL as the solution to the
quadratic equation
• From the equations above, we can see that for positive output voltages, the load current is
supplied by QN, which acts as the output emitter follower. Meanwhile,QP will be
conducting a current that decreases as vO increases; for large vO the current in QP can be
ignored altogether. For negative input voltages the opposite occurs
---eqn 1.14
---eqn 1.15

40. Transfer characteristic
• Since the transition is a smooth one, crossover distortion will be almost totally
eliminated as illustrated below
Fig 9:Transfer characteristic of the class AB stage

41. Output Resistance
• If we assume that the source supplying vI is ideal, then the output resistance of the
class AB stage can be determined from the circuit Fig.10 as
• where reN and reP are the small-signal emitter resistances of QN and QP, respectively.
At a given input voltage, the currents iN and iP can be determined, and reN and reP are
given by
---eqn 1.16
---eqn 1.17
Thus,

42. Fig 10: Determining the
small-signal output
resistance of the class AB
circuit of Fig. 8
• Since as iN increases, iP decreases, and vice versa, the output resistance remains approximately constant in the
region around vI = 0.This, in effect, is the reason for the virtual absence of crossover distortion.At larger load
currents, either iN or iP will be significant, and Rout decreases as the load current increases.

43. Biasing the Class AB Circuit
• we discuss two approaches for generating the voltageVBB required for biasing the
class AB output stage.
• Biasing Using Diodes
• Biasing Using theVBE Multiplier

44. Biasing Using Diodes
• We will discuss classAB circuit with bias voltage generated by a constant current passing
through diodes. In large-power circuits, output transistors are large, while biasing diodes
can be smaller.The quiescent current (IQ) is established in output transistors based on the
ratio (n) of their emitter-junction area to the biasing diodes' area. However, it's challenging
to achieve in discrete circuits.
• When the output stage sources current, the base current of one transistor increases,
demanding more current from the bias source.The bias current (IBIAS) must exceed the
maximum base drive for stability. Due to the limitation of n being small (due to IQ being
much smaller than peak load current), diodes cannot be significantly smaller than output
devices, posing a disadvantage.
• The diode biasing has an advantage in thermal stabilization.Quiescent power dissipation
raises transistor temperature, affectingVBE. Diode biasing, with close thermal contact,
compensates for this, protecting against thermal runaway by adjustingVBB with
temperature changes.This thermal contact is easily achieved in integrated circuits and in
discrete circuits by mounting bias diodes on the metal case of output transistors.

45. Biasing using diode (figure)
Fig 11: A class AB output stage
utilizing diodes for biasing. If the
junction area of the output devices,
QN and QP , is n times that of the
biasing devices D1 and D2 , a
quiescent current IQ = nIBIAS flows in
the output devices.

46. THERMAL DESIGN CONSIDERATION

47. JunctionTemperature
• Power transistors dissipate large amounts of power in their collector–base
junctions.The dissipated power is converted into heat, which raises the junction
temperature. However, the junction temperatureTJ must not be allowed to exceed
a specified maximum,TJmax; otherwise the transistor could suffer permanent
damage. For silicon devices,TJmax is in the range of 150°C to 200°C

48. Thermal Resistance
• Consider first the situation of a transistor operating in free air—that is, with no
special arrangements for cooling.The heat dissipated in the transistor junction will
be conducted away from the junction to the transistor case, and from the case to
the surrounding environment. In a steady state in which the transistor is
dissipating PD watts, the temperature rise of the junction relative to the
surrounding ambience can be expressed as,
TJ –TA = θJAPD ---eqn 1.18
• where θJA is the thermal resistance between junction and ambience,
having the units of degrees Celsius per watt.
• it is desirable to have, for the thermal resistance θJA, as small a value as
possible

49. Electrical equivalent circuit of the thermalconduction
process;TJ − TA = PDθJΑ.
Equation (1.18), which describes the thermal-conduction process, is analogous to Ohm’s law, which describes the
electrical-conduction process. In this analogy, power dissipation corresponds to current, temperature difference
corresponds to voltage difference, and thermal resistance corresponds to electrical resistance.Thus, we may
represent the thermal conduction process by the electric circuit shown in Fig. 12.
Fig. 12

50. Power DissipationVersusTemperature
• Transistor manufacturers provide specifications such as the maximum junction
temperature (TJmax), maximum power dissipation at a specific ambient temperature
(TA0, typically 25°C), and thermal resistance (θJA). Additionally, a graph (Fig. 13)
illustrates that the device can safely dissipate the rated power (PD0) at ambient
temperatures belowTA0. For higher ambient temperatures, power dissipation must
be derated according to a straight line on the graph, representing Eq. (1.18). IfTA0
and PD0 coincide, the junction temperature will reach the maximum allowed value,
TJmax. Substituting these quantities in Eq. (1.18) results in
--- eqn 1.19
which is the inverse of the slope of the power-derating straight line. At an ambient
temperatureTA, higher thanTA0, the maximum allowable power dissipation PDmax
can be obtained from Eq. (1.18) by substitutingTJ =TJmax; thus,

51. --- eqn 1.20
Fig 13: Maximum allowable power dissipation
versus ambient temperature for a BJT
operated in free air.This is known as a
“power-derating” curve.

52. Transistor Case and Heat Sink
• The thermal resistance between junction and ambience, θJA, can be expressed as
θJA = θJC + θCA ---eqn 1.21
• where θJC is the thermal resistance between junction and transistor case (package)
and θCA is the thermal resistance between case and ambience
• Although the circuit designer has no control over θJC (once a particular transistor
has been selected), the designer can considerably reduce θCA below its free-air
value (specified by the manufacturer as part of θJA). Reduction of θCA can be
effected by providing means to facilitate heat transfer from case to ambience.
• A popular approach is to bolt the transistor to the chassis or to an extended metal
surface. Such a metal surface then functions as a heat sink. Heat is easily
conducted from the transistor case to the heat sink; that is, the thermal resistance
θCS is usually very small.

53. • Also, heat is efficiently transferred (by convection and radiation) from the heat
sink to the ambience, resulting in a low thermal resistance θSA.Thus, if a heat sink
is utilized, the case-to-ambience thermal resistance given by,
θCA = θ CS + θSA ---eqn 1.22
Fig 14: Electrical analog of the thermal conduction
process when a heat sink is utilized
Fig 15: Maximum allowable power
dissipation versus transistor-case
temperature

54. • The electrical analog of the thermal-conduction process when a heat sink is
employed is shown in Fig. 14, from which we can write,
TJ –TA = PD(θJC + θCS + θSA) ---eqn 1.23
• If the device can be maintained at a case temperatureTC,TC0 ≤TC ≤TJmax, then the
maximum safe power dissipation is obtained whenTJ =TJmax,
---eqn 1.24
• The fig 15 graph simply states that for operation at ambient temperatures belowTA0, the
device can safely dissipate the rated value of PD0 watts

55. The BJT Safe Operating Area
1.Maximum Allowable Current (ICmax): Exceeding ICmax
continuously can lead to wire melting that bonds the device to
package terminals, posing potential damage.
2.Maximum Power Dissipation Hyperbola: This hyperbola
represents points where vCE iC equals PDmax at TC0. For
temperatures above TC0, power-derating curves should be
used to determine the lower PDmax and adjust the hyperbola
accordingly. Temporary excursions above the hyperbola are
allowed, but the average power dissipation should not
surpass PDmax.
3.Second-Breakdown Limit: Second breakdown results
from non-uniform current flow across the emitter–base
junction, causing current crowding and localized power
dissipation (hot spots). This phenomenon can lead to a
localized form of thermal runaway, increasing temperature
and current, ultimately risking junction destruction.
4.Collector-to-Emitter Breakdown Voltage (BVCEO): The
instantaneous vCE should never exceed BVCEO to prevent
avalanche breakdown of the collector–base junction
Fig 15: Safe operating area (SOA) of a BJT.

56. Short-Circuit Protection
• The class AB output stage in Figure 16 is equipped with short-circuit
protection to prevent damage when sourcing current. In the event of a short
circuit, the large current flowing through Q1 creates a voltage drop across
RE1, activating Q5. Q5 then diverts most of the IBIAS current, reducing Q1's base
drive to a safe level. While effective in preventing device damage, this
protection method introduces a disadvantage by causing a 0.5 V drop
across each RE during normal operation, reducing the output voltage swing.
However, the inclusion of emitter resistors also provides the added benefit of
safeguarding the output transistors against thermal runaway.

57. Fig 16.: A class AB output stage with short-circuit protection.The protection circuit
shown operates in the event of an output short circuit while vO is positive.

58. MOS PowerTransistors

59. Structure of the Power MOSFET
• At the present time the most popular structure for a power MOSFET is the
doublediffused or DMOS transistor shown in Fig. 17. As indicated, the device is
fabricated on a lightly doped n-type substrate with a heavily doped region at the
bottom for the drain contact.Two diffusions are employed, one to form the p-type
body region and another to form the n-type source region.
Fig. 17: Double-diffused vertical MOS transistor (DMOS).

60. • The DMOS (Double-Diffused Metal-Oxide-Semiconductor) device operates
by applying a positive gate voltage (vGS) greater than the threshold voltage
(Vt), inducing a lateral n-channel in the p-type body region beneath the gate
oxide. The resulting short channel, denoted as L, allows current conduction
by electrons from the source through this channel to the substrate and then
vertically down to the drain.
• Despite its short channel, the DMOS transistor exhibits a remarkably high
breakdown voltage, potentially reaching up to 600 V. This is attributed to the
depletion region between the substrate and body, which extends mainly into
the lightly doped substrate without spreading into the channel. The DMOS
transistor combines a high current capability, up to 50 A, with the mentioned
high breakdown voltage. The vertical structure of the device ensures
efficient utilization of silicon area.
• While an earlier V-groove MOS device structure, still in use, has lost ground
to the DMOS structure, particularly for high-power applications, the V-groove
MOSFET may still find relevance in high-frequency applications.

61. Characteristics of Power MOSFETs
• Power MOSFETs, despite having a different structure, share similarities with small-
signal MOSFETs. However, key differences exist:
1.Threshold Voltages: Power MOSFETs typically have threshold voltages ranging
from 2 V to 4 V.
2.Saturation Characteristics: In saturation, the drain current is related to vGS by the
square-law characteristic. Nevertheless, for higher vGS values, the iD–vGS
characteristic becomes linear due to the high electric field along the short channel,
causing velocity saturation. In this linear region, the iD–vGS relationship is constant,
implying a constant transconductance (gm).
3.Velocity Saturation: The linear portion of the iD–vGS characteristic results from
velocity saturation, where the high electric field limits the velocity of charge carriers.
4.Subthreshold Region: The iD–vGS characteristic includes a segment labeled
"subthreshold," which is of little significance for power devices. However, it is
relevant in very-low-power applications.

62. Fig 18:Typical iD–vGS characteristic for a power MOSFET
• The iD−vGS characteristic shown in Fig. 18 includes a segment labeled “subthreshold.”Though of
little significance for power devices, the subthreshold region of operation is of interest in very-low-
power applications

63. Temperature Effects
• Of considerable interest in the design of MOS power circuits is the variation of the
MOSFET characteristics with temperature, illustrated in Fig. 19.
Fig 19:The iD–vGS characteristic curve of a power MOS transistor (IRF 630,
Siliconix) at case temperatures of –55°C, +25°C, and +125°C

64. • For most power MOSFETs, there exists a specific range of vGS values
(typically between 4 V to 6 V) where the temperature coefficient of drain
current (iD) is zero. Beyond this range, particularly at higher vGS values, iD
demonstrates a negative temperature coefficient. This characteristic is
crucial as it indicates that a MOSFET operating beyond the point of zero-
temperature-coefficient is not prone to thermal runaway. However, at lower
currents (below the zero-temperature-coefficient point), the temperature
coefficient of iD is positive, making the power MOSFET susceptible to
thermal runaway.
• The positive temperature coefficient at low currents is attributed to the
relatively low vOV = (vGS - Vt) where Vt is the threshold voltage, and the
temperature dependence is dominated by the negative temperature
coefficient of Vt (ranging from -3 mV/°C to -6 mV/°C). This negative
coefficient causes vOV to increase with temperature, leading to a positive
temperature coefficient of iD. Given that class AB output stages are biased
at low currents, precautions must be taken to prevent thermal runaway
under these conditions.

65. Comparison with BJTs
• The power MOSFET does not suffer from second breakdown, which limits the safe
operating area of BJTs. Also, power MOSFETs do not require the large dc base-
drive currents of power BJTs. Note, however, that the driver stage in a MOS power
amplifier should be capable of supplying sufficient current to charge and discharge
the MOSFET’s large and nonlinear input capacitance in the time allotted. Finally,
the power MOSFET features, in general, a higher speed of operation than the
power BJT.This makes MOS power transistors especially suited to switching
applications—for instance, in motor-control circuits.

66. A Class AB Output Stage Utilizing Power
MOSFETs
• The class AB output stage in Fig. 20 utilizes a pair of complementary
MOSFETs and incorporates BJTs for biasing and the driver stage. The driver
stage employs complementary Darlington emitter followers (Q1 through Q4)
to provide low output resistance, essential for high-speed driving of the
output MOSFETs.
• A notable feature in the circuit is the biasing mechanism, employing two
VBE multipliers formed by Q5 and Q6, along with their associated resistors.
Q6 is in direct thermal contact with the output transistors, achieved by
mounting Q6 on their common heat sink. Through careful selection of the
VBE multiplication factor of Q6, the bias voltage VGG (between the gates of
the output transistors) is adjusted to decrease with temperature at the same
rate as the sum of the threshold voltages (VtN + |VtP|) of the output
MOSFETs. This design choice ensures the stabilization of overdrive
voltages and, consequently, the quiescent current of the output transistors
against temperature variations.

67. • Analytically,VGG is given by
• SinceVBE6 is thermally coupled to the output devices while the other BJTs remain at
constant temperature, we have
which is the relationship needed to determine R3/R4 so that .The otherVBE
multiplier is then adjusted to yield the value ofVGG required for the desired
quiescent current in QN and QP.

68. Fig 20: A class AB amplifier with MOS output transistors and BJT drivers. Resistor R3 is adjusted to
provide temperature compensation while R1 is adjusted to yield the desired value of quiescent current
in the output transistors. Resistors RG are used to suppress parasitic oscillations at high frequencies.
Typically, RG = 100 Ω.

69. END