This document provides information about Pentium real mode, including:
- Pentium real mode operates like an 8086 and allows legacy PCDOS/MSDOS systems to run. It can access the first 1MB of memory.
- It provides default segment registers (CS, DS, SS, ES, FS, GS), a 16-bit IP, and supports 6 active segments. It executes instructions from 8086 through Pentium except protected mode instructions.
- Data types include bytes, words, doublewords, signed/unsigned integers, BCD, strings, bits, pointers. Aligned data is faster than misaligned.
- The software model uses 16-bit registers and segments. General purpose registers
The document provides information about the 8086 and 80386 microprocessors. It discusses the 8086's 16-bit architecture and its 14 registers including the accumulator, base, count, and data registers. It also describes the 8086's addressing modes. For the 80386, it discusses its 32-bit architecture with 32-bit general purpose registers and segment registers. It outlines the 80386's register organization, flag register, descriptor registers, addressing modes including scaled indexed mode, control registers, and debug registers.
The document provides an overview of the 8086/8088 microprocessor architecture. It discusses the main components including the Bus Interface Unit (BIU) and Execution Unit (EU) that work in parallel to implement a two-stage pipeline. It describes the various registers like the segment, index, pointer, and flag registers. It also covers the different addressing modes used to calculate physical memory addresses from segment and offset values in real mode.
This document discusses different addressing modes used in microprocessor instructions. It begins by explaining the importance of understanding addressing modes for efficient software development. It then provides objectives for the chapter, which are to explain each data and program memory addressing mode, how to use them to form assembly statements, and how to select the appropriate mode for a given task. The document goes on to describe various data addressing modes like register, immediate, direct, displacement, indirect, base-plus-index, relative, and scaled-index. It also covers program memory addressing modes like direct, relative, and indirect. Examples are provided to illustrate how each mode works.
The 8086 microprocessor has a 16-bit arithmetic logic unit and data bus. It uses a 20-bit address bus to access up to 1 megabyte of memory addressed through segment registers. The 8086 has separate bus interface and execution units, with registers in each unit used for fetching instructions, computing addresses, and executing operations. Key registers include the instruction pointer, segment registers, and general purpose registers like the accumulator, base, count, and data registers.
This document discusses different memory addressing modes used in microprocessors, including real mode, protected mode, and flat mode addressing. It provides details on how addresses are calculated in real mode using segment registers and offsets. Protected mode addressing allows accessing memory above 1MB by using descriptor tables to map segment selectors to base addresses and limits. Various programming models for addressing program memory and stack memory are also covered.
The document discusses the register set and addressing modes of the Motorola 68020 microprocessor. It describes the 18 different addressing modes, including register direct, register indirect, address register indirect with index/displacement, memory indirect, program counter indirect, absolute, and immediate. It provides details on the types of registers in the 68020, which include 8 data registers, 7 address registers, 3 stack pointers, a program counter, condition code, and status and control registers.
The 8086 microprocessor has an architecture that separates it into a Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and handles address calculation on the buses. The EU decodes and executes instructions using its 16-bit ALU. The 8086 has 16 general purpose registers including 4 data registers (AX, BX, CX, DX) and segment/pointer registers. It also contains a flag register for storing status flags. The 8086 can queue up to 6 bytes of upcoming instructions to improve performance.
The document provides information about the 8086 and 80386 microprocessors. It discusses the 8086's 16-bit architecture and its 14 registers including the accumulator, base, count, and data registers. It also describes the 8086's addressing modes. For the 80386, it discusses its 32-bit architecture with 32-bit general purpose registers and segment registers. It outlines the 80386's register organization, flag register, descriptor registers, addressing modes including scaled indexed mode, control registers, and debug registers.
The document provides an overview of the 8086/8088 microprocessor architecture. It discusses the main components including the Bus Interface Unit (BIU) and Execution Unit (EU) that work in parallel to implement a two-stage pipeline. It describes the various registers like the segment, index, pointer, and flag registers. It also covers the different addressing modes used to calculate physical memory addresses from segment and offset values in real mode.
This document discusses different addressing modes used in microprocessor instructions. It begins by explaining the importance of understanding addressing modes for efficient software development. It then provides objectives for the chapter, which are to explain each data and program memory addressing mode, how to use them to form assembly statements, and how to select the appropriate mode for a given task. The document goes on to describe various data addressing modes like register, immediate, direct, displacement, indirect, base-plus-index, relative, and scaled-index. It also covers program memory addressing modes like direct, relative, and indirect. Examples are provided to illustrate how each mode works.
The 8086 microprocessor has a 16-bit arithmetic logic unit and data bus. It uses a 20-bit address bus to access up to 1 megabyte of memory addressed through segment registers. The 8086 has separate bus interface and execution units, with registers in each unit used for fetching instructions, computing addresses, and executing operations. Key registers include the instruction pointer, segment registers, and general purpose registers like the accumulator, base, count, and data registers.
This document discusses different memory addressing modes used in microprocessors, including real mode, protected mode, and flat mode addressing. It provides details on how addresses are calculated in real mode using segment registers and offsets. Protected mode addressing allows accessing memory above 1MB by using descriptor tables to map segment selectors to base addresses and limits. Various programming models for addressing program memory and stack memory are also covered.
The document discusses the register set and addressing modes of the Motorola 68020 microprocessor. It describes the 18 different addressing modes, including register direct, register indirect, address register indirect with index/displacement, memory indirect, program counter indirect, absolute, and immediate. It provides details on the types of registers in the 68020, which include 8 data registers, 7 address registers, 3 stack pointers, a program counter, condition code, and status and control registers.
The 8086 microprocessor has an architecture that separates it into a Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and handles address calculation on the buses. The EU decodes and executes instructions using its 16-bit ALU. The 8086 has 16 general purpose registers including 4 data registers (AX, BX, CX, DX) and segment/pointer registers. It also contains a flag register for storing status flags. The 8086 can queue up to 6 bytes of upcoming instructions to improve performance.
The 8086 microprocessor is a 16-bit processor that can address up to 1MB of memory using a segmented architecture. It is divided into a Bus Interface Unit that handles fetching instructions and transferring data, and an Execution Unit that decodes and executes instructions. The BIU uses segment registers to map the physical memory addresses and fetches multiple instructions using pipelining to overlap execution. The EU contains registers like AX, BX, CX for data and flags for status.
This document contains information about the 8086 microprocessor used in a college course on microprocessors and microcontrollers. It includes details about the architecture and components of the 8086 such as the bus interface unit, execution unit, registers, addressing modes, and instruction set. It also provides explanations of the different addressing modes used by the 8086 like register, immediate, direct, register indirect, base, indexed, and based indexed addressing.
This document provides information about the 8086 microprocessor used in microcontroller applications. It discusses the architecture of the 8086 including its registers, buses, addressing modes, instruction set and interrupts. Specifically, it outlines the features of the 8086, describes the bus interface unit and execution unit, and explains the different general purpose and segment registers as well as the various addressing modes supported by the 8086 architecture.
The instruction set of the 8051 microcontroller supports 8-bit operations and direct bit manipulation well suited for control applications. It has 256 instructions that use various addressing modes including register, direct, indirect, immediate, relative, and others. The instruction set includes arithmetic, logical, data transfer, boolean, and branching instructions. Conditional jumps and operations on individual bits allow for efficient programming of control flow and logic.
The document describes the 8086 16-bit microprocessor, including that it has a 20-bit address bus, 16-bit data bus, 29,000 transistors, and supports up to 1MB of memory. It discusses the 8086's architecture, which has a bus interface unit and execution unit, as well as its 14 16-bit registers including general purpose, pointer, index, and segment registers. The document also covers the 8086's instruction queue and concept of segmented memory addressing.
The document discusses the MIPS instruction set architecture. It describes the MIPS ISA's registers and memory organization, with 32 general purpose registers and 4GB of maximum memory addressed through bytes or words. It outlines the main instruction formats - R-format for arithmetic/logical instructions, I-format for data transfer, and J-format for jumps. The key MIPS instruction types are described, including how they manipulate data in registers or move it between registers and memory.
The document discusses the registers and addressing modes of the 8086 microprocessor. It describes the various registers - general purpose registers, pointer/index registers, segment registers, instruction pointer, and status flags register. It explains how the segment registers point to memory segments and how memory addresses are calculated. The instruction pointer acts as a program counter. There are seven addressing modes - register, immediate, direct, register indirect, based, indexed, and based indexed with displacement that specify the location of operands in memory using combinations of registers, displacements, and offsets.
The document summarizes the technical specifications and architecture of the Intel 8086 microprocessor, including:
- It was developed by Intel from 1976-1978 and had a 16-bit data bus, 20-bit address bus, and maximum clock speed of 5-10MHz.
- It had 1MB of addressable memory divided into four 64KB segments accessed via segment registers, and used 16-bit registers that limited direct addressing to 64KB of memory.
- Core components included the Accumulator, Base, Count, and Data registers, as well as other registers like the Instruction Pointer, Stack Pointer, Flags register, and segment registers.
The 8086 CPU is a 16-bit microprocessor with a 16-bit data bus, 20-bit address bus, and includes an ALU, BIU, and EU. The BIU fetches instructions and data from memory using segment registers and address pointers, while the EU decodes and executes instructions using general purpose registers like AX, BX, CX, DX, and flags. Memory is divided into segments of up to 64KB that can overlap. The 8086 supports various addressing modes to access memory locations.
The 8051 microcontroller has the following key features:
- 4K bytes of ROM, 128 bytes of RAM, four 8-bit I/O ports, and two 16-bit timers. It has pins for serial communication and can address up to 64K bytes each of external code and data memory. The 40-pin device uses 32 pins for I/O, with some pins having dual purposes. It uses a crystal oscillator connected to pins 18 and 19 to generate the clock signal. The 8051 has separate internal memory spaces for code and data and can access additional external memory. Special function registers like the Program Status Word and Accumulator control various functions.
The document discusses various addressing modes of the 8051 microcontroller including immediate, register, direct, register indirect, indexed, and bit addressing modes. It describes how each mode accesses memory and provides examples. It also covers special function registers, use of RAM as scratchpad memory, and bit addressing of ports, memory, and registers.
The document summarizes features and specifications of the Intel 8086 microprocessor. Some key points:
- The Intel 8086 is a 16-bit microprocessor that has a 20-bit address bus, allowing it to access up to 1MB of memory across 220 addresses. It has 14 16-bit registers and supports word sizes of 16 bits.
- The 8086 operates in minimum and maximum modes and can pre-fetch up to six instruction bytes to speed up execution. It requires a +5V power supply and has a 40-pin dual in-line package.
- Memory is byte-addressable, where each byte has a separate address ranging from 00000H to FFFFFH. The
The document discusses the architecture of the 8086/8088 microprocessors. It describes their data buses, address buses, memory support, and segment registers. The 8086 has a 16-bit data bus and 20-bit address bus, while the 8088 has an 8-bit data bus but the same 20-bit address bus. Both support up to 1MB of memory divided into segments of 64KB each. The 8086/8088 use a bus interface unit to access memory and I/O, and an execution unit to decode and execute instructions. They employ pipelining to improve performance by fetching the next instruction in parallel with executing the current one.
The document provides an introduction to ARMv8 Aarch64, a 64-bit instruction set introduced in ARMv8. Some key points:
- It uses 64-bit pointers and registers, with 32-bit fixed length instructions. It has 31 general purpose 64-bit registers.
- Many traditional ARM features are removed or modified, such as conditional execution, immediate shifts, load/store multiple. New features are added like large PC-relative addressing and branching.
- It has a load-acquire/store-release memory model and supports atomic operations. Advanced SIMD and floating point are now mandatory.
The document describes the Intel 8086 microprocessor. It is a 16-bit microprocessor that can access up to 1 MB of memory using a 20-bit address bus. It has a multiplexed address/data bus and requires a single phase clock. The 8086 has two main units - the Bus Interface Unit which handles bus transactions and the Execution Unit which decodes and executes instructions. It uses a segmented memory architecture with separate code, data, extra, and stack segments.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has a 20-bit address bus and supports 64K I/O ports. The 8086 uses a pipeline architecture with an Execution Unit that decodes and executes instructions, and a Bus Interface Unit that handles memory access and address calculation. The 8086's registers include general-purpose registers like AX, BX, CX and DX, as well as segment registers and flags that provide status information.
A microprocessor is an electronic component that is used by a computer to do its work. It is a central processing unit on a single integrated circuit chip containing millions of very small components including transistors, resistors, and diodes that work together. Some microprocessors in the 20th century required several chips. Microprocessors help to do everything from controlling elevators to searching the Web. Everything a computer does is described by instructions of computer programs, and microprocessors carry out these instructions many millions of times a second. [1]
Microprocessors were invented in the 1970s for use in embedded systems. The majority are still used that way, in such things as mobile phones, cars, military weapons, and home appliances. Some microprocessors are microcontrollers, so small and inexpensive that they are used to control very simple products like flashlights and greeting cards that play music when you open them. A few especially powerful microprocessors are used in personal computers.
The document discusses the history and evolution of microprocessors from early 4-bit processors of the 1970s to modern 64-bit processors. It covers early technologies like PMOS and NMOS and describes processors like the Intel 4004, 8008, 8080, and 8085. It also discusses the internal architecture of processors like the 8085 including components like the ALU, registers, program counter, and memory interfacing. Modern processors including the Pentium series and RISC processors are also briefly outlined.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has a 20-bit address bus and supports 64K I/O ports. The 8086 has two main units - the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU handles fetching instructions from memory and performing bus operations, while the EU decodes and executes instructions. The 8086 uses a segmented memory architecture with four segment registers - code, data, extra, and stack - to access the 1 MB address space.
The 80386 microprocessor was introduced by Intel in 1985. It had a 32-bit data bus and 32-bit address bus, allowing it to access up to 4GB of memory. It improved on the 80286 by including a memory management unit and paging capability, improving efficiency and reducing software overhead. The 80386 could operate in real, protected, and virtual modes and introduced concepts such as paging and virtual memory. It had enhanced addressing modes and data types compared to earlier processors.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
The 8086 microprocessor is a 16-bit processor that can address up to 1MB of memory using a segmented architecture. It is divided into a Bus Interface Unit that handles fetching instructions and transferring data, and an Execution Unit that decodes and executes instructions. The BIU uses segment registers to map the physical memory addresses and fetches multiple instructions using pipelining to overlap execution. The EU contains registers like AX, BX, CX for data and flags for status.
This document contains information about the 8086 microprocessor used in a college course on microprocessors and microcontrollers. It includes details about the architecture and components of the 8086 such as the bus interface unit, execution unit, registers, addressing modes, and instruction set. It also provides explanations of the different addressing modes used by the 8086 like register, immediate, direct, register indirect, base, indexed, and based indexed addressing.
This document provides information about the 8086 microprocessor used in microcontroller applications. It discusses the architecture of the 8086 including its registers, buses, addressing modes, instruction set and interrupts. Specifically, it outlines the features of the 8086, describes the bus interface unit and execution unit, and explains the different general purpose and segment registers as well as the various addressing modes supported by the 8086 architecture.
The instruction set of the 8051 microcontroller supports 8-bit operations and direct bit manipulation well suited for control applications. It has 256 instructions that use various addressing modes including register, direct, indirect, immediate, relative, and others. The instruction set includes arithmetic, logical, data transfer, boolean, and branching instructions. Conditional jumps and operations on individual bits allow for efficient programming of control flow and logic.
The document describes the 8086 16-bit microprocessor, including that it has a 20-bit address bus, 16-bit data bus, 29,000 transistors, and supports up to 1MB of memory. It discusses the 8086's architecture, which has a bus interface unit and execution unit, as well as its 14 16-bit registers including general purpose, pointer, index, and segment registers. The document also covers the 8086's instruction queue and concept of segmented memory addressing.
The document discusses the MIPS instruction set architecture. It describes the MIPS ISA's registers and memory organization, with 32 general purpose registers and 4GB of maximum memory addressed through bytes or words. It outlines the main instruction formats - R-format for arithmetic/logical instructions, I-format for data transfer, and J-format for jumps. The key MIPS instruction types are described, including how they manipulate data in registers or move it between registers and memory.
The document discusses the registers and addressing modes of the 8086 microprocessor. It describes the various registers - general purpose registers, pointer/index registers, segment registers, instruction pointer, and status flags register. It explains how the segment registers point to memory segments and how memory addresses are calculated. The instruction pointer acts as a program counter. There are seven addressing modes - register, immediate, direct, register indirect, based, indexed, and based indexed with displacement that specify the location of operands in memory using combinations of registers, displacements, and offsets.
The document summarizes the technical specifications and architecture of the Intel 8086 microprocessor, including:
- It was developed by Intel from 1976-1978 and had a 16-bit data bus, 20-bit address bus, and maximum clock speed of 5-10MHz.
- It had 1MB of addressable memory divided into four 64KB segments accessed via segment registers, and used 16-bit registers that limited direct addressing to 64KB of memory.
- Core components included the Accumulator, Base, Count, and Data registers, as well as other registers like the Instruction Pointer, Stack Pointer, Flags register, and segment registers.
The 8086 CPU is a 16-bit microprocessor with a 16-bit data bus, 20-bit address bus, and includes an ALU, BIU, and EU. The BIU fetches instructions and data from memory using segment registers and address pointers, while the EU decodes and executes instructions using general purpose registers like AX, BX, CX, DX, and flags. Memory is divided into segments of up to 64KB that can overlap. The 8086 supports various addressing modes to access memory locations.
The 8051 microcontroller has the following key features:
- 4K bytes of ROM, 128 bytes of RAM, four 8-bit I/O ports, and two 16-bit timers. It has pins for serial communication and can address up to 64K bytes each of external code and data memory. The 40-pin device uses 32 pins for I/O, with some pins having dual purposes. It uses a crystal oscillator connected to pins 18 and 19 to generate the clock signal. The 8051 has separate internal memory spaces for code and data and can access additional external memory. Special function registers like the Program Status Word and Accumulator control various functions.
The document discusses various addressing modes of the 8051 microcontroller including immediate, register, direct, register indirect, indexed, and bit addressing modes. It describes how each mode accesses memory and provides examples. It also covers special function registers, use of RAM as scratchpad memory, and bit addressing of ports, memory, and registers.
The document summarizes features and specifications of the Intel 8086 microprocessor. Some key points:
- The Intel 8086 is a 16-bit microprocessor that has a 20-bit address bus, allowing it to access up to 1MB of memory across 220 addresses. It has 14 16-bit registers and supports word sizes of 16 bits.
- The 8086 operates in minimum and maximum modes and can pre-fetch up to six instruction bytes to speed up execution. It requires a +5V power supply and has a 40-pin dual in-line package.
- Memory is byte-addressable, where each byte has a separate address ranging from 00000H to FFFFFH. The
The document discusses the architecture of the 8086/8088 microprocessors. It describes their data buses, address buses, memory support, and segment registers. The 8086 has a 16-bit data bus and 20-bit address bus, while the 8088 has an 8-bit data bus but the same 20-bit address bus. Both support up to 1MB of memory divided into segments of 64KB each. The 8086/8088 use a bus interface unit to access memory and I/O, and an execution unit to decode and execute instructions. They employ pipelining to improve performance by fetching the next instruction in parallel with executing the current one.
The document provides an introduction to ARMv8 Aarch64, a 64-bit instruction set introduced in ARMv8. Some key points:
- It uses 64-bit pointers and registers, with 32-bit fixed length instructions. It has 31 general purpose 64-bit registers.
- Many traditional ARM features are removed or modified, such as conditional execution, immediate shifts, load/store multiple. New features are added like large PC-relative addressing and branching.
- It has a load-acquire/store-release memory model and supports atomic operations. Advanced SIMD and floating point are now mandatory.
The document describes the Intel 8086 microprocessor. It is a 16-bit microprocessor that can access up to 1 MB of memory using a 20-bit address bus. It has a multiplexed address/data bus and requires a single phase clock. The 8086 has two main units - the Bus Interface Unit which handles bus transactions and the Execution Unit which decodes and executes instructions. It uses a segmented memory architecture with separate code, data, extra, and stack segments.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has a 20-bit address bus and supports 64K I/O ports. The 8086 uses a pipeline architecture with an Execution Unit that decodes and executes instructions, and a Bus Interface Unit that handles memory access and address calculation. The 8086's registers include general-purpose registers like AX, BX, CX and DX, as well as segment registers and flags that provide status information.
A microprocessor is an electronic component that is used by a computer to do its work. It is a central processing unit on a single integrated circuit chip containing millions of very small components including transistors, resistors, and diodes that work together. Some microprocessors in the 20th century required several chips. Microprocessors help to do everything from controlling elevators to searching the Web. Everything a computer does is described by instructions of computer programs, and microprocessors carry out these instructions many millions of times a second. [1]
Microprocessors were invented in the 1970s for use in embedded systems. The majority are still used that way, in such things as mobile phones, cars, military weapons, and home appliances. Some microprocessors are microcontrollers, so small and inexpensive that they are used to control very simple products like flashlights and greeting cards that play music when you open them. A few especially powerful microprocessors are used in personal computers.
The document discusses the history and evolution of microprocessors from early 4-bit processors of the 1970s to modern 64-bit processors. It covers early technologies like PMOS and NMOS and describes processors like the Intel 4004, 8008, 8080, and 8085. It also discusses the internal architecture of processors like the 8085 including components like the ALU, registers, program counter, and memory interfacing. Modern processors including the Pentium series and RISC processors are also briefly outlined.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has a 20-bit address bus and supports 64K I/O ports. The 8086 has two main units - the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU handles fetching instructions from memory and performing bus operations, while the EU decodes and executes instructions. The 8086 uses a segmented memory architecture with four segment registers - code, data, extra, and stack - to access the 1 MB address space.
The 80386 microprocessor was introduced by Intel in 1985. It had a 32-bit data bus and 32-bit address bus, allowing it to access up to 4GB of memory. It improved on the 80286 by including a memory management unit and paging capability, improving efficiency and reducing software overhead. The 80386 could operate in real, protected, and virtual modes and introduced concepts such as paging and virtual memory. It had enhanced addressing modes and data types compared to earlier processors.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
Rainfall intensity duration frequency curve statistical analysis and modeling...bijceesjournal
Using data from 41 years in Patna’ India’ the study’s goal is to analyze the trends of how often it rains on a weekly, seasonal, and annual basis (1981−2020). First, utilizing the intensity-duration-frequency (IDF) curve and the relationship by statistically analyzing rainfall’ the historical rainfall data set for Patna’ India’ during a 41 year period (1981−2020), was evaluated for its quality. Changes in the hydrologic cycle as a result of increased greenhouse gas emissions are expected to induce variations in the intensity, length, and frequency of precipitation events. One strategy to lessen vulnerability is to quantify probable changes and adapt to them. Techniques such as log-normal, normal, and Gumbel are used (EV-I). Distributions were created with durations of 1, 2, 3, 6, and 24 h and return times of 2, 5, 10, 25, and 100 years. There were also mathematical correlations discovered between rainfall and recurrence interval.
Findings: Based on findings, the Gumbel approach produced the highest intensity values, whereas the other approaches produced values that were close to each other. The data indicates that 461.9 mm of rain fell during the monsoon season’s 301st week. However, it was found that the 29th week had the greatest average rainfall, 92.6 mm. With 952.6 mm on average, the monsoon season saw the highest rainfall. Calculations revealed that the yearly rainfall averaged 1171.1 mm. Using Weibull’s method, the study was subsequently expanded to examine rainfall distribution at different recurrence intervals of 2, 5, 10, and 25 years. Rainfall and recurrence interval mathematical correlations were also developed. Further regression analysis revealed that short wave irrigation, wind direction, wind speed, pressure, relative humidity, and temperature all had a substantial influence on rainfall.
Originality and value: The results of the rainfall IDF curves can provide useful information to policymakers in making appropriate decisions in managing and minimizing floods in the study area.
artificial intelligence and data science contents.pptxGauravCar
What is artificial intelligence? Artificial intelligence is the ability of a computer or computer-controlled robot to perform tasks that are commonly associated with the intellectual processes characteristic of humans, such as the ability to reason.
› ...
Artificial intelligence (AI) | Definitio
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Discover the latest insights on Data Driven Maintenance with our comprehensive webinar presentation. Learn about traditional maintenance challenges, the right approach to utilizing data, and the benefits of adopting a Data Driven Maintenance strategy. Explore real-world examples, industry best practices, and innovative solutions like FMECA and the D3M model. This presentation, led by expert Jules Oudmans, is essential for asset owners looking to optimize their maintenance processes and leverage digital technologies for improved efficiency and performance. Download now to stay ahead in the evolving maintenance landscape.
Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
- Gain actionable insights into AWS IAM policies and roles, using hands on approach.
#Prerequisites:
- Basic understanding of AWS services and architecture
- Familiarity with cloud security concepts
- Experience using the AWS Management Console or AWS CLI.
- For hands on lab create account on [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
# Scenario Covered:
- Basics of IAM in AWS
- Implementing IAM Policies with Least Privilege to Manage S3 Bucket
- Objective: Create an S3 bucket with least privilege IAM policy and validate access.
- Steps:
- Create S3 bucket.
- Attach least privilege policy to IAM user.
- Validate access.
- Exploiting IAM PassRole Misconfiguration
-Allows a user to pass a specific IAM role to an AWS service (ec2), typically used for service access delegation. Then exploit PassRole Misconfiguration granting unauthorized access to sensitive resources.
- Objective: Demonstrate how a PassRole misconfiguration can grant unauthorized access.
- Steps:
- Allow user to pass IAM role to EC2.
- Exploit misconfiguration for unauthorized access.
- Access sensitive resources.
- Exploiting IAM AssumeRole Misconfiguration with Overly Permissive Role
- An overly permissive IAM role configuration can lead to privilege escalation by creating a role with administrative privileges and allow a user to assume this role.
- Objective: Show how overly permissive IAM roles can lead to privilege escalation.
- Steps:
- Create role with administrative privileges.
- Allow user to assume the role.
- Perform administrative actions.
- Differentiation between PassRole vs AssumeRole
Try at [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
Software Engineering and Project Management - Introduction, Modeling Concepts...Prakhyath Rai
Introduction, Modeling Concepts and Class Modeling: What is Object orientation? What is OO development? OO Themes; Evidence for usefulness of OO development; OO modeling history. Modeling
as Design technique: Modeling, abstraction, The Three models. Class Modeling: Object and Class Concept, Link and associations concepts, Generalization and Inheritance, A sample class model, Navigation of class models, and UML diagrams
Building the Analysis Models: Requirement Analysis, Analysis Model Approaches, Data modeling Concepts, Object Oriented Analysis, Scenario-Based Modeling, Flow-Oriented Modeling, class Based Modeling, Creating a Behavioral Model.
2. pbborole 2
Pentium Real Mode
• Features
• Software model
• MMU addressing mechanism
• Addressing modes and instructions
• Architecture
• Interrupts
• IO addressing
3. pbborole 3
Pentium Real Mode features
• Operates like a very high
performance 8086
• PCDOS or MSDOS operating system
works in real mode.
• Can access first 1M bytes of
memory(00000 – FFFFF)
• IP is 16 bit.
• Provides two additional segment
registers FS and GS.
4. pbborole 4
Pentium Real Mode features
• Default mode.
• Provides vector table.
• No protection among segments.
• Segments can be overlapped.
• The size of each segment is 64K bytes.
• Provides 6 active segments.
• 16 bit and 32 bit operands and addressing
allowed.
• Executes 8086, 80286,80386, 80486 and
Pentium instructions except protected
mode instruction.
5. pbborole 5
Pentium Data types
Byte
0
7
Byte
Low Byte
High Byte
0
7
8
15
Address n
Address n+1
Word
Byte 0
Byte1
Byte2
Byte3
0
7
8
15
16
23
24
31
Address n
Address n+1
Address n+2
Address n+3
Double word
n is even for aligned
n is divisible by 4
for aligned double word
6. pbborole 6
Pentium Data types
• Bytes, words and double words are
fundamental data types.
• Byte is present in any bank of memory or
IO.
• Byte has unique address.
• A word is formed by using two bytes.
• Each byte in the word has its own address.
Two addresses are acquired by each word.
The address of word is the lower address.
• Hence the number of words to be accessed
by microprocessor is reduced by 2.
7. pbborole 7
Pentium Data types
• A double word is two contiguous
word starting at any byte address.
• Each byte of a double word has
address.
• Hence each double word acquires
four addresses.
• The lower byte has least address
while higher byte has most address.
• The address of lower byte is the
address of double word.
• The number of double words is
reduced by 4.
8. pbborole 8
Pentium Aligned and misaligned
words
• Aligned Word.
• Address is always even.
• Lower byte is at lower
address (even) of the
word.
• Higher byte is at higher
address(odd) of the
word.
• Accesses one word within
one bus cycle.
• Bandwidth is very high.
• Lower byte is present on
lower data bus and higher
byte is present on higher
data bus.
• Swapping is not required.
• Misaligned word.
• Address is always odd.
• Lower byte is at lower
address (odd) of the
word.
• Higher byte is at higher
address(even) of the
word.
• Accesses one word in two
bus cycles.
• Bandwidth is reduced.
• Lower byte is present on
higher data bus and
higher byte is present on
lower data bus.
• Swapping is required.
9. pbborole 9
Pentium Aligned and misaligned
Double words
• Aligned double word.
• Address is evenly divisible
by 4. 1/4th aligned double
word.
• Byte 0 is present on D0-
D7,byte 1 is present on
D8-D15,byte2 is present
on D16 –D23 and byte3 is
present on D24 – D31
data lines.
• Accesses one double
word within one bus
cycle.
• Swapping is not required.
• Misaligned double word.
• Address is not evenly
divisible by 4. 3/4th
misaligned double word.
• Byte 0 is not present on
D0-D7,byte 1 is not
present on D8-D15,byte2
is not present on D16 –
D23 and byte3 is not
present on D24 – D31
data lines.
• Two bus cycles are
required.
• Swapping is required.
10. pbborole 10
Data Types - Signed
• Handles 8bit ,16 bit, 32 bit signed
numbers.
• Signed numbers are always
represented in 2’s compliment form.
• MSB indicates sign bit
11. pbborole 11
Data Type BCD
• Handles packed BCD numbers.
• Handles unpacked BCD numbers.
• Unpacked BCD is a byte. Lower nibble is
used to represent value of the BCD (0-9).
Upper nibble must be zero for multiplication
and division and any value for addition and
subtraction. The range of each unpacked
BCD is 0 to 9.
• Packed BCD is a byte. Lower nibble is lower
digit and upper nibble is higher digit. The
range is 00 to 99
12. pbborole 12
Data Type String
• Contiguous sequence of bytes,words or
double words.
• A string may contain from zero bytes to
232-1 bytes.
• Bit string is contiguous sequence of bits.
A bit string may begin at any bit position
of any byte and may contain up to 232 –1
bits.
13. pbborole 13
Data Types bit & pointer
• Bit field is contiguous sequence of bits. A
bit field may begin at any bit position of any
byte and may contain up to 32 bits.
• Near Pointer is a 32 bit logical address. Near
pointer is an offset within a segment
• Far Pointer is a 48 bit logical address. It has
two components viz. 16 bit segment selector
and 32 bit offset.
14. pbborole 14
Pentium software model
• Application programming model
• System programming model
• Software compatibility
• Instruction Set.
15. pbborole 15
Pentium software model - Real
IP 16 bit
CS 16 bit
DS 16 bit
SS 16 bit
ES 16 bit
FS 16 bit
GS 16 bit
MODULE
CODE
MODULE
DATA
STACK
DATA
STRUCT1
DATA
STRUCT2
DATA
STRUCT3
16. pbborole 16
IP & Segment Registers
• Instruction pointer is 16 bit (Real mode).
• IP is always used in conjunction with CS to
access instructions.
• Never used as operand register.
• Holds offset address of an instruction.
• Code segment register is used to hold
segment address of an instruction.
• IP value is changed by branch instruction
• CS value is changed by only intersegment
branch instruction, interrupts and
exception.
17. pbborole 17
Segment registers
• Stack segment register holds segment address
of stack memory.
• All stack operations use SS to locate stack.
• DS, ES, FS, GS are four data segment registers.
• Used to access different data structures.
• Hold segment addresses of data structures.
19. pbborole 19
General purpose registers
• Used as general purpose registers to store
operands of arithmetic and logical operations.
• Can be used to store result.
• Can be used in data transfer operations.
• Can be used in byte(H &L). 16 bit (X) and 32 bit(E)
operations.
• EAX and EDX are used in multiply and divide
instructions, result correction, load/store flags.
• EAX and EDX are used in IO operations.
• EAX is used in string operations.
• AL and EBX are used in translate operations.
• ECX is used in loop, repeat, rotate and shift
operations.
21. pbborole 21
General Purpose Register
• ESP is used in conjunction with SS to
access stack in LIFO mode.
• All these registers are used in arithmetic
and logical operations.
• Used to store operands and results.
• All 8 general purpose registers can be
used in offset address calculations.
• All 8 general purpose registers can be
used as base registers.
• All 8 except ESP registers can be used as
Index registers.
22. pbborole 22
Status Register
• Provides three types of flags viz. status
flags,control flags and machine flags.
• System flags are not available in real
mode.
• Control flags Interrupt Enable,Direction
flag and Trap are available.
• Status flags are Overflow, Sign, Zero, AC,
P and C.
23. pbborole 23
MMU Real mode
• Provides 1 Mbytes + 64K byte memory
space for an 8086 program.
• Offset address is added into segment
address as shown below
• XXXX0
• +YYYY
• ZZZZZ
• The resulting address has 21 bits.
• There is possibility of carry when the base
address is added to the effective address.
• In 8086 carry bit is truncated. But in
80386,486,Pemtium the carry bit is stored
in bit position 20.
24. pbborole 24
MMU Real Mode
• 32 bit effective address can be generated
but the value of 32 bit address may not
exceed 65535 without causing an
exception.
• For fully compatibility with 80286 real
mode pseudo protection faults(INT12 or
13) will occur if an effective address is
generated outside the range 0 through
65,535.
• Total number of segments is 16.
25. pbborole 25
MMU Real Mode
• In default mode, the operand size
and addressing is 16 bit.
• Operand size Prefix and Address size
prefix is required for 32 bit operand
and 32 bit address respectively.
28. pbborole 28
Pentium stack
• Saves either words or double words not byte.
• Operates in LIFO mode.
• Saves words from higher address to lower
address.
• Reads words from lower address to higher
address.
• SP is always used in conjunction with SS to point
stack.
• Current stack location is called TOP of the stack.
• PUSH, POP,CALL RET, INT use LIFO stack.
• For word operation it increments/decrements SP
by 2. For double word operation it
increments/decrements SP by 4. For high
performance SP should point aligned location.
29. pbborole 29
Pentium stack
• Base pointer can be used to pass parameters
to the subroutine via stack.
• Base pointer uses stack in random mode.
(Stack frame)
• SP is not affected due to parameter passing.
• Always RAM.
• Can use SP or ESP. But physical address
should not be greater than FFFFFH.
32. pbborole 32
Pentium Instruction format
• The length of instruction varies from 1byte to 14 bytes.
• There are over 100000 variations of machine language
instructions.
• Two types – 16 bit and 32 bit.
• Format consists of Prefixes, opcode, addressing mode,
scaled index, displacement and immediate bytes.
• 16 bit instruction format is used to execute 8086 and 80286
programs.
• 32 bit format is used to execute 80386 and Pentium
programs.
• Operands are located in register, instruction, memory or
IO.
• Many instructions have two or more addressing modes.
33. pbborole 33
Pentium Instruction format
Address size
0-1 byte
Prefix
Operand size
0-1 byte
prefix
Opcode
1-2 bytes
Essential
Addressing
Mode 0-1 byte
Scaled index
0-1byte
Optional
Optional
Displacement
0-4 bytes
Optional
Immediate
0-4 bytes
Optional
Other prefixes may be added
34. pbborole 34
Pentium Instruction format
• Prefixes – These are optional bytes.
• One or more bytes preceding an
instruction that modify the operation
of the instruction.
• Types of prefixes –
• Segment override prefix- overrides
default segment register selection.
35. pbborole 35
Default Segment register
selection
Memory Segment
register
Selection rule
Instruction CS Automatic with
instruction fetch IP is
used
Stack SS LIFO uses SP. Random
uses BP
Local Data DS All Data memory
accesses except
destination string
Destination
string
ES Destination string
36. pbborole 36
Segment override prefix
• This prefix byte is used to change the
segment register of data memory except
destination string and stack memory in
random mode.
• Other default segment registers are not
affected like instruction fetch, LIFO stack,
destination string.
• All six segment registers can be used to
access data memory.
37. pbborole 37
Prefixes
• Address size prefix(67H) switches between
32 bit and 16 bit address generation.
• Operand size prefix(66H)switches between
32bit and 16 bit operands.
• Repeat prefix is used in string operation.
Repeat next instruction until CX becomes
zero.
38. pbborole 38
Instruction format
• Opcode – Selects the operation
• One or two bytes.
• Opcode table- Higher nibble of opcode byte
selects row of the table while lower nibble
selects column of the table.
• If the first byte of opcode is OFH then
second opcode byte is used to select row
and column of the opcode table.
• Three bits of opcode may be present in
addressing mode byte.
39. pbborole 39
Opcode
• Format of one byte opcode:
D W
Opcode bits
D =0 R/M is destination and REG is source.
D=1 R/M is source and REG is destination.
R/M and REG are bits of addressing mode byte.
If addressing mode byte is not present then D bit is opcode bit.
W bit is used to select byte,word or double word.
In 16 bit operand size mode, W=0 for byte W=1 for word
In 32 bit operand size mode, W =0 for byte W=1 for double word.
40. pbborole 40
Opcode for segment register
2bit Sreg2 present in opcode byte while Sreg3 is present in
Opcode field of addressing mode byte.
2 bit Sreg2 format:-
Sreg2 2bit Segment register selected
00 ES
01 CS
10 SS
11 DS
41. pbborole 41
Opcode for segment register
2bit Sreg2 present in opcode byte while Sreg3 is present in
Opcode field of addressing mode byte.
3 bit Sreg3 format:-
Sreg3 3bit Segment register selected
000 ES
001 CS
010 SS
011 DS
100 FS
101 GS
42. pbborole 42
Addressing mode byte
• Addressing mode byte indicates type of
addressing mode.
• Indicates location of operands.
• Indicates the way of effective address
computation.
• Indicates source and destination operands.
• Optional.
• Normally not present in implied addressing
mode with special register.
• For Single operand instruction, three bit
field REG is used as opcode field.
44. pbborole 44
Format
• MOD (2bit) field indicates whether the
operand is located in register or memory.
• MOD = 11 -> Register, MOD 11-> Memory
• MOD = 00 -> No displacement
• MOD = 01-> 8BIT signed displacement(2’s
complement).
• MOD =10-> 16 BIT unsigned
displacement(16 bit addressing mode).
• 32 BIT unsigned displacement ( 32 bit
addressing mode).
45. pbborole 45
Format
• REG – Three bit field indicates either
source or destination register
depending upon D bit of opcode in
two operand operation.
• REG indicates name of register.
• Name of register depends upon W bit
of opcode.
• In single or no operand instruction,
REG functions as opcode field.
46. pbborole 46
REG format
16 bit operand size mode:
REG or
R/M(MOD =11)
W =0 (byte) W=1 (Word)
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI
47. pbborole 47
REG format
32 Bit operand size:
REG or
R/M(MOD =11)
W =0 (byte) W=1 (DWord)
000 AL EAX
001 CL ECX
010 DL EDX
011 BL EBX
100 AH ESP
101 CH EBP
110 DH ESI
111 BH EDI
48. pbborole 48
R/M Format
• R/M(Register/Memory) is a 3 bit field.
• When MOD = 11 R/M -> Register else R/M ->
Memory.
• When MOD = 11 R/M indicates either source
or destination register, depending upon D
bit of opcode in two operand instruction.
• When MOD = 11 R/M indicates name of
register.
• When MOD = 00, 01 or 10 R/M indicates
effective address computation.
50. pbborole 50
R/M format
32 bit addressing mode:
R/M MOD =00 MOD =01 MOD =10
000 DS:[EAX] DS:[EAX+disp8] DS:[EAX+disp32]
001 DS:[ECX] DS:[ECX+disp8] DS:[ECX+disp32
]
010 SS:[EDX] SS:[EDX+disp8] SS:[EDX+disp32]
011 SS:[EBX] SS:[EBX+disp8] SS:[EBX+disp32]
100
scale
d
DS:[base+(
scaleinde
x)]
DS:[{base+(scal
e
index)}+disp8]
DS:[{base+(scal
e
index)}+disp32]
101 DS:[direct] SS:[EBP+disp8] SS:[EBP+disp32]
110 DS:[ESI] DS:[ESI+disp8] DS:[ESI+disp32]
111 DS:[EDI] DS:[EDI+disp8] DS:[EDI+disp32]
51. pbborole 51
Scaled index byte
• Required in scaled indexed addressing
mode.
• Applicable in 32 bit addressing mode.
• R/M = 100 and MOD = 00,01,10.
• Effective address is {base+scale*index}.
• Base value is stored in any 32 bit register.
• Index value is stored in any 32 bit register
except ESP.
52. pbborole 52
Scale Index Base format
S S
Index Base
SS -> Scale or multiplication factor
SS=00 -> 1
SS=01-> 2
SS=10 -> 4
SS=11-> 8
53. pbborole 53
Scale Index Base format
Base Effective address
000 DS:[EAX+(SCALE INDEX)]
001 DS:[ECX+(SCALE INDEX)]
010 DS:[EDX+(SCALE INDEX)]
011 DS:[EBX+(SCALE INDEX)]
100 SS:[ESP+(SCALE INDEX)]
101 DS:[d32+(SCALE INDEX)] No base
register is selected.
110 DS:[ESI+(SCALE INDEX)]
111 DS:[EDI+(SCALE INDEX)]
Format for base field (MOD =00):
54. pbborole 54
Scale Index Base format
Base Effective address
000 DS:[EAX+(SCALE INDEX)+ disp8]
001 DS:[ECX+(SCALE INDEX)+ disp8]
010 DS:[EDX+(SCALE INDEX)+ disp8]
011 DS:[EBX+(SCALE INDEX)+ disp8]
100 SS:[ESP+(SCALE INDEX)+ disp8]
101 SS:[EBP+(SCALE INDEX)+ disp8]
110 DS:[ESI+(SCALE INDEX)+ disp8]
111 DS:[EDI+(SCALE INDEX)+ disp8]
Format for base field (MOD =01):
55. pbborole 55
Scale Index Base format
Base Effective address
000 DS:[EAX+(SCALE INDEX)+ disp32]
001 DS:[ECX+(SCALE INDEX)+ disp32]
010 DS:[EDX+(SCALE INDEX)+ disp32]
011 DS:[EBX+(SCALE INDEX)+ disp32]
100 SS:[ESP+(SCALE INDEX)+ disp32]
101 SS:[EBP+(SCALE INDEX)+ disp32]
110 DS:[ESI+(SCALE INDEX)+ disp32]
111 DS:[EDI+(SCALE INDEX)+ disp32]
Format for base field (MOD =10):
56. pbborole 56
Scale Index Base format
INDEX INDEX REGISTER
000 EAX
001 ECX
010 EDX
011 EBX
100 NO INDEX REGISTER
101 EBP
110 ESI
111 EDI
If Index =100 then SS must be 00 else effective address is
•undefined
57. pbborole 57
Displacement
• Optional byte.
• If mod =00 or 11, then no displacement.
• If mod =01, the displacement is 8 bit signed. The 8 bit
signed displacement is either +ve or –ve(2’s compliment)
• If mod =10 and 16 bit addressing mode, then the
displacement is unsigned 16 bit(two bytes). This
displacement is always +ve. 1st byte is lower byte.
• If mod =10 and 32 bit addressing mode, then the
displacement is unsigned 32 bit(4bytes). This displacement
is always +ve. 1st byte is lower byte.
• In direct addressing (e.g. r/m =110 and mod =00 and 16 bit
addressing ), the displacement is 16 bit and treated as
offset address. In 32 bit addressing (r/m =100,mod
=00,base =101, the 32 bit displacement is added into scale
indexed.
58. pbborole 58
Immediate Data
• Present in immediate addressing mode.
• Either byte, word or double word
depending upon w bit and operand size
prefix.
• Can be loaded into register or memory
59. pbborole 59
Instruction format
• One mnemonic may have two or
more opcodes.
• Two types of instructions viz. single
operand and two operand.
• In two operand either destination or
source must be present in
register(except string instructions).
• The size of source operand must be
same as that of destination operand.
60. pbborole 60
Addressing modes
• Way of locating operands.
• Operands are located in register,
instruction data memory, stack
memory and IO.
• Indicates the way of effective
address computation.
61. pbborole 61
Addressing modes
• Three types addressing modes – Data, memory
and IO.
• Data addressing modes- Used to process
operands.
• Used by arithmetic, logical and data transfer
instructions.
• All registers except IP, data memory and stack
memory are used.
• Classified into the following categories- Register,
immediate and memory addressing modes.
• Length of instruction varies from 1 byte to 14
bytes.
62. pbborole 62
Register addressing modes
• In one operand instruction, operand is
located in register.
• Used in arithmetic,logical and data
transfer operations.
• The operand is 1byte,2bytes or 4 bytes.
• In two operand instruction, both operands
are located in registers.
• The mod = 11 .
• Two types of formats – one operand and
two operands.
63. pbborole 63
One operand
• Opcode is 1 byte or 2 bytes.
• Length of instruction varies from 1 byte to 3 bytes.
• Two types short and long instructions.
• Short instruction contains only opcode.
• Long instruction contains addressing mode byte.
• In Addressing mode byte OPCODE field is used
instead of REG field.
• The R/M field indicates register(Long).
• Opcode byte indicates register(short).
64. pbborole 64
Two operand
• D bit of opcode indicates source and
destination.
• The length of instruction from 2 byte or 3 byte.
• Addressing mode byte is always present.
• R/M indicates source or destination register.
• REG field indicates destination or source
register.
• Segment register and data registers are
distinguished by opcodes.
• Segment register opcode has no w bit.
65. pbborole 65
Registers
Operand size
Register
Byte Word Dword
Accumulator AL,AH AX EAX
Base BL,BH BX EBX
Count CL,CH CX ECX
Data DL,DH DX EDX
Stack pointer SP ESP
Base Pointer BP EBP
Source index SI ESI
Destination
Index
DI EDI
Code Segment CS
Data segment DS
Stack
Segment
SS
E segment ES
F segment FS
G segment GS
66. pbborole 66
Immediate addressing modes
• Operand (source)is specified by instruction itself.
• Operands(source) are stored in program or code
memory.
• Operand is fetched into instruction byte queue.
• Destination operand is either register or memory.
• Destination register has two forms viz. short and long.
• Short has no addressing mode byte while long has
addressing mode byte.
• Opcode is one or two byte.
• Data is 1 byte, 2 bytes or 4 bytes.
• Addressing mode byte is present for memory.
• The address of destination memory is determined by
memory addressing modes.
67. pbborole 67
Memory addressing modes
• Operand is located in data or stack memory.
• In two operand instruction at least one operand
must be present in register.
• D and W bits are used in two operand instruction.
• Addressing mode is always present.
• Mod = 00,01,10.
• Effective address depends upon Mod and R/M
values.
• Register is indicated by REG field and Memory
location is indicated by R/M field.
• Divided into following categories:- direct, register
indirect, based relative, indexed, based plus
indexed, based relative plus indexed, scaled
indexed and based plus scaled indexed, based
68. pbborole 68
Direct addressing mode
• Offset address of memory(data memory in default
mode) is indicated by instruction itself.
• In 16 bit addressing mode, mod = 00 and R/M =
110.
• In 32 bit addressing mode, mod =00 and R/M =
101.
• In 16 bit addressing mode, offset address is 16 bit
while in 32 bit addressing mode, offset address is
32 bit.
• REG field indicates source or destination register.
• Opcode(1-2 bytes)+addressing mode byte+offset
address(2 or 4 bytes).
• Stack memory can be accessed in random mode.
69. pbborole 69
Register Indirect addressing modes
• The offset address of data or stack memory is
stored in a register.
• Stack memory can be accessed in random and
LIFO modes.
• In LIFO mode, the SP or ESP is used in
conjunction with SS.
• In 16 bit addressing mode, BX, SI, DI and BP can
be used as a pointer. It is used to access single
data structure and one dimensional.
• In 32 bit addressing mode, EAX, EBX, ECX, EDX,
ESI and EDI can be used as pointers.
• Mod =00 R/M is 100,101(16 bit) and Mod =00 R/M is
000,001,010,011,110,111(32 bit).
• Opcode( 1 or 2 bytes) + addressing mode byte.
70. pbborole 70
Based relative addressing modes
• Base register is used to hold base address of data
structure.
• Displacement selects element within data structure.
• Effective address is contents of Base register +
displacement( 8 bit, 16 bit or 32 bit).
• Base register value is fixed and displacement is changed
to access new element.
• Mod = 01 or 10.
• In 16 bit addressing mode, BX, BP, SI and DI registers are
used as base register.
• In 32 bit addressing mode, EAX, EBX, ECX, EDX, EBP, ESI
and EDI registers can be used (without SIB byte)
• Can be used to implement linked list and one dimensional
array(multiple).
• Opcode(1-2 bytes)+addressing mode byte+disp(1.2.4
bytes)
71. pbborole 71
Based relative addressing modes
Element 0
Element 1
Element 2
Element 3
Element 4
------------
Element n-1
BASE register
Displacement
Displacement
Displacement
Displacement
Displacement
72. pbborole 72
Indexed register addressing
• In indexed register, the displacement value is used
as a pointer of array(i.e. displacement is fixed.)
• Contents of index register can be changed to point
new element.
• Used to implement one dimensional array.
• In 16 bit addressing mode, BX, BP, SI and DI
registers can be used as index registers.
• In 32 bit addressing mode, EAX, EBX, EDX, ECX,
EBP, ESI and EDI registers can be used as index
registers.
• Displacement is 1 byte, 2bytes or 4 bytes.
• Opcode(1-2bytes)+ addressing mode byte+
disp(1,2,4 bytes).
• Mod =01 or 10.
73. pbborole 73
Indexed addressing modes
Element 0
Element 1
Element 2
Element 3
Element 4
------------
Element n-1
DISP.
Index register
Index register
Index register
Index register
Index register
74. pbborole 74
Based + Indexed
• The effective address is contents of base register
and Index register.
• Used to access single, two dimensional array.
• In 16 bit addressing mode, BX+SI, BX+DI, BP+SI,
BP+DI registers are used.
• In 32 bit addressing mode, it is implemented using
scaled indexed.(with SIB byte).
• Mod =00, R/M =000, 001, 010, 011.
• Row is pointed by base register and column is
pointed by index register.
• Opcode (1-2 bytes) + addressing mode byte.
76. pbborole 76
Based relative +indexed
• Used to access multiple two dimensional arrays.
• The displacement indicates starting address of
data structure or two dimensional array.
• Displacement is fixed and base register is used to
point row and index register is used to point
column of the matrix.
• Mod = 01 or 10 and R/M is 000, 001, 010, 011.
• In 16 bit addressing mode, BX+SI, BX+DI, BP+SI,
BP+DI registers are used.
• In 32 bit, it is implemented by using scaled
index(with SIB byte.
• Opcode(1-2 bytes)+addressing mode +disp(1,2
bytes or4 bytes).
78. pbborole 78
Scaled Indexed direct
• 32 bit addressing mode only with R/M = 100.
• Contents of Index register are multiplied by
scale factor(1, 2, 4, 8).
• SIB byte is required.
• In scaled indexed direct, scaled indexed
value is added into 32 bit direct offset
address.(mod =00) and base value of SIB
byte =101.
• Base register is not present.
• Opcode(1-2 bytes)+addressing mode
byte+SIB byte+Direct address(4bytes).
79. pbborole 79
Based +scaled index
• 32 bit addressing mode only.
• Contents of Index register are multiplied by scale
factor(1, 2, 4, 8).
• Mod =00 and R/M =100.
• SIB byte is required.
• The effective address is [base]+[scale Index].
• Base registers are EAX, EBX, ECX, EDX, ESI, EDI,
ESP.
• Index registers are EAX, EBX, ECX, EDX, ESI, EDI,
EBP.
• Used to implement single two dimensional array.
• Opcode(1-2 bytes) + addressing mode byte+ SIB
byte.
80. pbborole 80
Based relative +scaled index
• 32 bit addressing mode only.
• Contents of Index register are multiplied by scale factor(1,
2, 4, 8).
• Mod =01 or 10 and R/M =100.
• SIB byte is required.
• The effective address is [base]+[scaleIndex]+disp.
• Displacement is either 1byte or 4 bytes.
• Base registers are EAX, EBX, ECX, EDX, ESI, EDI, ESP.
• Index registers are EAX, EBX, ECX, EDX, ESI, EDI, EBP.
• Used to implement multiple two dimensional arrays.
• Opcode(1-2 bytes) + addressing mode byte+ SIB
byte+disp(1 or 4 bytes).
90. pbborole 90
Stack memory(LIFO) addressing
modes
• In LIFO mode, the Pentium provides only one
addressing mode for stack operand( source or
destination) viz. Register Indirect.
• The other operand is register, data memory or
immediate.
• In this mode, the offset address of stack is stored
in SP or ESP.
• The segment address is always stored in SS.
• Used by PUSH and POP instructions.
• If operand is 16 bit, then decrements SP by 2. If
operand is 32 bit, then decrements SP by 4.
93. pbborole 93
Branch or code addressing mode
• Used by branch instructions only.
• Used to modify contents of IP and CS.
• Not used in arithmetic, logical and data
transfer operations.
• Two types of instructions viz. Unconditional
and conditional.
• Two types of addressing modes viz.
Intrasegment and Intersegment.
• The address of new program is located in
register, data memory, stack memory and
instruction.
94. pbborole 94
Intrasegment
• The value of IP is changed
• The value of CS is not changed.
• Branch within a segment.
• Branch in flat model.
• Types – Relative, register indirect,
memory indirect.
• Applicable to all branch instructions.
• Called near control transfer.
95. pbborole 95
Relative addressing
• Also called PC relative.
• Program is relocatable.
• Displacement value is added into IP or EIP.
• IP or EIP value is corrected before adding
displacement because some instructions after
branch are prefetched. As a result IP is
incremented.
• Displacement calculation is done by assembler
itself.
• Two types of labels are used viz. short and near.
• In short, the displacement is 8 bit signed.
• In Near, the displacement is 16bit unsigned(if
operand size is 16 bit) or 32 bit signed( if operand
size is 32 bit).
96. pbborole 96
Relative addressing modes
• The signed displacement is represented in
2’s complement form.
• The range of 8 bit signed displacement is –
128 to + 127 bytes.
• The range of 16 bit signed displacement is
32k bytes.
• The range of 32 bit signed displacement is
2G bytes.
• For forward jump, the displacement is +ve.
• For backward jump, the displacement is –
ve.
• Displacement = Address of jump location
Address of next instruction.
97. pbborole 97
Register indirect
• The offset address of jump location is
stored in register[16 bit or 32 bit].
• Offset address is loaded into IP/EIP directly.
• Not applicable to conditional branch.
• Program is not relocatable.
• The length of instruction is short.
• Mod =11.
98. pbborole 98
Memory Indirect
• The offset address is stored in data memory
or stack memory (random).
• The offset address is loaded into IP/EIP.
• Program is not relocatable.
• The length of instruction is short.
• The mod = 00,01,10.
• 16 bit or 32 bit addressing is used to locate
memory location.
• Not applicable to conditional branch.
99. pbborole 99
Intersegment
• Uses segmentation model.
• Contents of CS and IP/EIP are
modified.
• Offset address is loaded into IP/EIP
and segment address is loaded into
CS.
• Branch between segments.
• Called far control transfer.
• Types – direct or indirect.
• Not applicable to conditional branch.
100. pbborole 100
Direct and indirect
• The offset address is 16 bit or 32 bit.
• In direct, the offset address is 2nd and 3rd
bytes and the segment address is 4th and 5th
bytes (16bit offset).
• In direct, the offset address is 2nd ,3rd ,4th
and 5th bytes and segment address is 6th
and 7th bytes.
• In indirect, the offset address(16 bit or 32
bit) and segment address are stored in data
memory or stack memory.
• Mod = 00,01,10 , Mod =11 is invalid.
101. pbborole 101
IO addressing Modes
• Used to access IO ports.
• Destination or source register is AL, AX or EAX.
• Two types – Direct or Indirect.
• Direct – The address of IO port is 8 bit. The
address of IO port is specified by instruction itself.
• In direct mode, it can access 256 – 8bit IO
ports,128 –16 bit IO ports and 64 bit IO ports.
• In indirect addressing mode, the address of IO
port is stored in DX.
• In indirect addressing mode, it can access 64K- 8
bit IO ports, 32K – 16 bit IO ports and 16K – 32 bit
IO ports.