This document discusses different memory addressing modes used in microprocessors, including real mode, protected mode, and flat mode addressing. It provides details on how addresses are calculated in real mode using segment registers and offsets. Protected mode addressing allows accessing memory above 1MB by using descriptor tables to map segment selectors to base addresses and limits. Various programming models for addressing program memory and stack memory are also covered.
This document discusses different addressing modes used in microprocessor instructions. It begins by explaining the importance of understanding addressing modes for efficient software development. It then provides objectives for the chapter, which are to explain each data and program memory addressing mode, how to use them to form assembly statements, and how to select the appropriate mode for a given task. The document goes on to describe various data addressing modes like register, immediate, direct, displacement, indirect, base-plus-index, relative, and scaled-index. It also covers program memory addressing modes like direct, relative, and indirect. Examples are provided to illustrate how each mode works.
Chapter 3 INSTRUCTION SET AND ASSEMBLY LANGUAGE PROGRAMMINGFrankie Jones
3.1 UNDERSTANDING INSTRUCTION SET AND ASSEMBLY LANGUAGE
3.1.1 Define instruction set,machine and assembly language
3.1.2 Describe features and architectures of various type of microprocessor
3.1.3 Describe the Addressing Modes
3.2 APPLY ASSEMBLY LANGUAGE
3.2.1 Write simple program in assembly language
3.2.2 Tool in analyzing and debugging assembly language program
All-addressing-modes of the 80386 /microprocessor.pptxVidyaAshokNemade
The document discusses different addressing modes of the 80386 processor. It defines addressing modes as the techniques used to specify the address of an operand in an instruction. Some key addressing modes described are:
- Register addressing which transfers data between registers.
- Immediate addressing which specifies an immediate constant as the source.
- Direct addressing which directly specifies the memory address of the operand in the instruction.
- Register indirect addressing which uses a register like BX or BP to hold the effective address of the operand.
- Indexed addressing which uses a register like ESI or EDI to hold an index value plus a displacement to calculate the effective address.
The document discusses different addressing modes of the 80286 microprocessor including:
- Register addressing which uses 8-bit and 16-bit registers to specify locations.
- Immediate addressing where data immediately follows the opcode in memory as a constant.
- Direct addressing which transfers data between memory and registers using a memory offset.
- Indirect addressing which uses registers like BP, BX, DI and SI to hold memory offsets.
- Base-plus-index addressing which uses a base register and index register sum to indirectly address memory arrays.
- Base relative-plus-index which is a complex mode adding displacements to base and index registers to form a memory offset.
The document discusses various data addressing modes used in microprocessors, including register, immediate, direct, indirect, base-plus-index, register relative, base relative-plus-index, and scaled-index addressing. It also covers program addressing modes like direct, relative, and indirect jumping and calling. Finally, it discusses stack addressing and how the push and pop instructions are used to place data onto and remove data from the stack.
The document provides information about microprocessors and the Intel 8086 microprocessor. It discusses what a microprocessor is and the basic block diagram of a microprocessor. It then describes some key features of the Intel 8086 including that it is a 16-bit microprocessor with a 20-bit address bus and 14 general purpose registers. The document details the internal architecture of the 8086 including the execution unit, flag register, and bus interface unit. It also explains the various addressing modes and instruction set of the 8086 microprocessor.
The document discusses various addressing modes used in microprocessors including the 8086/8088. It describes indirect, register, and register indirect addressing modes in detail. Indirect addressing mode uses the address field to specify the memory location of the effective address. Register addressing mode uses register operands instead of memory. Register indirect mode specifies a register that contains the memory address of the operand. Examples are provided to illustrate how each mode works.
This document discusses different addressing modes used in microprocessor instructions. It begins by explaining the importance of understanding addressing modes for efficient software development. It then provides objectives for the chapter, which are to explain each data and program memory addressing mode, how to use them to form assembly statements, and how to select the appropriate mode for a given task. The document goes on to describe various data addressing modes like register, immediate, direct, displacement, indirect, base-plus-index, relative, and scaled-index. It also covers program memory addressing modes like direct, relative, and indirect. Examples are provided to illustrate how each mode works.
Chapter 3 INSTRUCTION SET AND ASSEMBLY LANGUAGE PROGRAMMINGFrankie Jones
3.1 UNDERSTANDING INSTRUCTION SET AND ASSEMBLY LANGUAGE
3.1.1 Define instruction set,machine and assembly language
3.1.2 Describe features and architectures of various type of microprocessor
3.1.3 Describe the Addressing Modes
3.2 APPLY ASSEMBLY LANGUAGE
3.2.1 Write simple program in assembly language
3.2.2 Tool in analyzing and debugging assembly language program
All-addressing-modes of the 80386 /microprocessor.pptxVidyaAshokNemade
The document discusses different addressing modes of the 80386 processor. It defines addressing modes as the techniques used to specify the address of an operand in an instruction. Some key addressing modes described are:
- Register addressing which transfers data between registers.
- Immediate addressing which specifies an immediate constant as the source.
- Direct addressing which directly specifies the memory address of the operand in the instruction.
- Register indirect addressing which uses a register like BX or BP to hold the effective address of the operand.
- Indexed addressing which uses a register like ESI or EDI to hold an index value plus a displacement to calculate the effective address.
The document discusses different addressing modes of the 80286 microprocessor including:
- Register addressing which uses 8-bit and 16-bit registers to specify locations.
- Immediate addressing where data immediately follows the opcode in memory as a constant.
- Direct addressing which transfers data between memory and registers using a memory offset.
- Indirect addressing which uses registers like BP, BX, DI and SI to hold memory offsets.
- Base-plus-index addressing which uses a base register and index register sum to indirectly address memory arrays.
- Base relative-plus-index which is a complex mode adding displacements to base and index registers to form a memory offset.
The document discusses various data addressing modes used in microprocessors, including register, immediate, direct, indirect, base-plus-index, register relative, base relative-plus-index, and scaled-index addressing. It also covers program addressing modes like direct, relative, and indirect jumping and calling. Finally, it discusses stack addressing and how the push and pop instructions are used to place data onto and remove data from the stack.
The document provides information about microprocessors and the Intel 8086 microprocessor. It discusses what a microprocessor is and the basic block diagram of a microprocessor. It then describes some key features of the Intel 8086 including that it is a 16-bit microprocessor with a 20-bit address bus and 14 general purpose registers. The document details the internal architecture of the 8086 including the execution unit, flag register, and bus interface unit. It also explains the various addressing modes and instruction set of the 8086 microprocessor.
The document discusses various addressing modes used in microprocessors including the 8086/8088. It describes indirect, register, and register indirect addressing modes in detail. Indirect addressing mode uses the address field to specify the memory location of the effective address. Register addressing mode uses register operands instead of memory. Register indirect mode specifies a register that contains the memory address of the operand. Examples are provided to illustrate how each mode works.
A microprocessor is an electronic component that is used by a computer to do its work. It is a central processing unit on a single integrated circuit chip containing millions of very small components including transistors, resistors, and diodes that work together. Some microprocessors in the 20th century required several chips. Microprocessors help to do everything from controlling elevators to searching the Web. Everything a computer does is described by instructions of computer programs, and microprocessors carry out these instructions many millions of times a second. [1]
Microprocessors were invented in the 1970s for use in embedded systems. The majority are still used that way, in such things as mobile phones, cars, military weapons, and home appliances. Some microprocessors are microcontrollers, so small and inexpensive that they are used to control very simple products like flashlights and greeting cards that play music when you open them. A few especially powerful microprocessors are used in personal computers.
The document discusses the architecture of the 8086 microprocessor. It describes the 8086 as a 16-bit processor that can access external memory using a 20-bit address bus. The 8086 uses memory segmentation to map the larger 20-bit physical addresses to the smaller 16-bit registers. Each segment is defined by a base address stored in a 16-bit segment register. The 20-bit physical address is calculated by combining the segment register value and offset. The document provides details on the various memory segments and addressing modes supported by the 8086 architecture.
The 8086 microprocessor has a 16-bit arithmetic logic unit and data bus. It uses a 20-bit address bus to access up to 1 megabyte of memory addressed through segment registers. The 8086 has separate bus interface and execution units, with registers in each unit used for fetching instructions, computing addresses, and executing operations. Key registers include the instruction pointer, segment registers, and general purpose registers like the accumulator, base, count, and data registers.
The document discusses addressing modes for the 8086 microprocessor. It defines addressing modes as the way in which an instruction's operand is specified, including rules for interpreting or modifying the address before execution. Addressing modes for 8086 instructions are divided into two categories: those for data and those for branches. The 8086 supports flexible memory addressing modes to easily access variables, arrays, records, pointers and other complex data types through the use of displacement, base, and index registers. Common 8086 addressing modes include implied, immediate, and register modes.
The document provides information about the 8086 and 80386 microprocessors. It discusses the 8086's 16-bit architecture and its 14 registers including the accumulator, base, count, and data registers. It also describes the 8086's addressing modes. For the 80386, it discusses its 32-bit architecture with 32-bit general purpose registers and segment registers. It outlines the 80386's register organization, flag register, descriptor registers, addressing modes including scaled indexed mode, control registers, and debug registers.
This document provides information about the 8086 microprocessor used in microcontroller applications. It discusses the architecture of the 8086 including its registers, buses, addressing modes, instruction set and interrupts. Specifically, it outlines the features of the 8086, describes the bus interface unit and execution unit, and explains the different general purpose and segment registers as well as the various addressing modes supported by the 8086 architecture.
The document discusses processor architecture and interfacing. It provides an overview of computer organization and architecture, software and hardware abstraction, the abstract CPU architecture and functional blocks of a CPU. It then describes the central hardware of a microprocessor, highlighting three basic characteristics: instruction set, bandwidth and clock speed. The remainder of the document focuses on different Intel processors, comparing their development from the 8088 to Pentium models. It also covers the 8086 architecture, registers and addressing in memory and segments.
The document provides an overview of the 8086/8088 microprocessor architecture. It discusses the main components including the Bus Interface Unit (BIU) and Execution Unit (EU) that work in parallel to implement a two-stage pipeline. It describes the various registers like the segment, index, pointer, and flag registers. It also covers the different addressing modes used to calculate physical memory addresses from segment and offset values in real mode.
The 8086 microprocessor has an architecture that separates it into a Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and handles address calculation on the buses. The EU decodes and executes instructions using its 16-bit ALU. The 8086 has 16 general purpose registers including 4 data registers (AX, BX, CX, DX) and segment/pointer registers. It also contains a flag register for storing status flags. The 8086 can queue up to 6 bytes of upcoming instructions to improve performance.
(246431835) instruction set principles (2) (1)Alveena Saleem
The document discusses instruction set architecture principles including what an instruction set is, how instructions are represented and classified, and different types of instruction sets. It covers topics like register-based machines, addressing modes, common instruction types, and how the instruction set affects compiler design and register allocation.
This document contains information about the 8086 microprocessor used in a college course on microprocessors and microcontrollers. It includes details about the architecture and components of the 8086 such as the bus interface unit, execution unit, registers, addressing modes, and instruction set. It also provides explanations of the different addressing modes used by the 8086 like register, immediate, direct, register indirect, base, indexed, and based indexed addressing.
This document provides an introduction and overview of Emu8086, an emulator for the Intel 8086 microprocessor. It discusses how Emu8086 allows users to run 8086 programs on modern PCs and laptops by emulating the hardware. The document then describes the main components of the 8086 architecture, including general purpose registers like AX, BX, CX and DX, special purpose registers like IP and flags, and segment registers like CS, DS, SS and ES. It provides examples of how to use MOV, ADD, SUB and XCHG instructions to move data between registers and perform basic arithmetic operations.
The document discusses data formats and machine level programming on Intel processors. It describes how Intel uses words, double words, and quad words to refer to 16-bit, 32-bit, and 64-bit data types. It also discusses common data types like integers, pointers, floating point numbers, and how they are stored. The document then covers general purpose registers, addressing modes, and instructions for data movement between registers and memory like MOV, PUSH, and POP.
This document outlines the course outcomes and content for a Microprocessor and Programming course. The five course outcomes cover describing microprocessor architecture and organization, functional blocks and instruction set of the 8086 microprocessor, memory and addressing modes, using different instruction types and interrupts, and developing assembly language programs. The content includes details on the 8086 instruction format, operation codes, addressing modes, instruction types like data transfer, arithmetic, and flow control, and assembly programming tools.
The 80386 microprocessor had two main versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications that did not require the full 32-bit capabilities of the 80386DX. The 80386 supported protected mode which enabled virtual memory, paging, and memory protection in addition to the capabilities of the 80286. It had enhanced registers, addressing modes, and memory management compared to earlier Intel processors.
The 80386 microprocessor has two versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications not requiring the full 32-bit bus of the 80386DX. It supports up to 4GB of virtual memory address space using segmentation and paging. The 80386 architecture includes a central processing unit, memory management unit, and bus interface unit. It has numerous features that enhance performance such as cache, pipeline processing, and floating point unit.
The document discusses the registers and addressing modes of the 8086 microprocessor. It describes the various registers - general purpose registers, pointer/index registers, segment registers, instruction pointer, and status flags register. It explains how the segment registers point to memory segments and how memory addresses are calculated. The instruction pointer acts as a program counter. There are seven addressing modes - register, immediate, direct, register indirect, based, indexed, and based indexed with displacement that specify the location of operands in memory using combinations of registers, displacements, and offsets.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
A microprocessor is an electronic component that is used by a computer to do its work. It is a central processing unit on a single integrated circuit chip containing millions of very small components including transistors, resistors, and diodes that work together. Some microprocessors in the 20th century required several chips. Microprocessors help to do everything from controlling elevators to searching the Web. Everything a computer does is described by instructions of computer programs, and microprocessors carry out these instructions many millions of times a second. [1]
Microprocessors were invented in the 1970s for use in embedded systems. The majority are still used that way, in such things as mobile phones, cars, military weapons, and home appliances. Some microprocessors are microcontrollers, so small and inexpensive that they are used to control very simple products like flashlights and greeting cards that play music when you open them. A few especially powerful microprocessors are used in personal computers.
The document discusses the architecture of the 8086 microprocessor. It describes the 8086 as a 16-bit processor that can access external memory using a 20-bit address bus. The 8086 uses memory segmentation to map the larger 20-bit physical addresses to the smaller 16-bit registers. Each segment is defined by a base address stored in a 16-bit segment register. The 20-bit physical address is calculated by combining the segment register value and offset. The document provides details on the various memory segments and addressing modes supported by the 8086 architecture.
The 8086 microprocessor has a 16-bit arithmetic logic unit and data bus. It uses a 20-bit address bus to access up to 1 megabyte of memory addressed through segment registers. The 8086 has separate bus interface and execution units, with registers in each unit used for fetching instructions, computing addresses, and executing operations. Key registers include the instruction pointer, segment registers, and general purpose registers like the accumulator, base, count, and data registers.
The document discusses addressing modes for the 8086 microprocessor. It defines addressing modes as the way in which an instruction's operand is specified, including rules for interpreting or modifying the address before execution. Addressing modes for 8086 instructions are divided into two categories: those for data and those for branches. The 8086 supports flexible memory addressing modes to easily access variables, arrays, records, pointers and other complex data types through the use of displacement, base, and index registers. Common 8086 addressing modes include implied, immediate, and register modes.
The document provides information about the 8086 and 80386 microprocessors. It discusses the 8086's 16-bit architecture and its 14 registers including the accumulator, base, count, and data registers. It also describes the 8086's addressing modes. For the 80386, it discusses its 32-bit architecture with 32-bit general purpose registers and segment registers. It outlines the 80386's register organization, flag register, descriptor registers, addressing modes including scaled indexed mode, control registers, and debug registers.
This document provides information about the 8086 microprocessor used in microcontroller applications. It discusses the architecture of the 8086 including its registers, buses, addressing modes, instruction set and interrupts. Specifically, it outlines the features of the 8086, describes the bus interface unit and execution unit, and explains the different general purpose and segment registers as well as the various addressing modes supported by the 8086 architecture.
The document discusses processor architecture and interfacing. It provides an overview of computer organization and architecture, software and hardware abstraction, the abstract CPU architecture and functional blocks of a CPU. It then describes the central hardware of a microprocessor, highlighting three basic characteristics: instruction set, bandwidth and clock speed. The remainder of the document focuses on different Intel processors, comparing their development from the 8088 to Pentium models. It also covers the 8086 architecture, registers and addressing in memory and segments.
The document provides an overview of the 8086/8088 microprocessor architecture. It discusses the main components including the Bus Interface Unit (BIU) and Execution Unit (EU) that work in parallel to implement a two-stage pipeline. It describes the various registers like the segment, index, pointer, and flag registers. It also covers the different addressing modes used to calculate physical memory addresses from segment and offset values in real mode.
The 8086 microprocessor has an architecture that separates it into a Bus Interface Unit (BIU) and Execution Unit (EU). The BIU fetches instructions and data from memory and handles address calculation on the buses. The EU decodes and executes instructions using its 16-bit ALU. The 8086 has 16 general purpose registers including 4 data registers (AX, BX, CX, DX) and segment/pointer registers. It also contains a flag register for storing status flags. The 8086 can queue up to 6 bytes of upcoming instructions to improve performance.
(246431835) instruction set principles (2) (1)Alveena Saleem
The document discusses instruction set architecture principles including what an instruction set is, how instructions are represented and classified, and different types of instruction sets. It covers topics like register-based machines, addressing modes, common instruction types, and how the instruction set affects compiler design and register allocation.
This document contains information about the 8086 microprocessor used in a college course on microprocessors and microcontrollers. It includes details about the architecture and components of the 8086 such as the bus interface unit, execution unit, registers, addressing modes, and instruction set. It also provides explanations of the different addressing modes used by the 8086 like register, immediate, direct, register indirect, base, indexed, and based indexed addressing.
This document provides an introduction and overview of Emu8086, an emulator for the Intel 8086 microprocessor. It discusses how Emu8086 allows users to run 8086 programs on modern PCs and laptops by emulating the hardware. The document then describes the main components of the 8086 architecture, including general purpose registers like AX, BX, CX and DX, special purpose registers like IP and flags, and segment registers like CS, DS, SS and ES. It provides examples of how to use MOV, ADD, SUB and XCHG instructions to move data between registers and perform basic arithmetic operations.
The document discusses data formats and machine level programming on Intel processors. It describes how Intel uses words, double words, and quad words to refer to 16-bit, 32-bit, and 64-bit data types. It also discusses common data types like integers, pointers, floating point numbers, and how they are stored. The document then covers general purpose registers, addressing modes, and instructions for data movement between registers and memory like MOV, PUSH, and POP.
This document outlines the course outcomes and content for a Microprocessor and Programming course. The five course outcomes cover describing microprocessor architecture and organization, functional blocks and instruction set of the 8086 microprocessor, memory and addressing modes, using different instruction types and interrupts, and developing assembly language programs. The content includes details on the 8086 instruction format, operation codes, addressing modes, instruction types like data transfer, arithmetic, and flow control, and assembly programming tools.
The 80386 microprocessor had two main versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications that did not require the full 32-bit capabilities of the 80386DX. The 80386 supported protected mode which enabled virtual memory, paging, and memory protection in addition to the capabilities of the 80286. It had enhanced registers, addressing modes, and memory management compared to earlier Intel processors.
The 80386 microprocessor has two versions - the 80386DX with a 32-bit address and data bus, and the 80386SX with a 24-bit address bus and 16-bit data bus. The 80386SX was developed later for applications not requiring the full 32-bit bus of the 80386DX. It supports up to 4GB of virtual memory address space using segmentation and paging. The 80386 architecture includes a central processing unit, memory management unit, and bus interface unit. It has numerous features that enhance performance such as cache, pipeline processing, and floating point unit.
The document discusses the registers and addressing modes of the 8086 microprocessor. It describes the various registers - general purpose registers, pointer/index registers, segment registers, instruction pointer, and status flags register. It explains how the segment registers point to memory segments and how memory addresses are calculated. The instruction pointer acts as a program counter. There are seven addressing modes - register, immediate, direct, register indirect, based, indexed, and based indexed with displacement that specify the location of operands in memory using combinations of registers, displacements, and offsets.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Adaptive synchronous sliding control for a robot manipulator based on neural ...IJECEIAES
Robot manipulators have become important equipment in production lines, medical fields, and transportation. Improving the quality of trajectory tracking for
robot hands is always an attractive topic in the research community. This is a
challenging problem because robot manipulators are complex nonlinear systems
and are often subject to fluctuations in loads and external disturbances. This
article proposes an adaptive synchronous sliding control scheme to improve trajectory tracking performance for a robot manipulator. The proposed controller
ensures that the positions of the joints track the desired trajectory, synchronize
the errors, and significantly reduces chattering. First, the synchronous tracking
errors and synchronous sliding surfaces are presented. Second, the synchronous
tracking error dynamics are determined. Third, a robust adaptive control law is
designed,the unknown components of the model are estimated online by the neural network, and the parameters of the switching elements are selected by fuzzy
logic. The built algorithm ensures that the tracking and approximation errors
are ultimately uniformly bounded (UUB). Finally, the effectiveness of the constructed algorithm is demonstrated through simulation and experimental results.
Simulation and experimental results show that the proposed controller is effective with small synchronous tracking errors, and the chattering phenomenon is
significantly reduced.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
A review on techniques and modelling methodologies used for checking electrom...nooriasukmaningtyas
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
3. Prophet Muhammad ﷺ said,
“A Muslim does not regularly attend
the mosques to perform prayer and
remember Allah, but Allah feels
happy with him just as the family of
one who is absent feels happy when
he comes back to them”
Sunan Ibn Majah, Book 4, Hadith 66
4. Outline
• Data Addressing modes
• Types of data and register addressing mode
• Program memory addressing mode
• Stack memory addressing mode
5. Addressing Modes
CHAPTER OBJECTIVES
• Explain the operation of each data-addressing mode.
• Use the data-addressing modes to form assembly language
statements.
• Explain the operation of each program memory-addressing mode.
• Use the program memory-addressing modes to form assembly and
machine language statements.
• Select the appropriate addressing mode to accomplish a given
task.
• Detail the difference between addressing memory data using real
mode and protected mode operation.
• Describe the sequence of events that place data onto the stack or
remove data from the stack.
• Explain how a data structure is placed in memory and used with
software Addressing Modes
5
6. Addressing modes
• Three Addressing modes
• Data Addressing modes
• Program memory addressing
• Stack memory addressing
7. Data Addressing Modes
• MOV instruction defines the direction of data flow. The source is to
the right and the destination is to the left, next to the opcode MOV.
MOV AX,BX
• An opcode, or operation code, tells the microprocessor which
operation to perform.
• MOV AX, BX instruction transfers the word contents of the source
register (BX) into the destination register (AX).
7
8. 3.1 Data Addressing mode
• Register Addressing
• Immediate Addressing
• Direct Data Addressing
• Register Indirect Addressing
• Base plus Index Addressing
• Register relative Addressing
• Base relative plus index Addressing
• Scaled index Addressing
10. Register Addressing
• The most common form of data addressing.
– once register names learned, easiest to apply.
• The microprocessor contains these 8-bit
register names used with register addressing:
AH, AL, BH, BL, CH, CL, DH, and DL.
• 16-bit register names: AX, BX, CX, DX, SP,
BP, SI, and DI.
10
11. In 80386 & above, extended 32-bit register
names are: EAX, EBX, ECX, EDX, ESP,
EBP, EDI, and ESI.
• 64-bit mode register names are: RAX, RBX,
RCX, RDX, RSP, RBP, RDI, RSI, and R8
through R15.
• Important for instructions to use registers that
are the same size.
– never mix an 8-bit with a 16-bit register, an 8- or
a 16-bit register with a 32-bit register
– this is not allowed by the microprocessor and
results in an error when assembled
11
12. Fig.3.3 The effect of executing the MOV BX, CX instruction at the point just before
the BX register changes. Note that only the rightmost 16 bits of register EBX
change.
12
13. Immediate Addressing
• Term immediate implies that data immediately
follow the hexadecimal opcode in the memory.
– immediate data are constant data
– data transferred from a register or memory
location are variable data
• Immediate addressing operates upon a byte or
word of data.
• Figure 3–4 shows the operation of a MOV
EAX,13456H instruction.
13
14. • Figure 3–4 The operation of the MOV EAX,3456H instruction. This
instruction copies the immediate data (13456H) into EAX.
As with the MOV instruction illustrated in
Figure 3–3, the source data overwrites the
destination data.
14
15. • In symbolic assembly language, the symbol #
precedes immediate data in some assemblers.
– MOV AX,#3456H instruction is an example
• Most assemblers do not use the # symbol, but
represent immediate data as in the
MOV AX,3456H instruction.
– an older assembler used with some Hewlett-
Packard logic development does, as may others
15
16. • The symbolic assembler portrays immediate
data in many ways.
• The letter H appends hexadecimal data.
• If hexadecimal data begin with a letter, the
assembler requires the data start with a 0.
– to represent a hexadecimal F2, 0F2H is used in
assembly language
• Decimal data are represented as it is and
requires no special codes or adjustments.
– an example is the 100 decimal in the
MOV AL,100 instruction
16
17. An ASCII-coded character or characters may be
depicted in the immediate form if the ASCII data
are enclosed in apostrophes.
– be careful to use the apostrophe (‘) for ASCII
data and not the single quotation mark (`)
• Binary data are represented if the binary
number is followed by the letter B.
– in some assemblers, the letter Y
17
18. Direct Data Addressing
• Applied to many instructions in a typical program.
Copies the content from memory location
• Two basic forms of direct data addressing:
– direct addressing, which applies to a MOV between a
memory location and AL, AX, or EAX
– displacement addressing, which applies to almost any
instruction in the instruction set
• Address is formed by adding the displacement to the
default data segment address or an alternate segment
address.
18
19. Direct Addressing
• Direct addressing with a MOV instruction transfers data
between a memory location, located within the data
segment, and the AL (8-bit), AX (16-bit), or EAX (32-bit)
register.
• MOV AL,DATA loads AL from the data segment memory
location DATA (1234H).
– DATA is a symbolic memory location, while 1234H is the
actual hexadecimal location
19
20. • This instruction transfers a copy contents of memory
location 11234H into AL.
– the effective address is formed by adding 1234H (the
offset address) and 10000H (the data segment address of
1000H times 10H) in a system operating in the real mode
20
22. Register Indirect Addressing
• Allows data to be addressed at any memory
location through an offset address held in any of the
following registers: BP, BX, DI, and SI.
• In addition, 80386 and above allow register
indirect addressing with any extended register
except ESP.
• In the 64-bit mode, the segment registers serve no
purpose in addressing a location in the flat model.
22
24. Base-Plus-Index Addressing
• Similar to indirect addressing because it indirectly
addresses memory data.
• The base register often holds the beginning
location of a memory array.
– the index register holds the relative position of an
element in the array
– whenever BP addresses memory data, both the
stack segment register and BP generate the effective
address
24
26. Locating Array Data Using Base-
Plus-Index Addressing
• A major use is to address elements in a memory
array.
• To accomplish this, load the BX register (base) with
the beginning address of the array and the DI
register (index) with the element number to be
accessed.
• Figure 3–9 shows the use of BX and DI to access an
element in an array of data.
26
28. Register Relative Addressing
• Similar to base-plus-index addressing and
displacement addressing.
– data in a segment of memory are addressed by
adding the displacement to the contents of a base
or an index register (BP, BX, DI, or SI)
• Figure 3–10 shows the operation of the
MOV AX,[BX+1000H] instruction.
• A real mode segment is 64K bytes long.
28
30. Addressing Array Data with
Register Relative
• It is possible to address array data with register
relative addressing.
– such as with base-plus-index addressing
• In Figure 3–11, register relative addressing is
illustrated with the same example as for
baseplus-index addressing.
– this shows how the displacement ARRAY adds to
index register DI to generate a reference to an array
element
30
32. Base Relative-Plus-Index
Addressing
• Similar to base-plus-index addressing.
– adds a displacement
– uses a base register and an index register to form
the memory address
• This type of addressing mode often addresses a
two-dimensional array of memory data.
32
33. Addressing Data with Base
Relative-Plus-Index
• Least-used addressing mode.
• Figure 3–12 shows how data are referenced if the
instruction executed by the microprocessor is MOV
AX,[BX + SI + 100H].
– displacement of 100H adds to BX and SI to form
the offset address within the data segment
• This addressing mode is too complex for frequent
use in programming.
33
35. Addressing Arrays with Base
Relative-Plus-Index
• Suppose a file of many records exists in memory,
each record with many elements.
– displacement addresses the file, base register
addresses a record, the index register addresses an
element of a record
• Figure 3–13 illustrates this very complex form of
addressing.
35
37. Scaled-Index Addressing
• Unique to 80386 - Core2 microprocessors.
– uses two 32-bit registers (a base register and an
index register) to access the memory
• The second register (index) is multiplied by a
scaling factor.
– the scaling factor can be 1x, 2x, 4x, 8x
• A scaling factor of is implied and need not be
included in the assembly language instruction
(MOV AL,[EBX + ECX]).
37
42. Real Mode Memory Addressing
•The only mode available on for 8088-8086
•Real mode memory is the first 1M (220) bytes of the
memory system (real, conventional, DOS memory)
•All real mode 20-bit addresses are a combination of a
segment address (in a segment register) plus an offset
address (in another register)
•The segment register address (16-bits) is appended with
a 0H or 00002 (or multiplied by 10H) to form a 20-bit
start of segment address
•The effective memory address =
this 20-bit segment address + a 16-bit offset address in
a register
•Segment length is fixed = 216 = 64K bytes 42
45. Defaults
• CS for program (code)
• SS for stack
• DS for data
• ES for string destination
• Default offset addresses that go with them:
Segment Offset (16-bit)
8080, 8086, 80286
Offset (32-bit)
80386 and above
Purpose
CS IP EIP Program
SS SP, BP ESP, EBP Stack
DS BX, DI, SI, 8-bit or 16-bit
#
EAX, EBX, ECX, EDX,
ESI, EDI, 8-bit or 32-bit
#
Data
ES DI EDI String
destination 45
47. Segmentation: Pros and Cons
Advantages:
•Allows easy and efficient relocation of code and data
•A program can be located anywhere in memory without
any change to the program
•Program writing needs not worry about actual memory
structure of the computer used to execute it
•To relocate code or data only the segment number
needs to be changed
Disadvantages:
•Complex hardware and for address generation
•Software: Programs limited by segment size
(only 64KB with the 8086)
47
48. Limitations of the above real mode segmentation scheme
•Segment size is fixed at 64 KB
•Segment can not begin at an arbitrary memory
address…
With 20-bit memory addressing, can only begin at
addresses starting with 0H, i.e. at 16 byte intervals
•Difficult to use with 24 or 32-bit memory addressing
with segment registers remaining at 16-bits
80286 and above use 24, 32, 36 bit addresses but still
16-bit segment registers
→ Use memory segmentation in the protected mode
48
49. 49
Segment and Offset Addressing Scheme Allows
Relocation
• Segment plus offset addressing allows DOS programs to be relocated in
memory.
• A relocatable program is one that can be placed into any area of memory and
executed without change.
• Relocatable data are data that can be placed in any area of memory and used
without any change to the program.
50. Protected Mode Memory Addressing
• Used in 80286 and above
• Protected mode is where Windows operates
• Allows access to data and programs located above the first 1M byte
of memory, as well as within the first 1M byte of memory
• Multi-task Support
• 32 bit offset address
• Segments can be up to 4GB in Size
• Task Segments Defined by Descriptor Tables
• Memory Protection and Task Privilege
• Paging Support
51. Protected Mode Memory Addressing
51
Remember using real mode addressing we were previously able
to address 1M Byte of memory.
Using Protected Mode memory addressing locations above the
1M byte boundary can be addressed.
The Protected Memory scheme still uses base address and
index address to calculate actual memory locations but, this is
done in a different way from what we had done previously.
52. 52
The offset address is still used as previously, to find the
memory location within the segment that we are interested in.
The use of the base or the segment address has changed a bit.
The segment register now contains a selector rather than the
“actual” base address of the segment.
An additional table called a descriptor table uses the selector
as an index to provide additional information known as
descriptor.
The descriptor describes:
• location
•Length
•Access rights
For the segment of interest.
53. 53
There are two descriptor tables. Global Descriptor table and
local descriptor table.
Each table contains 8192 descriptors.
Global descriptors contain segment definitions that apply to all
programs. – System Descriptor.
Local Descriptors provide information that are unique to an
application. – Application Descriptor.
Because each table contains 8192 descriptors, there are a total
of 16384 descriptors available to any application.
This also now means that up to 16384 memory segments could
be described to be used by each application.
54. 54
80286 Descriptor
00000000 00000000
Access Rights Base (B23-B16)
Base (B15 – B0)
Limit (L15 –L0)
80386 through P4 Descriptor
Base
(B31-B24)
G D 0 A
V
Limit
(L19-L16)
Access Rights Base (B23-B16)
Base (B15 – B0)
Limit (L15 –L0)
55. 55
Segment Limit – The last possible offset address of the
segment.
So if the segment begins at memory location F00000H and
ends at location F000FFH. What should be the value of the
limit register ?
Remember the limit registers size on 80286 is 16 bits and
80386 and above is 20 bit.
Additional bits available to 80386 and above
G – Granularity bit –
If G =0 – The limit specifies segment limit of 00000H to FFFFFH.
If G =1 – The limit specifies segment limit of 00000XXXH to
FFFFFXXXH.
appended with FFFH
56. 56
This increases the limit and allows the segment length of 4K to
4G bytes in steps of 4K Bytes.
80286 has 16 bits to define offset because of its internal
architecture.
80386 and above have 32 bits and have a 32 bit internal
architecture.
Thus operating systems also work in either 16 bit mode or 32
bit mode. DOS works uses 16 bit environment and windows
uses 32 bits.
In the 64-bit descriptor, the L bit (probably means large, but
Intel calls it the 64-bit)
64-bit extensions when L = 1 & 32-bit when L=0
57. 57
Example:
Segment start and end if the base address is
10000000H, the limit is 001FFH and G bit =0.
Base = Start = 10000000H
G =0
End = Base + Limit = 10000000H + 001FFH =
100001FFH
58. 58
Example:
Segment start and end if the base address is 10000000H, the
limit is 001FFH and G bit =1.
Base = Start = 10000000H
G =1
End = Base + Limit = 10000000H + 001FFXXXH = 101FFFFFH
59. 59
AV – Available
AV =1 – Available
AV =0 – Not Available.
D = Data access
D = 1 – The instructions are in 32bits and the registers are 32
bits.
D = 0 – The instructions are 16 bit instructions compatible with
8086-80286
60. 60
Access Rights byte- Control access to protected mode memory
segment. This byte describes how the segment functions in the
system.
7 6 5 4 3 2 1 0
P DPL S E ED/C R/W A
A = 0 – Segment Not Accessed
A =1 – Segment has been accessed
E = 1 Descriptor describes code segment
E = 0 Descriptor describes data segment
ED = 0 Segment expands upwards
ED = 1 Segment expands downward
W = 0 Data may not be written
W = 1 Data may be written
61. 61
C = 0 Ignore descriptor privilege level
C = 1 Abide by privilege level
R = 0 Code segment may not be read
R = 1 Code segment may be read
S = 0 System descriptor
S = 1 Code or data segment descriptor
DPL= Sets the descriptor privilege level ( 00 – 11)
P = 0 Descriptor is undefined
P = 1 Segment contains a valid base and limit
7 6 5 4 3 2 1 0
P DPL S E ED/C R/W A
62. 62
Selector TI RPL
15 3 2 1 0
Selector – Selects one of the 8192 descriptors.
TI – Chooses either the global descriptor table or the local
table.
T1 = 0 – Global descriptor table
T1 =1 – Local descriptor table
RPL – Requested privilege level.
00 – highest
11 - lowest
63.
64. 64
Flat Mode Memory
• A flat mode memory system is one in which there is no segmentation.
• does not use a segment register to address a location in the memory
• First byte address is at 00 0000 0000H; the last location is at FF FFFF FFFFH.
• address is 40-bits
• The segment register still selects the privilege level of the software.
• Real mode system is not available if the processor operates in the 64-bit mode.
• Protection and paging are allowed in the 64-bit mode.
• The CS register is still used in the protected mode operation in the 64-bit mode.
• Most programs today are operated in the IA32 compatible mode.
• current software operates properly, but this will change in a few years as memory
becomes
larger and most people have 64-bit computers
66. Memory Paging
66
The memory paging mechanism located within the 80386 and
above allows any physical memory location to be assigned to
any linear address.
The linear address is defined as the address generated by a
program.
Within the memory paging unit the linear address is invisibly
translated into any physical address.
This allows an application written to function at a specific
address to be relocated through the paging mechanism
67. It also allows memory to be placed into areas where no
memory exists.
The paging unit is controlled by the contents of the
microprocessor’s control registers.
The linear address is broken into three sections that are used
to access the page directory entry, page table entry, and page
offset address
The page directory contains 1,024 doubleword addresses that
locate up to 1,024 page tables
The page directory and each page table are 4K bytes in length
70. PROGRAM MEMORY ADDRESSING
MODES
• Used with the JMP (jump) and CALL instructions.
• Consist of three distinct forms:
– direct, relative, and indirect
70
71. Direct Program Memory Addressing
• Used for all jumps and calls by early
microprocessor; also used in high-level languages,
such as BASIC.
– GOTO and GOSUB instructions
• The microprocessor uses this form, but not as
often as relative and indirect program memory
addressing.
• The instructions for direct program memory
addressing store the address with the opcode.
71
73. • This JMP instruction loads CS with 1000H and IP
with 0000H to jump to memory location 10000H
for the next instruction.
– an intersegment jump is a jump to any memory
location within the entire memory system
• Often called a far jump because it can jump to
any memory location for the next instruction.
– in real mode, any location within the first 1M
byte
– In protected mode operation, the far jump can
jump to any location in the 4G-byte address range
in the 80386 - Core2 microprocessors
73
74. • The only other instruction using direct program
addressing is the intersegment or far CALL
instruction.
• Usually, the name of a memory address, called a
label, refers to the location that is called or
jumped to instead of the actual numeric address.
• When using a label with the CALL or JMP
instruction, most assemblers select the best form
of program addressing.
74
75. Relative Program Memory
Addressing
• Not available in all early microprocessors, but it is
available to this family of microprocessors.
• The term relative means “relative to the
instruction pointer (IP)”.
• The JMP instruction is a 1-byte instruction, with a
1-byte or a 2-byte displacement that adds to the
instruction pointer
75
77. Indirect Program Memory
Addressing
• The microprocessor allows several forms of
program indirect memory addressing for the JMP
and CALL instructions.
• In 80386 and above, an extended register can be
used to hold the address or indirect address of a
relative JMP or CALL.
– for example, the JMP EAX jumps to the location
address by register EAX
77
78. • If a relative register holds the address, the
jump is considered to be an indirect jump.
• For example, JMP [BX] refers to the memory
location within the data segment at the offset
address contained in BX.
– at this offset address is a 16-bit number used as
the offset address in the intra-segment jump
– this type of jump is sometimes called an indirect-
indirect or double-indirect jump
• Figure shows a jump table that is stored,
beginning at memory location TABLE.
78
80. STACK MEMORY-ADDRESSING
MODES
• The stack plays an important role in all
microprocessors.
– holds data temporarily and stores return
addresses used by procedures
• Stack memory is LIFO (last-in, first-out) memory
– describes the way data are stored and removed
from the stack
80
81. • Data are placed on the stack with a PUSH
instruction; removed with a POP instruction.
• Stack memory is maintained by two registers:
– the stack pointer (SP or ESP)
– the stack segment register (SS)
• Whenever a word of data is pushed onto the
stack, the high-order 8 bits are placed in the
location addressed by SP – 1.
– low-order 8 bits are placed in the location
addressed by SP – 2
81
82. • The SP is decremented by 2 so the next word
is stored in the next available stack location.
– the SP/ESP register always points to an area of
memory located within the stack segment.
• In protected mode operation, the SS register
holds a selector that accesses a descriptor for
the base address of the stack segment.
• When data are popped from the stack, the low
order 8 bits are removed from the location
addressed by SP.
– high-order 8 bits are removed; the SP register is
incremented by 2
82
84. • Note that PUSH and POP store or retrieve
words of data—never bytes—in 8086 - 80286.
• 80386 and above allow words or doublewords
to be transferred to and from the stack.
• Data may be pushed onto the stack from any
16-bit register or segment register.
– in 80386 and above, from any 32-bit extended
register
• Data may be popped off the stack into any register
or any segment register except CS.
84
85. • PUSHA and POPA instructions push or pop all
except segment registers, on the stack.
• Not available on early 8086/8088 processors.
• 80386 and above allow extended registers to be
pushed or popped.
– 64-bit mode for Pentium and Core2 does not
contain a PUSHA or POPA instruction
85