past-research-on-pc-router
•Download as PPTX, PDF•
2 likes•854 views
This document summarizes the history of PC router research. It discusses several notable papers on click modular router from 1999, RouteBricks from 2009, PacketShader from 2011, and NetMap from 2012. These papers presented techniques like polling, parallelization using multi-cores/GPUs, pipelining, and batch processing to improve routing performance. Specific routing tables like DIR-24-8-BASIC and Waldvogel are also mentioned.
Report
Share
Report
Share
Recommended
Responsive Distributed Routing Algorithm
Global routing topology.
loop-free paths . Dynamic distributed algorithm was rooted on this algorithm . Take Less Recovery Time(h) than previous algorithm (h^2) when Network Links fails .
Oss vs drive test pdcp throughput
1) A throughput testing was conducted using OSS and drive test methods on site LBHWL22 to compare the results.
2) Using multiple FTP sessions, throughput was measured every 15 minutes over 1 hour for a UE on the site.
3) The results showed that the drive test throughput was slightly higher than the OSS throughput, but both followed the same trend over time.
fccm2015-jain-presentation
The document proposes an efficient coarse-grained overlay architecture based on DSP blocks in FPGAs. It consists of a 2D array of tiles with a programmable functional unit and routing resources in each tile. The functional unit is implemented using the fully pipelined DSP48E1 block from Xilinx FPGAs to achieve high frequencies near 400MHz. Experimental results show the overlay can map compute kernels with up to 72 operations and achieves 11-52% higher throughput than Vivado HLS implementations. Future work includes reducing the overlay area and exploring alternative interconnect architectures.
PERFORMANCE STUDIES ON THE VARIOUS ROUTING PROTOCOLS IN AD-HOC NETWORKS
Every protocol has its advantages and disadvantages in different scenarios. The choice of a routing protocol should be made carefully after considering every aspect we provided in this section (and possibly more).
Meteo I/O Introduction
MeteoIO is a meteorological data input/output library that aims to remove IO functions from physics engines, make IO easy to use and robust, and simplify data preparation. It supports reading data from various sources into standardized data structures and writing output. Plugins allow adding new data sources. It performs operations like data filtering, unit conversions, and spatial and temporal interpolation to produce complete meteorological datasets.
HPC DAY 2017 | Prometheus - energy efficient supercomputing
HPC DAY 2017 - http://www.hpcday.eu/
Prometheus - energy efficient supercomputing
Marek Magrys | Manager of Mass Storage Departament, ACC Cyfronet AGH-UST
Paralell
The document provides an introduction to parallel programming concepts. It discusses Flynn's taxonomy of parallel systems including SISD, SIMD, MIMD, and MISD models. It then gives examples of adding two vectors in parallel using different models like SISD, SIMD, SIMD-SIMT, MIMD-MPMD, and MIMD-SPMD. It also covers parallel programming concepts like synchronization, computational patterns like map, reduce, and pipeline, and data usage patterns like gather, scatter, subdivide and pack. Finally, it provides an overview of CUDA hardware including its memory model, execution model using kernels, blocks, threads and warps. It highlights some caveats of CUDA like data
STOR2RRD presentation from Common CZ/SK 2015
Storage performance monitoring tool (STOR2RRD) has been presented on Common CZ/SK conference at 9th of June 2015
Recommended
Responsive Distributed Routing Algorithm
Global routing topology.
loop-free paths . Dynamic distributed algorithm was rooted on this algorithm . Take Less Recovery Time(h) than previous algorithm (h^2) when Network Links fails .
Oss vs drive test pdcp throughput
1) A throughput testing was conducted using OSS and drive test methods on site LBHWL22 to compare the results.
2) Using multiple FTP sessions, throughput was measured every 15 minutes over 1 hour for a UE on the site.
3) The results showed that the drive test throughput was slightly higher than the OSS throughput, but both followed the same trend over time.
fccm2015-jain-presentation
The document proposes an efficient coarse-grained overlay architecture based on DSP blocks in FPGAs. It consists of a 2D array of tiles with a programmable functional unit and routing resources in each tile. The functional unit is implemented using the fully pipelined DSP48E1 block from Xilinx FPGAs to achieve high frequencies near 400MHz. Experimental results show the overlay can map compute kernels with up to 72 operations and achieves 11-52% higher throughput than Vivado HLS implementations. Future work includes reducing the overlay area and exploring alternative interconnect architectures.
PERFORMANCE STUDIES ON THE VARIOUS ROUTING PROTOCOLS IN AD-HOC NETWORKS
Every protocol has its advantages and disadvantages in different scenarios. The choice of a routing protocol should be made carefully after considering every aspect we provided in this section (and possibly more).
Meteo I/O Introduction
MeteoIO is a meteorological data input/output library that aims to remove IO functions from physics engines, make IO easy to use and robust, and simplify data preparation. It supports reading data from various sources into standardized data structures and writing output. Plugins allow adding new data sources. It performs operations like data filtering, unit conversions, and spatial and temporal interpolation to produce complete meteorological datasets.
HPC DAY 2017 | Prometheus - energy efficient supercomputing
HPC DAY 2017 - http://www.hpcday.eu/
Prometheus - energy efficient supercomputing
Marek Magrys | Manager of Mass Storage Departament, ACC Cyfronet AGH-UST
Paralell
The document provides an introduction to parallel programming concepts. It discusses Flynn's taxonomy of parallel systems including SISD, SIMD, MIMD, and MISD models. It then gives examples of adding two vectors in parallel using different models like SISD, SIMD, SIMD-SIMT, MIMD-MPMD, and MIMD-SPMD. It also covers parallel programming concepts like synchronization, computational patterns like map, reduce, and pipeline, and data usage patterns like gather, scatter, subdivide and pack. Finally, it provides an overview of CUDA hardware including its memory model, execution model using kernels, blocks, threads and warps. It highlights some caveats of CUDA like data
STOR2RRD presentation from Common CZ/SK 2015
Storage performance monitoring tool (STOR2RRD) has been presented on Common CZ/SK conference at 9th of June 2015
Achieving congestion diversity in multi hop wireless mesh networks
This paper compares congestion-aware routing algorithms like Backpressure (BP), Enhanced Backpressure (E-BP), and Congestion Diversity Protocol (CDP) to a shortest path routing protocol (LQSR) on a wireless mesh network testbed. The results show that under moderate to heavy UDP traffic, CDP significantly outperforms LQSR in 80-90% of cases, while BP and E-BP often degrade performance compared to LQSR for both UDP and TCP traffic. Shortest path routing fails to utilize available path diversity and can increase congestion and delay, especially with significant UDP traffic loads.
Network on Chip Architecture and Routing Techniques: A survey
This document summarizes research on Network on Chip (NOC) architecture and routing techniques. It discusses NOC topology options including mesh, torus, ring and irregular networks. It also reviews router architecture, switching techniques, virtual channels, buffering, error correction, quality of service implementations, and routing algorithms. Specific NOC implementations discussed include QNOC, Ethereal NOC, and SPIN NOC. The document provides an overview of research on improving performance and efficiency in NOC design.
Coscup2021 open source network os for datacenter
Open Source Network OS for Datacenter summarizes SONiC, an open source network operating system for datacenters. Key points include:
- SONiC uses a spine-leaf topology and supports VxLAN overlay networking with MP-BGP EVPN control plane.
- It has a modular architecture with components like SWSS for state synchronization, Orchagent for state processing, and SAI for hardware abstraction.
- Applications communicate through Redis databases and netlink messaging. Orchagent acts as a consumer and producer to process state between databases.
Network on chip by shoeb
Network on a chip is an approach where the communication features of large-scale integrated systems are implemented on a single silicon chip. It reduces complexity in wiring design and provides better power, speed and reliability compared to other designs. Network on a chip uses switches and links to route messages from source to destination modules in a scalable, homogeneous switched fabric network. It improves power efficiency and allows for features like multi-topology support in complex system-on-chip designs.
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
The document discusses trends in system-on-chip (SoC) and network-on-chip (NoC) architectures, including the integration of multiple CPU cores, hardware accelerators, and peripherals on a single chip connected by an on-chip network. NoCs are presented as a scalable solution to connect the growing number of computational resources in modern SoCs. Examples of ARM-based multicore SoCs including the big.LITTLE subsystem are provided to illustrate the challenges of cache coherency, interrupts, and task migration in multicore systems.
ODSA PoC: Network Flow Processor Overview
The document discusses a proposed network flow processor device for an ODSA proof of concept. It would include hardware accelerators for compute-intensive functions, high-performance distributed mesh fabric for multi-terabit bandwidth between processing elements, and tightly coupled memory engines and banks. It would provide optimal multi-threading between processing cores, hardware accelerators, and memory banks with the highest multi-threading silicon architecture. The device would extend Netronome's switch fabric using logic blocks interconnected by a terabit switch fabric and include an instruction-driven switch fabric for asynchronous memory traffic.
Univa and SUSE at SC17: Scaling Machine Learning for SUSE Linux Containers, S...
Armed with nothing more than an Apache Spark toting SUSE Linux laptop, you have all the trappings required to prototype the application of Machine Learning against your data-science needs. From programmability in Scala, Java or Python, to built-in support for Machine Learning via MLlib, Spark is an exceedingly effective enabler that allows you to rapidly produce results. Of course, as soon as your prototyping proves successful, you'll want to scale out to embrace the volume, variety and velocity that characterizes today's demands in Big Data Analytics ... in production. Because Spark is as comfortable on an isolated laptop as it is in a distributed-computing environment, addressing these ‘Big Data’ requirements in production boils down to effectively and efficiently embracing SUSE Linux containers, servers, clusters and clouds. As case studies will illustrate, this transition from prototype to production can be made successfully.
Managing Containerized HPC and AI Workloads on TSUBAME3.0
By leveraging the operating environment provided by SUSE Linux Enterprise Server, Univa® Grid Engine® manages workloads for the Tokyo Institute of Technology’s (TITECH) TSUBAME3.0 supercomputer. In many respects, this is an exceptional supercomputer that combines the leading-edge compute (Intel Xeon CPUs and NVIDIA Pascal P100 GPUs) and interconnect (Intel Omni-Path) capabilities demanded by traditional HPC as well as Deep Learning workloads. TITECH’s desire to make extensive use of containerization via Docker is also a distinctive aspect of the overall platform that currently is being implemented. As noted in booth presentations at past SC events, SUSE Linux and Univa Grid Engine have a highly complementary affinity for Docker containers. In this year’s presentation, aspects of TSUBAME3.0 motivated projects for managing containerized workloads will be highlighted.
ZigBee
ZigBee is a wireless networking standard used for low-power wireless personal area networks. It uses small, low-power digital radios based on the IEEE 802.15.4-2003 standard. ZigBee is typically used in wireless control and monitoring applications that require long battery life and secure networking. These include wireless light switches, electrical meters with in-home-displays, traffic management systems, and other consumer and industrial equipment that requires short-range wireless transfer of data at relatively low rates. ZigBee has three device types - coordinators, routers, and end devices that form personal area networks in both peer-to-peer and mesh configurations.
Presentation reliable NoC
This document discusses techniques for improving the reliability of Network-on-Chip (NoC) designs. It begins by explaining the importance of fault tolerance in NoCs due to increasing technology scales. It then describes different types of faults and provides an overview of current reliability techniques including error correction codes, retransmission mechanisms, reliable task mapping, and fault-tolerant routing. Specific schemes for self-healing routers, error detection, power analysis, and resilience against negative bias temperature instability are also summarized. The document concludes by stating that while these techniques improve reliability, most increase power consumption, and future work should focus on reducing this overhead through thermal-aware designs and methods to selectively wear out cores.
Deccan RubyConf 2016 - Lighning Talk - SpiceRub
This document summarizes the SPICE Toolkit, a software library that interprets data from NASA space science missions. The toolkit was initially developed in FORTRAN in 1982 but has since been ported to C and other languages. While the C API is complex, third-party wrappers like SpiceRub have created more intuitive interfaces in languages like Ruby. SpiceRub provides Ruby classes and methods that abstract away the low-level C API. It can be used to calculate values like the distance between objects in space using SPICE kernel data from past and current NASA missions.
Devils Logic PDR presentation
This document outlines a proposed CubeSat mission to study Phobos, one of Mars' moons. A network of 4 CubeSats would work together to overcome limitations of a single CubeSat. Two CubeSats would each carry a spectrometer and camera to analyze surface composition and image Phobos. A third CubeSat would carry an X-ray spectrometer. The fourth CubeSat would function as a communications relay between the network and Earth. This coordinated approach would allow for more comprehensive scientific analysis of Phobos compared to previous single-satellite missions.
Tsfpga
This document discusses the Matrix, TSFPGA, and DPGA architectures. Matrix is based on an array of identical primitive elements with a configurable interconnect network. It operates in a pipelined fashion. TSFPGA moves the value registers to the inputs of computational elements, allowing values to move between producer and consumer with minimum transit time independent of when the consumer will use the data. It uses input registers and broadcasts the current timestep so inputs can load values when their programmed load time matches. The basic building block of TSFPGA is the subarray tile containing LUTs and a central crossbar for switching.
Emerging Technologies in On-Chip and Off-Chip Interconnection Networks
This document proposes emerging technologies for on-chip and off-chip interconnection networks, including optical network-on-chip (OWN) and reconfigurable optical and wireless network-on-chip (R-OWN). OWN combines optical and wireless interconnects to overcome limitations of each individually. R-OWN extends OWN with reconfigurable wireless links to improve utilization and throughput. Simulations show OWN and R-OWN reduce area, energy, latency and improve throughput compared to wired-only and hybrid wireless baselines.
ICIECA 2014 Paper 10
The document describes a proposed approach to developing an efficient Fast Fourier Transform (FFT) module using dual edge triggered flip flops and clock gating. FFT is used to modulate data between time and frequency domains in OFDM systems. Traditionally, single edge triggered flip flops are used in FFT architectures. The proposed system realizes FFT using dual edge triggered flip flops, which can capture and propagate data on both clock edges, improving speed. Clock gating is also used to reduce clock power consumption. Simulation results show the proposed structure achieves higher processing speeds compared to traditional single edge triggered flip flop designs.
Mobile Ad-hoc and Sensor Networks
This document discusses the properties and spectrum needs of nodes in a mobile ad-hoc network (MANET). Key properties of MANETs include flexible network architecture, variable routing paths due to limited wireless range, neighbor discovery abilities, and protocol diversity between nodes. Spectrum needs at nodes are also variable due to their mobility and ability to reuse frequencies. Individual nodes in a MANET require much smaller spectrum needs than those in a fixed infrastructure network due to multi-hop routing and spatial frequency reuse between low-power transmissions.
Arteris network on chip: The growing cost of wires
Arteris NoC SoC Interconnect presentation given by Jonah Probell at ARM Technology Conference 9-11 Nov 2010. Explains how traditional AXI fabrics require huge numbers of wires and leads to routing congestion, and how network on chip interconnects address routing congestion by allowing fewer wires. Explains the basics of NoC packetization and serialization.
Cassandra 1.2 by Eddie Satterly
Cassandra version 1.2 introduced several new features including concurrent schema changes, virtual nodes, off-heap storage for metadata, improved JBOD functionality, query profiling and tracing, atomic batches, enhancements to CQL3 including collections, and more. These features aimed to improve performance, scalability, diagnostics, and flexibility of the Cassandra database.
Lustre, RoCE, and MAN
In this deck from the DDN User Group at ISC 2019, Marek Magryś from Cyfronet presents: Lustre, RoCE, and MAN.
"This talk will describe the architecture and implementation of high capacity Lustre file system for the need of a data intensive project. Storage is based on DDN ES7700 building block and uses RDMA over Converged Ethernet as network transport. What is unusual is that the storage system is located over 10 kilometers away from the supercomputer. Challenges, performance benchmarks and tuning will be the main topic of the presentation."
Watch the video: https://wp.me/p3RLHQ-kAn
Learn more: http://www.cyfronet.krakow.pl/
and
https://www.ddn.com/company/events/isc-user-group/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Alexander Ignatyev "MapReduce infrastructure"
This document summarizes Yandex's MapReduce implementation. It describes Yandex's MapReduce clusters which contain 5 clusters with 2000 hosts and store 10PB of data. It also describes the structure of MapReduce tables which are divided into chunks and records. The document outlines some of Yandex's MapReduce applications like mr_cat, mr_cp and mr_grep which function similar to UNIX tools. It provides an overview of the Map and Reduce operations in Yandex MapReduce.
Cisco crs1
The document provides an overview of the Cisco CRS-1 router. It discusses the router's distributed architecture with multiple line cards and a high-speed fabric. The fabric uses a multi-stage Benes switch design to provide multiple paths between cards. Each line card contains specialized silicon that can process packets at wire speed through independent packet processing engines. The router is designed to scale routing capacity and features through this distributed and programmable hardware architecture.
NUMA-aware Scalable Graph Traversal on SGI UV Systems
The document discusses NUMA-aware scalable graph traversal on SGI UV systems. It proposes an efficient NUMA-aware breadth-first search (BFS) algorithm for large-scale graph processing by pruning remote edge traversals. Numerical results on SGI UV 300 systems with 32 sockets show the algorithm achieves 219 billion traversed edges per second (GTEPS), setting a new single-node performance record on the Graph500 benchmark.
More Related Content
What's hot
Achieving congestion diversity in multi hop wireless mesh networks
This paper compares congestion-aware routing algorithms like Backpressure (BP), Enhanced Backpressure (E-BP), and Congestion Diversity Protocol (CDP) to a shortest path routing protocol (LQSR) on a wireless mesh network testbed. The results show that under moderate to heavy UDP traffic, CDP significantly outperforms LQSR in 80-90% of cases, while BP and E-BP often degrade performance compared to LQSR for both UDP and TCP traffic. Shortest path routing fails to utilize available path diversity and can increase congestion and delay, especially with significant UDP traffic loads.
Network on Chip Architecture and Routing Techniques: A survey
This document summarizes research on Network on Chip (NOC) architecture and routing techniques. It discusses NOC topology options including mesh, torus, ring and irregular networks. It also reviews router architecture, switching techniques, virtual channels, buffering, error correction, quality of service implementations, and routing algorithms. Specific NOC implementations discussed include QNOC, Ethereal NOC, and SPIN NOC. The document provides an overview of research on improving performance and efficiency in NOC design.
Coscup2021 open source network os for datacenter
Open Source Network OS for Datacenter summarizes SONiC, an open source network operating system for datacenters. Key points include:
- SONiC uses a spine-leaf topology and supports VxLAN overlay networking with MP-BGP EVPN control plane.
- It has a modular architecture with components like SWSS for state synchronization, Orchagent for state processing, and SAI for hardware abstraction.
- Applications communicate through Redis databases and netlink messaging. Orchagent acts as a consumer and producer to process state between databases.
Network on chip by shoeb
Network on a chip is an approach where the communication features of large-scale integrated systems are implemented on a single silicon chip. It reduces complexity in wiring design and provides better power, speed and reliability compared to other designs. Network on a chip uses switches and links to route messages from source to destination modules in a scalable, homogeneous switched fabric network. It improves power efficiency and allows for features like multi-topology support in complex system-on-chip designs.
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
The document discusses trends in system-on-chip (SoC) and network-on-chip (NoC) architectures, including the integration of multiple CPU cores, hardware accelerators, and peripherals on a single chip connected by an on-chip network. NoCs are presented as a scalable solution to connect the growing number of computational resources in modern SoCs. Examples of ARM-based multicore SoCs including the big.LITTLE subsystem are provided to illustrate the challenges of cache coherency, interrupts, and task migration in multicore systems.
ODSA PoC: Network Flow Processor Overview
The document discusses a proposed network flow processor device for an ODSA proof of concept. It would include hardware accelerators for compute-intensive functions, high-performance distributed mesh fabric for multi-terabit bandwidth between processing elements, and tightly coupled memory engines and banks. It would provide optimal multi-threading between processing cores, hardware accelerators, and memory banks with the highest multi-threading silicon architecture. The device would extend Netronome's switch fabric using logic blocks interconnected by a terabit switch fabric and include an instruction-driven switch fabric for asynchronous memory traffic.
Univa and SUSE at SC17: Scaling Machine Learning for SUSE Linux Containers, S...
Armed with nothing more than an Apache Spark toting SUSE Linux laptop, you have all the trappings required to prototype the application of Machine Learning against your data-science needs. From programmability in Scala, Java or Python, to built-in support for Machine Learning via MLlib, Spark is an exceedingly effective enabler that allows you to rapidly produce results. Of course, as soon as your prototyping proves successful, you'll want to scale out to embrace the volume, variety and velocity that characterizes today's demands in Big Data Analytics ... in production. Because Spark is as comfortable on an isolated laptop as it is in a distributed-computing environment, addressing these ‘Big Data’ requirements in production boils down to effectively and efficiently embracing SUSE Linux containers, servers, clusters and clouds. As case studies will illustrate, this transition from prototype to production can be made successfully.
Managing Containerized HPC and AI Workloads on TSUBAME3.0
By leveraging the operating environment provided by SUSE Linux Enterprise Server, Univa® Grid Engine® manages workloads for the Tokyo Institute of Technology’s (TITECH) TSUBAME3.0 supercomputer. In many respects, this is an exceptional supercomputer that combines the leading-edge compute (Intel Xeon CPUs and NVIDIA Pascal P100 GPUs) and interconnect (Intel Omni-Path) capabilities demanded by traditional HPC as well as Deep Learning workloads. TITECH’s desire to make extensive use of containerization via Docker is also a distinctive aspect of the overall platform that currently is being implemented. As noted in booth presentations at past SC events, SUSE Linux and Univa Grid Engine have a highly complementary affinity for Docker containers. In this year’s presentation, aspects of TSUBAME3.0 motivated projects for managing containerized workloads will be highlighted.
ZigBee
ZigBee is a wireless networking standard used for low-power wireless personal area networks. It uses small, low-power digital radios based on the IEEE 802.15.4-2003 standard. ZigBee is typically used in wireless control and monitoring applications that require long battery life and secure networking. These include wireless light switches, electrical meters with in-home-displays, traffic management systems, and other consumer and industrial equipment that requires short-range wireless transfer of data at relatively low rates. ZigBee has three device types - coordinators, routers, and end devices that form personal area networks in both peer-to-peer and mesh configurations.
Presentation reliable NoC
This document discusses techniques for improving the reliability of Network-on-Chip (NoC) designs. It begins by explaining the importance of fault tolerance in NoCs due to increasing technology scales. It then describes different types of faults and provides an overview of current reliability techniques including error correction codes, retransmission mechanisms, reliable task mapping, and fault-tolerant routing. Specific schemes for self-healing routers, error detection, power analysis, and resilience against negative bias temperature instability are also summarized. The document concludes by stating that while these techniques improve reliability, most increase power consumption, and future work should focus on reducing this overhead through thermal-aware designs and methods to selectively wear out cores.
Deccan RubyConf 2016 - Lighning Talk - SpiceRub
This document summarizes the SPICE Toolkit, a software library that interprets data from NASA space science missions. The toolkit was initially developed in FORTRAN in 1982 but has since been ported to C and other languages. While the C API is complex, third-party wrappers like SpiceRub have created more intuitive interfaces in languages like Ruby. SpiceRub provides Ruby classes and methods that abstract away the low-level C API. It can be used to calculate values like the distance between objects in space using SPICE kernel data from past and current NASA missions.
Devils Logic PDR presentation
This document outlines a proposed CubeSat mission to study Phobos, one of Mars' moons. A network of 4 CubeSats would work together to overcome limitations of a single CubeSat. Two CubeSats would each carry a spectrometer and camera to analyze surface composition and image Phobos. A third CubeSat would carry an X-ray spectrometer. The fourth CubeSat would function as a communications relay between the network and Earth. This coordinated approach would allow for more comprehensive scientific analysis of Phobos compared to previous single-satellite missions.
Tsfpga
This document discusses the Matrix, TSFPGA, and DPGA architectures. Matrix is based on an array of identical primitive elements with a configurable interconnect network. It operates in a pipelined fashion. TSFPGA moves the value registers to the inputs of computational elements, allowing values to move between producer and consumer with minimum transit time independent of when the consumer will use the data. It uses input registers and broadcasts the current timestep so inputs can load values when their programmed load time matches. The basic building block of TSFPGA is the subarray tile containing LUTs and a central crossbar for switching.
Emerging Technologies in On-Chip and Off-Chip Interconnection Networks
This document proposes emerging technologies for on-chip and off-chip interconnection networks, including optical network-on-chip (OWN) and reconfigurable optical and wireless network-on-chip (R-OWN). OWN combines optical and wireless interconnects to overcome limitations of each individually. R-OWN extends OWN with reconfigurable wireless links to improve utilization and throughput. Simulations show OWN and R-OWN reduce area, energy, latency and improve throughput compared to wired-only and hybrid wireless baselines.
ICIECA 2014 Paper 10
The document describes a proposed approach to developing an efficient Fast Fourier Transform (FFT) module using dual edge triggered flip flops and clock gating. FFT is used to modulate data between time and frequency domains in OFDM systems. Traditionally, single edge triggered flip flops are used in FFT architectures. The proposed system realizes FFT using dual edge triggered flip flops, which can capture and propagate data on both clock edges, improving speed. Clock gating is also used to reduce clock power consumption. Simulation results show the proposed structure achieves higher processing speeds compared to traditional single edge triggered flip flop designs.
Mobile Ad-hoc and Sensor Networks
This document discusses the properties and spectrum needs of nodes in a mobile ad-hoc network (MANET). Key properties of MANETs include flexible network architecture, variable routing paths due to limited wireless range, neighbor discovery abilities, and protocol diversity between nodes. Spectrum needs at nodes are also variable due to their mobility and ability to reuse frequencies. Individual nodes in a MANET require much smaller spectrum needs than those in a fixed infrastructure network due to multi-hop routing and spatial frequency reuse between low-power transmissions.
Arteris network on chip: The growing cost of wires
Arteris NoC SoC Interconnect presentation given by Jonah Probell at ARM Technology Conference 9-11 Nov 2010. Explains how traditional AXI fabrics require huge numbers of wires and leads to routing congestion, and how network on chip interconnects address routing congestion by allowing fewer wires. Explains the basics of NoC packetization and serialization.
Cassandra 1.2 by Eddie Satterly
Cassandra version 1.2 introduced several new features including concurrent schema changes, virtual nodes, off-heap storage for metadata, improved JBOD functionality, query profiling and tracing, atomic batches, enhancements to CQL3 including collections, and more. These features aimed to improve performance, scalability, diagnostics, and flexibility of the Cassandra database.
Lustre, RoCE, and MAN
In this deck from the DDN User Group at ISC 2019, Marek Magryś from Cyfronet presents: Lustre, RoCE, and MAN.
"This talk will describe the architecture and implementation of high capacity Lustre file system for the need of a data intensive project. Storage is based on DDN ES7700 building block and uses RDMA over Converged Ethernet as network transport. What is unusual is that the storage system is located over 10 kilometers away from the supercomputer. Challenges, performance benchmarks and tuning will be the main topic of the presentation."
Watch the video: https://wp.me/p3RLHQ-kAn
Learn more: http://www.cyfronet.krakow.pl/
and
https://www.ddn.com/company/events/isc-user-group/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Alexander Ignatyev "MapReduce infrastructure"
This document summarizes Yandex's MapReduce implementation. It describes Yandex's MapReduce clusters which contain 5 clusters with 2000 hosts and store 10PB of data. It also describes the structure of MapReduce tables which are divided into chunks and records. The document outlines some of Yandex's MapReduce applications like mr_cat, mr_cp and mr_grep which function similar to UNIX tools. It provides an overview of the Map and Reduce operations in Yandex MapReduce.
What's hot (20)
Achieving congestion diversity in multi hop wireless mesh networks
Achieving congestion diversity in multi hop wireless mesh networks
Network on Chip Architecture and Routing Techniques: A survey
Network on Chip Architecture and Routing Techniques: A survey
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
Univa and SUSE at SC17: Scaling Machine Learning for SUSE Linux Containers, S...
Univa and SUSE at SC17: Scaling Machine Learning for SUSE Linux Containers, S...
Managing Containerized HPC and AI Workloads on TSUBAME3.0
Managing Containerized HPC and AI Workloads on TSUBAME3.0
Emerging Technologies in On-Chip and Off-Chip Interconnection Networks
Emerging Technologies in On-Chip and Off-Chip Interconnection Networks
Arteris network on chip: The growing cost of wires
Arteris network on chip: The growing cost of wires
Similar to past-research-on-pc-router
Cisco crs1
The document provides an overview of the Cisco CRS-1 router. It discusses the router's distributed architecture with multiple line cards and a high-speed fabric. The fabric uses a multi-stage Benes switch design to provide multiple paths between cards. Each line card contains specialized silicon that can process packets at wire speed through independent packet processing engines. The router is designed to scale routing capacity and features through this distributed and programmable hardware architecture.
NUMA-aware Scalable Graph Traversal on SGI UV Systems
The document discusses NUMA-aware scalable graph traversal on SGI UV systems. It proposes an efficient NUMA-aware breadth-first search (BFS) algorithm for large-scale graph processing by pruning remote edge traversals. Numerical results on SGI UV 300 systems with 32 sockets show the algorithm achieves 219 billion traversed edges per second (GTEPS), setting a new single-node performance record on the Graph500 benchmark.
Brkdct 3101
The document provides an overview of the architecture of Nexus 9000 series switches and techniques for troubleshooting them. It discusses the modular components of Nexus 9500 switches including supervisors, fabrics, I/O modules, and line cards. It also covers tools for monitoring system health and detailed troubleshooting techniques. The goal is to provide an understanding of the Nexus 9000 architecture and introduce system telemetry and troubleshooting case scenarios.
Cisco CCNA Data Center Networking Fundamentals
The document provides an overview of Cisco's physical infrastructure technology for data centers. It discusses the three layers of data center infrastructure including the network, access, and aggregation/services layers. It then covers topics like Moore's law, serializer-deserializer technology, multi-lane distribution, switching architecture changes, switch-on-chip architectures, and modular switch platforms. The document aims to explain how Cisco has adapted its data center switching technology to address the challenges of exponentially increasing bandwidth over time.
SRv6 On-Path Delay Measurement with Anomaly Detection OPSAWG WG
(1) The hackathon established a multivendor SRv6 network topology with IPFIX data collection and processing to validate two implementations of on-path delay measurement. (2) Visualizations showed how SRv6 SID lists, on-path delays, and BGP updates changed with traffic engineering. (3) Network anomaly detection was enhanced to recognize increased delays.
Barcelona Supercomputing Center, Generador de Riqueza
El Barcelona Supercomputing Center (BSC) fue establecido en 2005 y alberga el MareNostrum, uno de los superordenadores más potentes de España. Somos el centro pionero de la supercomputación en España. Nuestra especialidad es la computación de altas prestaciones - también conocida como HPC o High Performance Computing- y nuestra misión es doble: ofrecer infraestructuras y servicio de supercomputación a los científicos españoles y europeos, y generar conocimiento y tecnología para transferirlos a la sociedad. Somos Centro de Excelencia Severo Ochoa, miembros de primer nivel de la infraestructura de investigación europea PRACE (Partnership for Advanced Computing in Europe), y gestionamos la Red Española de Supercomputación (RES). Como centro de investigación, contamos con más de 456 expertos de 45 países, organizados en cuatro grandes áreas de investigación: Ciencias de la computación, Ciencias de la vida, Ciencias de la tierra y aplicaciones computacionales en ciencia e ingeniería.
Recent advance in netmap/VALE(mSwitch)
This document summarizes recent advancements in netmap and VALE (mSwitch).
Netmap is a fast packet I/O mechanism that removes unnecessary metadata and reduces data copies between the NIC and user-space. VALE (mSwitch) is a netmap-based software switch that can achieve line-rate packet forwarding using a minimal packet representation and efficient forwarding algorithms. Evaluation shows the bare mSwitch can saturate 10Gbps links with low CPU usage and scales well with number of ports. The document outlines the key techniques that enable high performance, including netmap, list-based forwarding, and separating packet processing from the switching fabric.
End nodes in the Multigigabit era
This document discusses challenges and opportunities for end nodes with multigigabit networking. It covers increasing bandwidth capabilities through technologies like DWDM and 10GbE. It also examines hardware challenges for processor, memory, and I/O buses. Software challenges discussed include zero-copy networking, ULNI/OS bypass, and network path pipelining. The document also summarizes network protocols like AQM, ECN, MPLS and their roles in high-speed networking.
Lte overview titus
LTE is a cellular wireless system standard that uses OFDMA for downlink and SC-FDMA for uplink. Key LTE technologies include bandwidth flexibility, advanced antenna techniques like MIMO, link adaptation, inter-cell interference coordination, and a two-layered HARQ protocol to provide low latency and high reliability data transmission. LTE aims to improve spectral efficiency, reduce costs, support new services, and provide higher data rates and lower latencies compared to previous cellular standards.
Network-aware Data Management for Large Scale Distributed Applications, IBM R...
The document discusses network-aware data management for large-scale distributed applications. It provides an outline for a presentation on this topic, including discussing the performance of VSAN and VVOL storage in virtualized environments, the PetaShare distributed storage system and Stork data scheduler, data streaming in high-bandwidth networks, and several other related topics like network reservations and scheduling. The presenter's background and experience working on data transfer scheduling, distributed storage, and high-performance computing networks is also briefly summarized.
High performace network of Cloud Native Taiwan User Group
The document discusses high performance networking and summarizes a presentation about improving network performance. It describes drawbacks of the current Linux network stack, including kernel overhead and data copying. It then discusses approaches like DPDK and RDMA that can help improve performance by reducing overhead and enabling zero-copy data transfers. A case study is presented on using RDMA to improve TensorFlow performance by eliminating unnecessary data copies between devices.
cisco-n3k-c3064pq-10gx-datasheet.pdf
The N3K-C3064PQ-10GX is a 1RU Cisco Nexus switch with 48 SFP+ ports and 4 QSFP+ ports, providing 1.28 Tbps switching capacity and 950 million packets per second forwarding rate. It runs the Cisco NX-OS operating system and supports features like vPC, POAP, EEM, and PTP. The switch is suited for high-performance, cost-effective top-of-rack applications in data centers.
Distance Vector Multicast Routing Protocol (DVMRP) : Combined Presentation
The document discusses Distance Vector Multicast Routing Protocol (DVMRP), which is a multicast routing protocol used to route multicast data packets across subnets. It operates similarly to RIP, maintaining routing tables and sharing information with neighboring routers. DVMRP uses reverse path multicasting and initially floods packets to discover group members, then prunes paths where there are no members. It is suitable for use within autonomous systems.
NST Product Catalog
The document provides product information for various networking equipment made by NST Network Solutions, including:
- Ethernet switches ranging from managed layer 2 switches to managed layer 3 switches with Gigabit Ethernet and fiber uplink ports.
- PoE switches, industrial switches, wireless access points, media converters, voice equipment, and a network management software.
- For each product type, it lists specific models and provides brief descriptions of their key features, interfaces, functions, specifications, and management capabilities.
The document serves as a product catalog or guide for NST Network Solutions' networking equipment portfolio. It concisely summarizes the equipment types and key details about multiple models in 3 sentences or less per category
GPRS/EDGE Basics / knowledge sharing
This Presentation Gives Basics of GPRS and EDGE Network. With Brief Introduction to Advanced Ideas are shared in these slides.
802.11.ppt
This ppt is basically give information and details idea about IEEE 802.11 WLAN Standard
Bluetooth specifications and overview.
Performance Analysis of Mesh-based NoC’s on Routing Algorithms
The advent of System-on-Chip (SoCs), has brought about a need to increase the scale of multi-core chip networks. Bus Based communications have proved to be limited in terms of performance and ease of scalability, the solution to both bus – based and Point-to-Point (P2P) communication systems is to use a communication infrastructure called Network-on-Chip (NoC). Performance of NoC depends on various factors such as network topology, routing strategy and switching technique and traffic patterns. In this paper, we have taken the initiative to compile together a comparative analysis of different Network on Chip infrastructures based on the classification of routing algorithm, switching technique, and traffic patterns. The goal is to show how varied combinations of the three factors perform differently based on the size of the mesh network, using NOXIM, an open source SystemC Simulator of mesh-based NoC. The analysis has shown tenable evidence highlighting the novelty of XY routing algorithm.
100 M pps on PC.
This document discusses achieving very high speeds of 100 million packets per second (100Mpps) on commodity PC hardware using kernel bypassing techniques. It describes the company redCDN and their development of a DDoS mitigation solution called redGuardian. Key challenges discussed include the limitations of operating system network stacks at high speeds, hardware capabilities, and how data plane frameworks like DPDK can be used to bypass the OS and achieve wire-speed performance by accessing network interface cards directly from userspace.
Dynamic Routing All Algorithms, Working And Basics
This document provides information on computer networks and routing protocols. It discusses advantages and problems of computer networks. It then describes the Enhanced Interior Gateway Routing Protocol (EIGRP) and some of its key features like security, congestion handling, efficiency, and support for IPv4 and IPv6. It also discusses static and dynamic routing, different routing metrics, and compares EIGRP to other routing protocols like RIP, OSPF, and IS-IS.
An FPGA for high end Open Networking
The document discusses several topics related to open networking with FPGAs including:
1) High Performance Reconfigurable Computing (HPRC) and the performance of FPGAs for networking and computing.
2) A demonstration by Huawei and Xilinx of a 400 Gbps core router implemented on FPGA cards.
3) Interchip and interboard communication technologies like Interlaken.
4) OpenFlow and how it allows a controller to programmatically alter the forwarding behavior of switches.
5) Network emulation tools like Mininet that can be used to test OpenFlow applications and topologies without requiring physical hardware.
Similar to past-research-on-pc-router (20)
NUMA-aware Scalable Graph Traversal on SGI UV Systems
NUMA-aware Scalable Graph Traversal on SGI UV Systems
SRv6 On-Path Delay Measurement with Anomaly Detection OPSAWG WG
SRv6 On-Path Delay Measurement with Anomaly Detection OPSAWG WG
Barcelona Supercomputing Center, Generador de Riqueza
Barcelona Supercomputing Center, Generador de Riqueza
Network-aware Data Management for Large Scale Distributed Applications, IBM R...
Network-aware Data Management for Large Scale Distributed Applications, IBM R...
High performace network of Cloud Native Taiwan User Group
High performace network of Cloud Native Taiwan User Group
Distance Vector Multicast Routing Protocol (DVMRP) : Combined Presentation
Distance Vector Multicast Routing Protocol (DVMRP) : Combined Presentation
Performance Analysis of Mesh-based NoC’s on Routing Algorithms
Performance Analysis of Mesh-based NoC’s on Routing Algorithms
Dynamic Routing All Algorithms, Working And Basics
Dynamic Routing All Algorithms, Working And Basics
Recently uploaded
Apps Break Data
How information systems are built or acquired puts information, which is what they should be about, in a secondary place. Our language adapted accordingly, and we no longer talk about information systems but applications. Applications evolved in a way to break data into diverse fragments, tightly coupled with applications and expensive to integrate. The result is technical debt, which is re-paid by taking even bigger "loans", resulting in an ever-increasing technical debt. Software engineering and procurement practices work in sync with market forces to maintain this trend. This talk demonstrates how natural this situation is. The question is: can something be done to reverse the trend?
JavaLand 2024: Application Development Green Masterplan
My presentation slides I used at JavaLand 2024
Session 1 - Intro to Robotic Process Automation.pdf
👉 Check out our full 'Africa Series - Automation Student Developers (EN)' page to register for the full program:
https://bit.ly/Automation_Student_Kickstart
In this session, we shall introduce you to the world of automation, the UiPath Platform, and guide you on how to install and setup UiPath Studio on your Windows PC.
📕 Detailed agenda:
What is RPA? Benefits of RPA?
RPA Applications
The UiPath End-to-End Automation Platform
UiPath Studio CE Installation and Setup
💻 Extra training through UiPath Academy:
Introduction to Automation
UiPath Business Automation Platform
Explore automation development with UiPath Studio
👉 Register here for our upcoming Session 2 on June 20: Introduction to UiPath Studio Fundamentals: https://community.uipath.com/events/details/uipath-lagos-presents-session-2-introduction-to-uipath-studio-fundamentals/
LF Energy Webinar: Carbon Data Specifications: Mechanisms to Improve Data Acc...
This LF Energy webinar took place June 20, 2024. It featured:
-Alex Thornton, LF Energy
-Hallie Cramer, Google
-Daniel Roesler, UtilityAPI
-Henry Richardson, WattTime
In response to the urgency and scale required to effectively address climate change, open source solutions offer significant potential for driving innovation and progress. Currently, there is a growing demand for standardization and interoperability in energy data and modeling. Open source standards and specifications within the energy sector can also alleviate challenges associated with data fragmentation, transparency, and accessibility. At the same time, it is crucial to consider privacy and security concerns throughout the development of open source platforms.
This webinar will delve into the motivations behind establishing LF Energy’s Carbon Data Specification Consortium. It will provide an overview of the draft specifications and the ongoing progress made by the respective working groups.
Three primary specifications will be discussed:
-Discovery and client registration, emphasizing transparent processes and secure and private access
-Customer data, centering around customer tariffs, bills, energy usage, and full consumption disclosure
-Power systems data, focusing on grid data, inclusive of transmission and distribution networks, generation, intergrid power flows, and market settlement data
Columbus Data & Analytics Wednesdays - June 2024
Columbus Data & Analytics Wednesdays, June 2024 with Maria Copot 20
Main news related to the CCS TSI 2023 (2023/1695)
An English 🇬🇧 translation of a presentation to the speech I gave about the main changes brought by CCS TSI 2023 at the biggest Czech conference on Communications and signalling systems on Railways, which was held in Clarion Hotel Olomouc from 7th to 9th November 2023 (konferenceszt.cz). Attended by around 500 participants and 200 on-line followers.
The original Czech 🇨🇿 version of the presentation can be found here: https://www.slideshare.net/slideshow/hlavni-novinky-souvisejici-s-ccs-tsi-2023-2023-1695/269688092 .
The videorecording (in Czech) from the presentation is available here: https://youtu.be/WzjJWm4IyPk?si=SImb06tuXGb30BEH .
AppSec PNW: Android and iOS Application Security with MobSF
Mobile Security Framework - MobSF is a free and open source automated mobile application security testing environment designed to help security engineers, researchers, developers, and penetration testers to identify security vulnerabilities, malicious behaviours and privacy concerns in mobile applications using static and dynamic analysis. It supports all the popular mobile application binaries and source code formats built for Android and iOS devices. In addition to automated security assessment, it also offers an interactive testing environment to build and execute scenario based test/fuzz cases against the application.
This talk covers:
Using MobSF for static analysis of mobile applications.
Interactive dynamic security assessment of Android and iOS applications.
Solving Mobile app CTF challenges.
Reverse engineering and runtime analysis of Mobile malware.
How to shift left and integrate MobSF/mobsfscan SAST and DAST in your build pipeline.
Connector Corner: Seamlessly power UiPath Apps, GenAI with prebuilt connectors
Join us to learn how UiPath Apps can directly and easily interact with prebuilt connectors via Integration Service--including Salesforce, ServiceNow, Open GenAI, and more.
The best part is you can achieve this without building a custom workflow! Say goodbye to the hassle of using separate automations to call APIs. By seamlessly integrating within App Studio, you can now easily streamline your workflow, while gaining direct access to our Connector Catalog of popular applications.
We’ll discuss and demo the benefits of UiPath Apps and connectors including:
Creating a compelling user experience for any software, without the limitations of APIs.
Accelerating the app creation process, saving time and effort
Enjoying high-performance CRUD (create, read, update, delete) operations, for
seamless data management.
Speakers:
Russell Alfeche, Technology Leader, RPA at qBotic and UiPath MVP
Charlie Greenberg, host
Dandelion Hashtable: beyond billion requests per second on a commodity server
This slide deck presents DLHT, a concurrent in-memory hashtable. Despite efforts to optimize hashtables, that go as far as sacrificing core functionality, state-of-the-art designs still incur multiple memory accesses per request and block request processing in three cases. First, most hashtables block while waiting for data to be retrieved from memory. Second, open-addressing designs, which represent the current state-of-the-art, either cannot free index slots on deletes or must block all requests to do so. Third, index resizes block every request until all objects are copied to the new index. Defying folklore wisdom, DLHT forgoes open-addressing and adopts a fully-featured and memory-aware closed-addressing design based on bounded cache-line-chaining. This design offers lock-free index operations and deletes that free slots instantly, (2) completes most requests with a single memory access, (3) utilizes software prefetching to hide memory latencies, and (4) employs a novel non-blocking and parallel resizing. In a commodity server and a memory-resident workload, DLHT surpasses 1.6B requests per second and provides 3.5x (12x) the throughput of the state-of-the-art closed-addressing (open-addressing) resizable hashtable on Gets (Deletes).
Taking AI to the Next Level in Manufacturing.pdf
Read Taking AI to the Next Level in Manufacturing to gain insights on AI adoption in the manufacturing industry, such as:
1. How quickly AI is being implemented in manufacturing.
2. Which barriers stand in the way of AI adoption.
3. How data quality and governance form the backbone of AI.
4. Organizational processes and structures that may inhibit effective AI adoption.
6. Ideas and approaches to help build your organization's AI strategy.
“Temporal Event Neural Networks: A More Efficient Alternative to the Transfor...
“Temporal Event Neural Networks: A More Efficient Alternative to the Transfor...Edge AI and Vision Alliance
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2024/06/temporal-event-neural-networks-a-more-efficient-alternative-to-the-transformer-a-presentation-from-brainchip/
Chris Jones, Director of Product Management at BrainChip , presents the “Temporal Event Neural Networks: A More Efficient Alternative to the Transformer” tutorial at the May 2024 Embedded Vision Summit.
The expansion of AI services necessitates enhanced computational capabilities on edge devices. Temporal Event Neural Networks (TENNs), developed by BrainChip, represent a novel and highly efficient state-space network. TENNs demonstrate exceptional proficiency in handling multi-dimensional streaming data, facilitating advancements in object detection, action recognition, speech enhancement and language model/sequence generation. Through the utilization of polynomial-based continuous convolutions, TENNs streamline models, expedite training processes and significantly diminish memory requirements, achieving notable reductions of up to 50x in parameters and 5,000x in energy consumption compared to prevailing methodologies like transformers.
Integration with BrainChip’s Akida neuromorphic hardware IP further enhances TENNs’ capabilities, enabling the realization of highly capable, portable and passively cooled edge devices. This presentation delves into the technical innovations underlying TENNs, presents real-world benchmarks, and elucidates how this cutting-edge approach is positioned to revolutionize edge AI across diverse applications."Choosing proper type of scaling", Olena Syrota
Imagine an IoT processing system that is already quite mature and production-ready and for which client coverage is growing and scaling and performance aspects are life and death questions. The system has Redis, MongoDB, and stream processing based on ksqldb. In this talk, firstly, we will analyze scaling approaches and then select the proper ones for our system.
Astute Business Solutions | Oracle Cloud Partner |
Your goto partner for Oracle Cloud, PeopleSoft, E-Business Suite, and Ellucian Banner. We are a firm specialized in managed services and consulting.
inQuba Webinar Mastering Customer Journey Management with Dr Graham Hill
HERE IS YOUR WEBINAR CONTENT! 'Mastering Customer Journey Management with Dr. Graham Hill'. We hope you find the webinar recording both insightful and enjoyable.
In this webinar, we explored essential aspects of Customer Journey Management and personalization. Here’s a summary of the key insights and topics discussed:
Key Takeaways:
Understanding the Customer Journey: Dr. Hill emphasized the importance of mapping and understanding the complete customer journey to identify touchpoints and opportunities for improvement.
Personalization Strategies: We discussed how to leverage data and insights to create personalized experiences that resonate with customers.
Technology Integration: Insights were shared on how inQuba’s advanced technology can streamline customer interactions and drive operational efficiency.
A Deep Dive into ScyllaDB's Architecture
This talk will cover ScyllaDB Architecture from the cluster-level view and zoom in on data distribution and internal node architecture. In the process, we will learn the secret sauce used to get ScyllaDB's high availability and superior performance. We will also touch on the upcoming changes to ScyllaDB architecture, moving to strongly consistent metadata and tablets.
Skybuffer SAM4U tool for SAP license adoption
Manage and optimize your license adoption and consumption with SAM4U, an SAP free customer software asset management tool.
SAM4U, an SAP complimentary software asset management tool for customers, delivers a detailed and well-structured overview of license inventory and usage with a user-friendly interface. We offer a hosted, cost-effective, and performance-optimized SAM4U setup in the Skybuffer Cloud environment. You retain ownership of the system and data, while we manage the ABAP 7.58 infrastructure, ensuring fixed Total Cost of Ownership (TCO) and exceptional services through the SAP Fiori interface.
Must Know Postgres Extension for DBA and Developer during Migration
Mydbops Opensource Database Meetup 16
Topic: Must-Know PostgreSQL Extensions for Developers and DBAs During Migration
Speaker: Deepak Mahto, Founder of DataCloudGaze Consulting
Date & Time: 8th June | 10 AM - 1 PM IST
Venue: Bangalore International Centre, Bangalore
Abstract: Discover how PostgreSQL extensions can be your secret weapon! This talk explores how key extensions enhance database capabilities and streamline the migration process for users moving from other relational databases like Oracle.
Key Takeaways:
* Learn about crucial extensions like oracle_fdw, pgtt, and pg_audit that ease migration complexities.
* Gain valuable strategies for implementing these extensions in PostgreSQL to achieve license freedom.
* Discover how these key extensions can empower both developers and DBAs during the migration process.
* Don't miss this chance to gain practical knowledge from an industry expert and stay updated on the latest open-source database trends.
Mydbops Managed Services specializes in taking the pain out of database management while optimizing performance. Since 2015, we have been providing top-notch support and assistance for the top three open-source databases: MySQL, MongoDB, and PostgreSQL.
Our team offers a wide range of services, including assistance, support, consulting, 24/7 operations, and expertise in all relevant technologies. We help organizations improve their database's performance, scalability, efficiency, and availability.
Contact us: info@mydbops.com
Visit: https://www.mydbops.com/
Follow us on LinkedIn: https://in.linkedin.com/company/mydbops
For more details and updates, please follow up the below links.
Meetup Page : https://www.meetup.com/mydbops-databa...
Twitter: https://twitter.com/mydbopsofficial
Blogs: https://www.mydbops.com/blog/
Facebook(Meta): https://www.facebook.com/mydbops/
Recently uploaded (20)
JavaLand 2024: Application Development Green Masterplan
JavaLand 2024: Application Development Green Masterplan
Overcoming the PLG Trap: Lessons from Canva's Head of Sales & Head of EMEA Da...
Overcoming the PLG Trap: Lessons from Canva's Head of Sales & Head of EMEA Da...
Session 1 - Intro to Robotic Process Automation.pdf
Session 1 - Intro to Robotic Process Automation.pdf
LF Energy Webinar: Carbon Data Specifications: Mechanisms to Improve Data Acc...
LF Energy Webinar: Carbon Data Specifications: Mechanisms to Improve Data Acc...
AppSec PNW: Android and iOS Application Security with MobSF
AppSec PNW: Android and iOS Application Security with MobSF
Connector Corner: Seamlessly power UiPath Apps, GenAI with prebuilt connectors
Connector Corner: Seamlessly power UiPath Apps, GenAI with prebuilt connectors
Dandelion Hashtable: beyond billion requests per second on a commodity server
Dandelion Hashtable: beyond billion requests per second on a commodity server
“Temporal Event Neural Networks: A More Efficient Alternative to the Transfor...
“Temporal Event Neural Networks: A More Efficient Alternative to the Transfor...
Nordic Marketo Engage User Group_June 13_ 2024.pptx
Nordic Marketo Engage User Group_June 13_ 2024.pptx
Astute Business Solutions | Oracle Cloud Partner |
Astute Business Solutions | Oracle Cloud Partner |
inQuba Webinar Mastering Customer Journey Management with Dr Graham Hill
inQuba Webinar Mastering Customer Journey Management with Dr Graham Hill
Must Know Postgres Extension for DBA and Developer during Migration
Must Know Postgres Extension for DBA and Developer during Migration
past-research-on-pc-router
- 2. 目次 • Click (452Kpps/333Kpps) (ACM SOSP ’99) • RouteBricks (18.96Mpps/12(?)Mpps) (ACM SOSP ‘09) • PacketShader (58.4Mpps/50+(?)Mpps) (ACM SIGCOMM ’11) • NetMap (USENIX ATC ’12) • DIR-24-8-BASIC • Waldvogel
- 3. • E. Kohler, R. Morris, B. Chen, J. Jannotti, and M. F. Kaashoek., “The Click modular router”, ACM Transactions on Computer Systems 18(3), August 2000, pages 263- 297. • SOSP ‘99, TOCS ’00 • Still active – Used in SEATTLE(SIGCOMM’08) – Used in RouteBricks(SOSP’09) – Last release: 2011/09/24 – Last commit: 2014/04/06 • Interrupt v.s. Polling (i.e., spin-wait, busy-wait) • Pentium III 700 MHz, 100Mbps Ether DEC tulip PCI, … • Linux 84kpps, Polling Linux 284kpps • Routing 333kpps, Forwarding 452kpps • Time taken: 2,798 ns/packet Click Modular Router (1)
- 4. Click Modular Router (2)
- 5. RouteBricks (1) • M. Dobrescu, N. Egi, K. Argyraki, B.-G. Chun, K. Fall, Gianluca Iannaccone, Allan Knies, Maziar Manesh, Sylvia Ratnasamy, “RouteBricks: Exploiting Parallelism To Scale Software Routers, ” 22nd ACM Symposium on Operating Systems Principles (SOSP), October 2009 • SOSP ’09 • Click-base • Leverages: – multi-cores. – multi-queue NICs. – batch processing. • NUMA-aware data placement didn’t make differences (in contrast to PacketShader). • Achieved 18.96Mpps Forwarding, 12(?)Mpps Routing • (Routing: 256K routes with memory expansion (DIR-24-8-BASIC))
- 7. PacketShader (1) • S. Han, K. Jang, K. Park and S. Moon. “PacketShader: a GPU-accelerated Software Router.” In proceedings of ACM SIGCOMM 2010, Delhi, India. September 2010. • Speeds routing lookups (not just forwarding) • Forwarding: 41.1 Gbps or 58.4 Mpps • IPv4 Routing (DIR-24-8-BASIC, 282K routes): 39Gbps. • IPv6 Routing (Waldvogel, 200K routes): 38Gbps. • Up to 130us/200us (IPv4/IPv6) routing delay (260us/400us for roundtrip)
- 8. PacketShader (2) • Not a pps-limitation ?
- 9. PacketShader (3) (a) Cores contend for queues. Leads to expensive cache bouncing and lock contention. (b) Better coupling of queues and cores. pipeline batch pipeline • Buffer management • Pipelining • Batch processing • Decoupling among queues and cores
- 10. NetMap (1) • Luigi Rizzo, “netmap: a novel framework for fast packet I/O,” Usenix ATC'12, Boston, June 2012 • Forwarding 14.88 Mpps (1 core 900 MHz) • Objective: to move packets quickly between the apps and the network cards. • Reduced copy, modified buffer management. • Protection. User-land v.s. Kernel. • 408 ns / batch. • Implementation on Linux/FreeBSD/Click.
- 11. NetMap (2)
- 12. Techniques • Polling (i.e., spin-wait or busy-wait) • Parallelization – i.e., multi-queues, multi-cores, GPUs • Pipelining • Reduce overhead – Batch processing (amortized over a batch) – Remove copy, improve buffer managements
- 13. Routing tables
- 14. DIR-24-8-BASIC • P. Gupta, S. Lin, and N. McKeown. “Routing Lookups in Hardware at Memory Access Speeds.” In Proceedings of the IEEE INFOCOM Conference, San Francisco, CA, USA, March 1998. • INFOCOM ‘98
- 15. Waldvogel • M. Waldvogel, G. Varghese, J. Turner, B. Plattner. “Scalable High-Speed IP Routing Lookups.” Proc. ACM SIGCOMM 1997 , pp. 25-36, Cannes, France.