1. Nandita Datt Mysore Gurudatt
2600 Waterview Parkway, Richardson,TX | nandita.dmg@gmail.com | https://www.linkedin.com/in/nanditadatt
OBJECTIVE
Electrical Engineering Graduate actively seeking full-time in VLSI Design/ ASIC Design/ DFT/Verification
EDUCATION
University of Texas at Dallas, Richardson, TX Jan 2015-Dec2016
MS in Electrical Engineering (Digital Systems) GPA 3.85/4
R.V College of Engineering, Bangalore June 2013
BS in Electrical Engineering GPA 8.59/10
TECHNICAL SKILLS
Languages: Verilog, C, System Verilog, Perl
Tools : Cadence tools- Virtuoso Platform, Spectre, EDI Encounter, Analog Design Environment;
Simplescalar; IDE- Xilinx; Synopsys Tools- Design Vision, SiliconSmart, Primetime, Waveview, Hspice, Tetramax; AWR VSS
RELEVANT COURSEWORK
VLSI Design, Advanced VLSI Design, Application Specific IC Design, Testing & Testable Design, Computer Architecture,
Advanced Digital Logic, Microprocessors, RF Systems & Engineering, Digital Signal Processing.
ACADEMIC PROJECTS
ASIC Design of MSDAP chip for Hearing aid application (Current project)
 Designed a Low Power DSP chip for hearing aid application and optimized it for minimum chip area, power and timing
constraints. Implementation of FIR filter at structural level for the audio processor chip. Performed physical design using
IC Compiler. Verified the functionality of the chip using RTL simulations and GLS.
Optimization of Cache Hierarchy of an Alpha 21264 EV6 Microprocessor
 Cache hierarchy of an Alpha microprocessor was fine-tuned using cache simulator (Simplesclar-3.0) based on the three
benchmarks namely, ANAGRAM, GCC and GO by varying the various cache design parameters such as block size,
replacement policy, associativity, unified and split caches. Optimized configuration was chosen based on CPI, performance and
cost.
Custom design and Layout of a 14bx14b Booth Multiplier using IBM 130nm technology
 Manual Layout of encoder, partial product multiplexer, add block, compressor and carry propagate adder (ripple carry adder +
carry look ahead adder + carry select adder) was done using Cadence Virtuoso for optimizing power and delay. Functionality of
the design was verified using Cadence ADE and Hspice.
 Characterized the library using Synopsys SiliconSmart, flattened the netlist using Design Vision, Static Timing Analysis and
delay optimization was performed using Synopsys Primetime.
Design of a Radar mechanism to detect boats on a Lake (The Waitress Drone)
 Designed a radar system, comprising of transmit-receive blocks, that replaces a camera in a drone.
 Designed a communication link to communicate between drone and base station. The simulations were done on AWR VSS.
 Doppler Effect is used to detect the boat. The radar sends series of pulses in the region of interest and if any moving object is
detected, the pulses are reflected back to the radar. The distance of boat from drone is measured by comparing the frequency of
the received signal to a reference (usually the transmission signal).
Reverse Engineered an ARM processor and performed computation Fibonacci series
 The user mode of ARM processor is reverse engineered to execute branch and branch with link instruction, data processing
instruction, software interrupt and undefined instruction.
 Decoder, program counter, register file, barrel shifter, adder, instruction memory are designed to execute Fibonacci series (C
program is converted to object code).
EXPERIENCE
Single cell Isolation using DVD optical pickup - IISc (Indian Institute of science), Bangalore, India Feb-May2013
 A single-cell isolation system incorporating a DVD re-writable optical pickup was developed.
 Custom made modules have the required laser power and focusing optics to provide a steady Gaussian beam capable of
optically trapping micron-sized colloids and red blood cells.
WORK AUTHORIZATION
I possess EAD (Employment Authorization Doc) that allows me to work in the US.