The 8085 CPU communicates with other units using a 16-bit address bus, 8-bit data bus, and control bus. It has 16 address lines that can access up to 64K memory locations. The data bus is bidirectional and has 8 lines. The 8085 also has internal registers like the accumulator, flag bits, program counter, and stack pointer to perform operations and sequence instruction execution. It uses different addressing modes like immediate, register, and memory to specify the source and destination operands.

1. 1
The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU – Micro Processing Unit) communicates with the other
units using a 16-bit address bus, an 8-bit data bus and a control bus.

2. 2
The 8085 Bus Structure
Address Bus
 Consists of 16 address lines: A0 – A15
 Operates in unidirectional mode: The address bits are always sent from
the MPU to peripheral devices, not reverse.
 16 address lines are capable of addressing a
total of 216 = 65,536 (64k) memory locations.
 Address locations: 0000 (hex) – FFFF (hex)

3. 3
The 8085 Bus Structure
Data Bus
 Consists of 8 data lines: D0 – D7
 Operates in bidirectional mode: The data bits are sent from the
MPU to peripheral devices, as well as from the peripheral devices to
the MPU.
 Data range: 00 (hex) – FF (hex)
Control Bus
 Consists of various lines carrying the control signals such as read /
write enable, flag bits.

4. The 8085: CPU Internal Structure
The internal architecture of the 8085 CPU is
capable of performing the following operations:
 Store 8-bit data (Registers, Accumulator)
 Perform arithmetic and logic operations (ALU)
 Test for conditions (IF / THEN)
 Sequence the execution of instructions
 Store temporary data in RAM during execution
4

5. The 8085: CPU Internal Structure
5
Simplified block diagram

6. 6
The 8085: Registers

7. The 8085: CPU Internal Structure
Registers
 Six general purpose 8-bit registers: B, C, D, E, H, L
 They can also be combined as register pairs to
perform 16-bit operations: BC, DE, HL
 Registers are programmable (data load, move, etc.)
Accumulator
 Single 8-bit register that is part of the ALU !
 Used for arithmetic / logic operations – the result is always stored in
the accumulator.
7

8. The 8085: CPU Internal Structure
Flag Bits
 Indicate the result of condition tests.
 Carry, Zero, Sign, Parity, etc.
 Conditional operations (IF / THEN) are executed based on the condition of
these flag bits.
Program Counter (PC)
 Contains the memory address (16 bits) of the instruction that will be
executed in the next step.
Stack Pointer (SP)
8

9. FFeeaattuurreess ooff 88008866
-- 88008866 iiss aa 1166 bbiitt mmiiccrroopprroocceessssoorr,, IItt ccaann
ppeerrffoorrmm rreeaadd && wwrriittee ooppeerraattiioonn oonn bbootthh 88 oorr
1166 bbiitt ddaattaa....
-- 88008866 hhaass 1166 bbiitt ddaattaa bbuuss && 2200 bbiitt aaddddrreessss
bbuuss..
9 9

10. FFeeaattuurreess ooff 88008866 (( ccoonnttiinnuueedd))
-- 2200 bbiitt aaddddrreessss lliinneess ccaappaabbllee ooff aaddddrreessssiinngg
11MMBB mmeemmoorryy llooccaattiioonn
-- 1166 bbiitt ddaattaa aarree ssttoorreedd iinn 22 ccoonnsseeccuuttiivvee
mmeemmoorryy llooccaattiioonnss
-- 88008866 ccaann ggeenneerraattee 1166 bbiitt II//OO aaddddrreessss ,, 225566
== 6655553366 II//OO ppoorrttss
10 10

11. FFeeaattuurreess ooff 88008866 (( ccoonnttiinnuueedd))
-- 88008866 hhaass ffoouurrtteeeenn 1166 bbiitt rreeggiisstteerrss
-- 88008866 hhaass mmuullttiipplleexxeedd aaddddrreessss && ddaattaa bbuuss
-- 88008866 ooppeerraatteess iinn 22 mmooddeess ,, mmiinniimmuumm(( ssiinnggllee
pprroocceessssoorr )) && mmaaxxiimmuumm(( mmuullttii pprroocceessssoorr))
mmooddeess
-- 88008866 hhaass 66 bbyyttee pprreeffeettcchh iinnssttrruuccttiioonn QQuueeuuee
11 11

12. RReeggiisstteerrss OOrrggaanniissaattiioonn
• 16-Bit General Purpose Registers
– can access all 16-bits at once
– can access just high (H) byte, or low (L)
byte
only the General
Purpose registers
allow access as
8-bit High/Low
sub-registers
12 12

13. RReeggiisstteerrss OOrrggaanniissaattiioonn ((ccoonnttiinnuueedd))
• Register Set
16-Bit Segment Addressing Registers
CS Code Segment
DS Data Segment
SS Stack Segment
ES Extra Segment
13 13

14. RReeggiisstteerrss OOrrggaanniissaattiioonn ((ccoonnttiinnuueedd))
16-Bit Offset Addressing Registers
SP Stack Pointer
BP Base Pointer
SI Source Index
DI Destination Index
14 14

15. RReeggiisstteerrss OOrrggaanniissaattiioonn ((ccoonnttiinnuueedd))
16-Bit Control/Status Registers
- IP Instruction Pointer (Program Counter
for execution control)
- FLAGS 16-bit register
• It is not a 16-bit value but it is a
collection of 9 bit-flags (six are unused)
• Flag is set when it is equal to 1
• Flag is clear when it is equal to 0
15 15

16. AArrcchhiitteeccttuurree
16 16

17. AArrcchhiitteeccttuurree ((ccoonnttiinnuueedd))
• The 8086 has two parts, the Bus Interface Unit
(BIU) and the Execution Unit (EU).
• The BIU fetches instructions, reads and writes
data, and computes the 20-bit address
• The EU decodes and executes the instructions
using the 16-bit ALU.
17 17

18. AArrcchhiitteeccttuurree ((ccoonnttiinnuueedd))
• The BIU contains the following registers
- IP - the Instruction Pointer
- CS - the Code Segment Register
- DS - the Data Segment Register
- SS - the Stack Segment Register
- ES - the Extra Segment Register
18 18

19. AArrcchhiitteeccttuurree ((ccoonnttiinnuueedd))
• The BIU fetches instructions using the CS and
IP, written CS:IP, to construct the 20-bit
address. Data is fetched using a segment
register (usually the DS) and an effective
address (EA) computed by the EU depending
on the addressing mode
19 19

20. AArrcchhiitteeccttuurree ((ccoonnttiinnuueedd))
• The EU contains the following 16-bit general
purpose registers:
» AX - the Accumulator
» BX - the Base Register
» CX - the Count Register
» DX - the Data Register
» SP - the Stack Pointer defaults to
» BP - the Base Pointer / Stack segment
» SI - the Source Index Register
» DI - the Destination Register
20 20

21. AArrcchhiitteeccttuurree ((ccoonnttiinnuueedd))
HIGH BYTE GP REGISTERS LOW BYTE
AH
BH
CH
DH
AX
BX
CX
DX
21 21
AL
BL
CL
DL
8 BIT 16 BIT 8 BIT

22. AArrcchhiitteeccttuurree ((ccoonnttiinnuueedd))
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
FLAGS
AX
BX
CX
DX
22 22
Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index Register
Destination Index Register
BIU registers
(20 bit adder)
EU registers
16 bit arithmetic

23. GGeenneerraall ppuurrppoossee RReeggiisstteerrss
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and
data transfer instructions because it generates
the shortest Machine Language Code
– Must be used in multiplication and division
operations
– Must also be used in I/O operations
23 23

24. GGeenneerraall ppuurrppoossee RReeggiisstteerrss ((ccoonnttii....))
• BX
– Base Register
– Also serves as an address register
– Used in array operations
– Used in Table Lookup operations (XLAT )
24 24

25. GGeenneerraall ppuurrppoossee RReeggiisstteerrss ((ccoonnttii....))
• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations
• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations
25 25

26. PPooiinntteerr && IInnddeexx RReeggiisstteerrss
• Contain the offset addresses of memory
locations
• Can also be used in arithmetic and other
operations
• SP: Stack pointer
– Used with SS to access the stack segment
26 26

27. Pointer && IInnddeexx RReeggiisstteerrss ((ccoonnttiinnuueedd))
• BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments
• SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI
register points to memory locations in the data
segment which is addressed by the DS register.
Thus, SI is associated with the DS in string
operations.
27 27

28. Pointer && IInnddeexx RReeggiisstteerrss ((ccoonnttiinnuueedd))
• DI: Destination Index register
– is also required for some string operations.
– When string operations are performed, the DI
register points to memory locations in the data
segment which is addressed by the ES register.
Thus, DI is associated with the ES in string
operations.
• The SI and the DI registers may also be used to
access data stored in arrays
28 28

29. SSeeggmmeenntt RReeggiisstteerrss
• Are Address registers
• Store the memory addresses of instructions
and data
• Memory Organization
– Each byte in memory has a 20 bit address starting
with 0 to 220-1 or 1 meg of addressable memory
29 29

30. SSeeggmmeenntt RReeggiisstteerrss ((ccoonnttiinnuueedd))
– Addresses are expressed as 5 hex digits from
00000 - FFFFF
– Problem: But 20 bit addresses are TOO BIG to fit
in 16 bit registers!
– Solution: Memory Segment
• Block of 64K (65,536) consecutive memory bytes
• A segment number is a 16 bit number
30 30

31. SSeeggmmeenntt RReeggiisstteerrss ((ccoonnttiinnuueedd))
• Segment numbers range from 0000 to FFFF
• Within a segment, a particular memory
location is specified with an offset
• An offset also ranges from 0000 to FFFF
31 31

32. SSeeggmmeenntt RReeggiisstteerrss ((ccoonnttiinnuueedd))
Memory Model for 20-bit Address Space
32 32

33. • to calculate physical memory address
33 33

34. Memory Address Generation
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Adder
Physical Address (20 Bits)
34 34

35. FFllaagg RReeggiisstteerr
35 35
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign
6 are status flags
3 are control flag

36. 36
8086 Addressing Modes

37. What is the Addressing Mode ?
add dest, source ; dest +source→dest
add ax,bx ; ax +bx→ax
The addressing mode means where and how the
CPU gets the operands when the instruction is
executed.
37

38. 38
• Addressing modes ffoorr SSeeqquueennttiiaall CCoonnttrrooll
TTrraannssffeerr IInnssttrruuccttiioonnss
--------TThheessee IInnssttrruuccttiioonnss ttrraannssffeerr ccoonnttrrooll ttoo tthhee
nneexxtt sseeqquueennttiiaall iinnssttrruuccttiioonn iinn tthhee pprrooggrraamm
• AAddddrreessssiinngg mmooddeess ffoorr CCoonnttrrooll TTrraannssffeerr
IInnssttrruuccttiioonnss
----------TThheessee IInnssttrruuccttiioonnss ttrraannssffeerr ccoonnttrrooll ttoo
ssoommee pprreeddeeffiinneedd aaddddrreessss EExx::IINNTT CCAALLLL

39. 39
AAddddrreessssiinngg mmooddeess ffoorr SSeeqquueennttiiaall
CCoonnttrrooll
TTrraannssffeerr IInnssttrruuccttiioonnss
Three types of 8086 addressing modes
• Immediate Addressing Mode
---CPU gets the operand from the instruction
• Register Addressing Mode
---CPU gets the operand from one of the internal registers
• Memory Addressing Mode
---CPU gets the operand from the memory location(s)

40. 40
1. Immediate Addressing Mode
Exp
MOV AL, 80H
Machine code:B080H
AL
Instruction Queue
B0H
80H
MACHINE
CODE
MOV AX, 1234H
Machine Code:B83412H
Instruction Queue
B8
12H
AL
MACHINE
CODE
AH
34H
34
12
80H
12 34

41. 41
2. Register Addressing Mode
Exp： MOV AX, CX
Memory
89
C1
AX
CX Machine code

42. 3. Memory Addressing Mode
• Specify an offset address (effective address) using expressions of the form (different parts of
expression are optional):
– [ Base Register + Index Register+ Displacement]
• 1) Base Register---BX, BP
• 2) Index Register---SI, DI
• 3) Displacement ---constant value
• Example: 1) add ax,[20h] 2) add ax,[bx]
42
3) add ax,[bx+20h] 4) add ax, [bx+si]
5) add ax, [bx+si+20h]

43. 43
3. Memory Addressing Mode
⑴ Direct Addressing Mode
Exp: MOV AL, [1064H]
Machine code:A06410H
• The offset address of the operand is provided in the
instruction directly;
• The physical address can be calculated using the content
of DS and the offset :
PA = (DS)*10H+Offset

44. ⑴ Direct Addressing Mode
Example: MOV AL, [1064h] ;Assume (DS)=2000H
Machine code: A06410H
44
（DS)*10H=20000H
+ 1064H
21064H
20000H
21064H
AL
A0
64
10
…
45
Code
Segment
Data
Segment
45

45. 3. Memory Addressing Mode
⑵ Register Indirect Addressing Mode
• The address of memory location is in a register
(SI,DI,or BX only)
• The physical address is calculated using the content of DS
and the register(SI,DI,BX)
45
PA = (DS)*10H+(SI)/(DI)/(BX)

46. 46
⑵ Register Indirect Addressing Mode
ASSUME: (DS)=3000H, (SI)=2000H, (BX)=1000H
MOV AX, [SI] MOV [BX], AL
M
… …
50
40
AX
30000H
(DS)*10H=30000H
+ (SI)= 2000H
32000H
32000H
40 50
… …
(DS)*10h= 30000H
+ (BX)= 1000H
64H
M
31000H
AL 30000H
31000H
64H

47. ⑶ Register Relative Addressing
47
EA=
(BX)
(BP)
(DI)
(SI)
+ Displacement
For physical address calculation:
DS is used for BX,DI,SI;
SS is used for BP
PA=(DS)*10H+(BX)/(DI)/(SI)+Disp
OR
PA=(SS)*10H+(BP)+Disp

48. ⑶ Register Relative Addressing
MOV CL, [BX+1064H] ;assume: (DS)=2000h, (bx)=1000h
48
;Machine Code: 8A8F6410
(DS)*10h= 20000H
(BX)= 1000H
+ 1064H
22064H
20000H
22064H
8F
64
10
…
45
Code
Segment
Data
Segment
8A
…
CL
45 21000H
PPAA==((ddss))**1100hh++((bbxx))++11006644hh

49. ⑷ Based Indexed Addressing
49
EA=
(BX)
(BP) +
(DI)
(SI)
• Base register(bx or bp) determines which segment(data or stack) the operand is
stored;
• if using BX, the operand is defaultly located in Data segment,then:
PA=(DS)*10H+(BX)+(DI)/(SI)
• if using BP, the operand is defaultly located in stack segment,then:
PA=(SS)*10H+(BP)+(DI)/(SI)

50. ⑷ Based Indexed Addressing
Example: MOV AH, [BP][SI];Assume(ss)=4000h,(bp)=2000h,(si)=1200h
PPAA==((ssss))**1100hh++((bbpp))++((ssii))
50
M
… …
AH 40000H
56H
(SS)*10H= 40000H
(BP)= 2000H
+
43200H
43200H
(SI)= 1200H
56H

51. ⑸ Based Indexed Relative Addressing
51
EA=
(BX)
(BP) +
(DI)
(SI) + Displacement
if using BX, the operand is defaultly located in Data segment,then:
PA=(DS)*10H+(BX)+(DI)/(SI)+disp
if using BP, the operand is defaultly located in stack segment,then:
PA=(SS)*10H+(BP)+(DI)/(SI)+disp

52. ⑸ Based Indexed Relative Addressing
MOV [BX+DI+1234H], AH
;assume (ds)=4000h,(bx)=0200h,(di)=0010h
;machine code:88A13412h
52
A1
34
12
…
Code
segment
Data
segment
88
…
(DI)= 0010H
AH 45
40000H
(DS)*10H=40000H
(BX)= 0200H
+
1234H
45
41444H
41444H

53. Summary on the 8086 memory addressing modes
1. Direct Addressing [disp] disp DS CS ES SS
2. Register [BX]/[SI] /[DI] Content of the R DS CS ES SS
Indirect Addressing
53
operand offset address Default Overridden
（effective address ） Segment Register Segment
Register
3. Register [SI/DI/BX/BP+disp] (SI)/(DI)/(BX)/(BP)+disp DS CS ES SS
Relative Addressing
4. Based Indexed [BX+SI/DI] (BX)+disp DS CS ES SS
Addressing [BP+SI/DI] (BP)+disp SS CS ES DS
5. Based Indexed [BX+SI/DI+disp] (BX)+(SI)/(DI)+disp DS CS ES SS
Relative Addressing [BP+SI/DI+disp] (BP)+(SI)/(DI)+disp SS CS ES DS

54. Examples:
Assume: (BX)=6000H, (BP)=4000H, (SI)=2000H,
(DS)=3000H, (ES)=3500H, (SS)=5000H
IInnssttrruuccttiioonn aaddddrreessssiinngg llooggiiccaall pphhyyssiiccaall
1. MOV AX, [0520H]
mmooddee aaddddrreessss aaddddrreessss
Register Indirect Addressing 3000:6000 36000H
3. MOV AX, [SI+1000H] 3000:3000 33000H
4. MOV AX, [BP+6060H]
54
Direct Addressing 3000:0520 30520H
2. MOV AX, [BX]
Register Relative Addressing
Register Relative Addressing
5. MOV AX, ES: [BX+SI+0050H]
5000:A060 5A060H
Based Indexed Relative 3500:8050 3D050H
Addressing

55. 55
•AAddddrreessssiinngg mmooddeess ffoorr CCoonnttrrooll TTrraannssffeerr
IInnssttrruuccttiioonnss
MMooddeess ffoorr CCoonnttrrooll
TTrraannssffeerr IInnssttrruuccttiioonnss
IInntteerr--sseeggmmeenntt
IInnttrraa--sseeggmmeenntt
IInntteerr--sseeggmmeenntt--DDiirreecctt
IInntteerr--sseeggmmeenntt--IInn DDiirreecctt
IInnttrraa--sseeggmmeenntt DDiirreecctt
IInnttrraa--sseeggmmeenntt IInnddiirreecctt

56. 56
IInntteerr--sseeggmmeenntt--DDiirreecctt AAddddrreessssiinngg MMooddee
CS 2000h
TThhee aaddddrreessss ttoo wwhhiicchh ccoonnttrrooll iiss ttoo bbee ttrraannssffeerrrreedd lliieess iinn tthhee ddiiffffeerreenntt
sseeggmmeenntt aanndd aappppeeaarrss ddiirreeccttllyy IInn tthhee iinnssttrruuccttiioonn aass aann iimmmmeeddiiaattee
ddiissppllaacceemmeenntt vvaalluuee ww..rr..tt IIPP IIff tthhee ddiissppllaacceemmeenntt iiss
88--bbiittss((--112288<<dd<<++11227))((sshhoorrtt)) IIff tthhee ddiissppllaacceemmeenntt iiss
1166--bbiittss((--332276688<<dd<<++33227667))((LLoonngg))
EExx:: CCAALLLL 00002200::00001100HH
segment1
AAssssuummee CCSS==22000000hh,,IIPP==00000000hh
AAfftteerr JJMMPP,,CCSS== 00002200hh,,IIPP==00001100hh
CS
segment2
IP
00
20
00
10
…
…
Sub-routine
0020
Op-code for CALL
0010

57. 57
Inter-sseeggmmeenntt--IINN--DDiirreecctt AAddddrreessssiinngg MMooddee
TThhee aaddddrreessss ttoo wwhhiicchh ccoonnttrrooll iiss ttoo bbee ttrraannssffeerrrreedd
lliieess iinn tthhee ddiiffffeerreenntt sseeggmmeenntt aanndd iitt iiss ppaasssseedd ttoo
tthhee
iinnssttrruuccttiioonn iinnddiirreeccttllyy ii..ee ccoonntteennttss ooff aa mmeemmoorryy
bblloocckk
ccoonnttaaiinniinngg ffoouurr bbyytteess
IIPP((LLSSBB)),,IIPP((MMSSBB)),,CCSS((LLSSBB)),,CCSS((MMSSBB))
EExx:: CCAALLLL [[BBXX]]
IP(LSB)10
IP(MSB)00
CS(LSB)20
…
Sub-routine
segment1
…
CS 3000h
BBeeffoorree JJMMPP,,AAssssuummee BBXX==110000hh,, CCSS==33000000hh,,IIPP==220000hh
CS 0020
Op-code for CALL
AAfftteerr JJMMPP,,CCSS== 00002200hh,,IIPP==00001100hh
segment2
IP 0010
CS(MSB)00
IP 0010

58. se Intra-seggmmeenntt--DDiirreecctt AAddddrreessssiinngg MMooddee
58
TThhee aaddddrreessss ttoo wwhhiicchh ccoonnttrrooll iiss ttoo bbee ttrraannssffeerrrreedd lliieess iinn tthhee ssaammee
sseeggmmeenntt aanndd aappppeeaarrss ddiirreeccttllyy IInn tthhee iinnssttrruuccttiioonn aass aann iimmmmeeddiiaattee
ddiissppllaacceemmeenntt vvaalluuee ww..rr..tt IIPP IIff tthhee ddiissppllaacceemmeenntt iiss
88--bbiittss((--112288<<dd<<++11227))((sshhoorrtt)) IIff tthhee ddiissppllaacceemmeenntt iiss
1166--bbiittss((--332276688<<dd<<++33227667))((LLoonngg))
EExx:: CCAALLLL 550000hh
Code
Segment
AAssssuummee CCSS==22000000hh,,IIPP==00000000hh
AAfftteerr CCAALLLL,,CCSS== 22000000hh,,IIPP==IIPP++550000hh
CS 2000h Op-code for CALL
IP
05
00
0500
Sub-routine
IP 0000

59. seg Intra-segmmeenntt--IInn--DDiirreecctt AAddddrreessssiinngg MMooddee
59
IInn tthhiiss mmooddee tthhee ddiissppllaacceemmeenntt ttoo wwhhiicchh ccoonnttrrooll iiss ttoo bbee ttrraannssffeerrrreedd,,
IIss iinn tthhee ssaammee sseeggmmeenntt iinn wwhhiicchh tthhee ccoonnttrrooll ttrraannssffeerr iinnssttrruuccttiioonn lliieess
BBuutt iitt iiss ppaasssseedd ttoo tthhee iinnssttrruuccttiioonn iinnddiirreeccttllyy
CS 2000h Op-code for CALL
IP
EExx:: CCAALLLL [[BBXX]]
Code
Segment
AAssssuummee CCSS==22000000hh,,IIPP==00000000hh ,, BBXX==880000hh
AAfftteerr CCAALLLL,,CCSS== 22000000hh,,IIPP==IIPP++880000hh
05
00
0800
Sub-routine
IP 0000

60. 60
EExxaammppllee::
TThhee CCoonntteennttss ooff ddiiffffeerreenntt rreeggiisstteerrss aarree ggiivveenn bbeellooww.. FFoorrmm eeffffeeccttiivvee aaddddrreesssseess ffoorr
ddiiffffeerreenntt aaddddrreessssiinngg mmooddeess
OOffffsseett((ddiissppllaacceemmeenntt))== 55000000HH
AAXX==11000000HH,,BBXX==22000000HH,,SSII==33000000HH,,DDII==44000000HH,,BBPP==55000000HH,,SSPP==66000000HH,,CCSS==00000000HH,,DDSS==11000000HH
SSSS==22000000HH,,IIPP==7000000HH
SShhiiffttiinngg aa nnuummbbeerr ffoouurr ttiimmeess iiss eeqquuiivvaalleenntt ttoo mmuullttiippllyyiinngg iitt bbyy 1166DD oorr 1100HH

61. 61
Instruction Set
&
Assembler Directives

62. 62
Programming in 8088/8086
Three levels of languages available to program a microprocessor:
Machine Languages, Assembly Languages, and High-level
Languages.
Machine Language
A sequence of binary codes for the instruction to be executed by
microcomputers.
Long binary bits can be simplified by using Hexadecimal format
It is difficult to program and error prone.
Different uP (micro-processor) uses different machine codes.

63. Programming in 8088/8086 (cont.)
Assembly Language
To simplify the programming, assembly language (instead of machine language) is
used.
Assembly language uses 2- to 4-letter mnemonics to represent each instruction
type. E.g. “Subtraction” is represented by SUB
Four fields in assembly language statement:
Label, OP Code, Operand and Comment fields.
Programs will be ‘translated’ into machine language, by Assembler, so it can be
loaded into memory for execution.
High-Level Language
High level languages, like C, Basic or Pascal, can also be used to program
microcomputers.
An interpreter or a compiler is used to ‘translate’ high level language statement to
machine code. High level language is easier to read by human and is more suitable
when the programs involves complex data structures.
63

64. 64
Assemblers
Programming the instructions directly in machine code is possible but
every machine codes depending on how the data is stored.
The process of converting the microprocessor instructions to the
binary machine code can be performed automatically by a computer
program, called an ASSEMBLER. Popular assemblers include IBM
macro Assembler, Microsoft Macro Assembler (MASM) and Borland
Turbo Assembler(installed on IE NT Network).
Most assemblers accept an input text file containing lines with a
rigorously defined syntax split into four fields.
Not all fields need to be present in a line. Eg. A line can be just a
comment line if it starts with semicolon;

65. 65
Source Codes, Object Codes and Linking
Source code is the text written by the programmer
in assembly language
(or any other programming language)
 Object code is the binary code obtained after
running the assembler (
Or compiler if the source is in a high level language).
 Modules of a program may be written separately
and linked together to
form a executable program using a linker.
 The linker joins the object code of the different
modules into one large
object file which is executable. Most assemblers on
IBM PCs produce
object files which must be linked ( even if there are
no separate modules).

66. Source Codes, Object Codes and Linking(Contd.,)
66

67. 67
Fields in Assembler
<label> <Mnemonic or directive> <operands> <;comment>
Comment field contains internal program documentation to improve
human readability -use meaningful comments
Operand field contains data or address used by the instruction.
The following conventions typically apply:

68. 68
Fields in Assembler (Contd.,)
<label> <Mnemonic or directive> <operands> <;comment>
Mnemonic/directive field contains the abbreviation for the processor
instruction (eg. MOV) or an assembler DIRECTIVE. Adirective produces no
object code but is used to control how the assembler operates.
Examples of directives include:
END -indicate the end of a program listing,
FRED LABEL NEAR - define “FRED” as a near label
TOM EQU 1000H -define “TOM” as the number 1000H
Label field contains a label which is assigned a value equal to the address
where the label appears.

69. 69
Why Program in Assembler?
Assembler language instruction has a one-to-one correspondence with the
binary machine code: the programmer controls precisely all the operations
performed by the processor (a high level language relies on a compiler or
interpreter to generate the instructions).
 Assembler can generate faster and more compact programs
 Assembler language allows direct access and full control of input/output
operations
 However, high-level language programs are easier to write and develop than
assembler language programs

70. 70
Advantages of High-level languages
Block structure code: programs are most readable when they are
broken into “logical blocks” that perform specific function.
Productivity: easier to program
Level of complexity: no need to know the hardware details
Simple mathematics formula statement
Portability: only need to change the compiler when it is ported to other machine
Abstract data types: different data types like floating-point value,
record and array, and high precision value.
Readability

71. 71
Intel 8086 Instruction Set Overview
Intel 8088 has ninety basic ( ie not counting addressing mode
variants) instructions
Instructions belong to one of the following groups: data
transfer, arithmetic, logic, string manipulation, control
transfer and processor control.

72. Converting Assembly Language Instructions to
Machine Code
• An instruction can be coded with 1 to 6 bytes
• Byte 1 contains three kinds of information
– Opcode field (6 bits) specifies the operation (add, subtract, move)
– Register Direction Bit (D bit) Tells the register operand in REG field in byte
2 is source or destination operand
1: destination 0: source
-Data Size Bit (W bit) Specifies whether the operation will be performed on 8-
bit or 16-bit data
72
0: 8 bits 1: 16 bits

73. • Byte 2 has three fields
– Mode field (MOD)
– Register field (REG) used to identify the register for the first operand
– Register/memory field (R/M field)
73

74. 2-bit MOD field and 3-bit R/M field together specify the second operand
74
Mode Field encoding
Register/memory (R/M) Field Encoding

75. Examples
MOV BL,AL (88C316)
Opcode for MOV = 100010
D = 0 (AL source operand)
W bit = 0 (8-bits)
Therefore byte 1 is 100010002=8816
• MOD = 11 (register mode)
• REG = 000 (code for AL)
• R/M = 011 (destination is BL)
Therefore Byte 2 is 110000112=C316
75

76. Examples:
MOV BL, AL = 10001000 11000011 = 88 C3h
ADD AX, [SI] = 00000011 00000100 = 03 04 h
ADD [BX] [DI] + 1234h, AX = 00000001 10000001 __ __ h =
76
01 81 34 12 h

77. 77
Intel 8086 Instruction Set Overview

78. (abbreviations below: d=destination, s=source)
General Data Movement Instructions
MOV d,s - moves byte or word; most commonly used instruction
PUSH s - stores a word (register or memory) onto the stack
POP d - removes a word from the stack
XCHG d,s - exchanges data, reg.-reg. Or memory to register
XLAT - translates a byte using a lookup table (has no operands)
IN d,s - moves data (byte or word) from I/O port to AX or AL
OUT d,s - moves data (byte or word) from AX or AL to I/O port
LEA d,s - loads effective address (not data at address) into register
LDS d,s - loads 4 bytes (starting at s) to pointer (d) and DS
LES d,s - loads 4 bytes (starting at s) to pointer (d) and ES
LAHF - loads the low-order bytes of the FLAGS register to AH
SAHF - stores AH into the low-order byte of FLAGS
PUSHF - copies the FLAGS register to the stack
POPF - copies a word from the stack to the FLAGS register
78
I. Data Movement Instructions (14)

79. Instructions for moving strings
String instructions are repeated when prefixed by the REP mnemonic (CX
contains the repetition count)
MOVS d,s - (MOVSB, MOVSW) memory to memory data transfer
LODS s - (LODSB and LODSW) copies data into AX or AH
STOS d - (STOSB, STOSW) stores data from AH or AX
79

80. 80
Data movement using MOV
MOV d, s
d=destination (register or effective memory address),
s=source (immediate data, register or memory address)
MOV can transfer data from:
any register to any register (except CS register)
memory to any register (except CS)
immediate operand to any register (except CS)
any register to a memory location
immediate operand to memory
MOV cannot perform memory to memory transfers (must use a register as an intermediate
storage).
MOV moves a word or byte depending on the operand bit-lengths; the source
and destination operands must have the same bit length.
MOV cannot be used to transfer data directly into the CS register.

81. The stack The stack
The stack is a block of memory reserved for temporary storage of data and
registers. Access is LAST-IN, FIRST OUT (LIFO)
The last memory location used in the stack is given by the effective
address calculated from the SP register and the SS register:
Example:
81

82. The stack
Data may be stored onto the stack using the PUSH instruction –this
automatically decrements SP by 2 (all stack operations involve words).
The POP instruction removes data from the stack (and increments SP by 2).
The stack may be up to 64K-bytes in length.
82

83. 83
PUSH and POP instructions
Examples:
PUSH AX ;stores AX onto the stack
POP AX ;removes a word from the stack and loads it into AX
PUSHF ;stores the FLAGS register onto the stack
POPF ; removes a word from the stack and loads it into FLAGS
PUSH may be used with any register to save a word (the register
contents) onto the stack. The usual order (e.g. as with MOV) of
storing the lower order byte in the lower memory location is used.
PUSH may also be used with immediate data, or data in memory.
 POP is the inverse of the PUSH instruction; it removes a word
from the top of the stack. Any memory location or 16-bit register
(except CS) may be used as the destination of a POP instruction.
PUSHF and POPF saves and loads the FLAGS register to/from the
stack,respectively.

84. 84
Exchange Instruction (XCHG)
XCHG exchanges the contents of two registers or a register and memory. Both
byte and word sized exchanges are possible.
Examples:
XCHG AX,BX; exchange the contents of AX and BX
XCHG CL,BL; exchange CL and BL contents
XCHG DX,FRED; exchanges content of DX and memory
DS:FRED
 Memory to Memory exchanges using XCHG are NOT allowed.

85. 85
Translate Instruction (XLAT)
Many applications need to quickly convert byte sized codes to other values
mapping one byte value to another (e.g. mapping keyboard binary codes to ASCII
code)
 XLAT can perform a byte translation using a look-up table containing up to 256
elements
XLAT assumes that the 256-byte table starts at the address given by DS:BX (i.e.
effective address formed by the DS and BX registers). AL is used as an index to
point to the required element in the table prior to the execution of XLAT. The result
of XLAT instruction is returned in the same register (AL).
AAddddrreessss DDaattaa TTaabbllee

86. 86
LEA &LDS
LEA loads the offset of a memory address into a 16-bit register. The offset address
may be specified by any of the addressing modes.
Examples (with BP=1000H):
LEA AX,[BP+40H];=>SS:[1000H+40H] =SS:[1040H];load 1040H into AX
LEA BX,FRED; load the offset of FRED (in data segment) to BX
LEA CX,ES:FRED; loads the offset of FRED (in extra segment) to CX
LDS -Load data and DS
LDS reads two words from the consecutive memory locations and loads them into the
specified register and the DS segment registers.
Examples (DS=1000H initially)
LDS BX,[2222H]; copies content of 12222H to BL, 12223H to BH, and 12224 and
12225 to DS register
LDS is useful for initializing the SI and DS registers before a string operation. E.g.
LDS SI, sting_pointer
The source for LDS can be displacement, index or pointer register (except SP).

87. 87
LES -Load data and ES
LES reads two words from memory and is very similar to LDS except that the second
word is stored in ES instead of DS.
LES is useful for initializing that DI and ES registers for strings operation.
Example (with DS=1000H):
LES DI, [2222H]; loads DI with contents stored at 12222H and 12223H and loads ES
with contents at 12224 and 12225H

88. 88
LAHF, SAHF
LAHF (load AH with the low-order byte of the FLAGS register) and SAHF
(Store AH into the low-order byte of the FLAG register)
very rarely used instructions -originally present to allow translation of 8085
programs to 8086.

89. 89
IN, OUT
Examples:
IN AX, 0C8h ;reads port address at C8h (8 bit address) and loads into AX
IN AL, DX ;reads the port address given by DX and loads into AL
OUT p8 ,AX ;sends the data in AX to port p8
OUT DL, AX ; sends the data in AX to port given by DL
IN reads data from the specified IO port (8-bit or 16-bit wide) to the accumulator (
AL or AX).
 The IO port can be an immediate address (8-bit only) or specified by a variable
or register (8 or 16-bit address). (Seems only DX can be used.)
OUT sends data from the accumulator register to the specified I/O port. Both byte and
word sized data may be sent using IN and OUT.

90. 90
II. Arithmetic IInnssttrruuccttiioonnss((2200))
IInntteell 88008888 hhaass 2200 iinnssttrruuccttiioonnss ffoorr ppeerrffoorrmmiinngg iinntteeggeerr aaddddiittiioonn,,
SSuubbttrraaccttiioonn ,, mmuullttiipplliiccaattiioonn,, ddiivviissiioonn,, aanndd ccoonnvveerrssiioonnss ffrroomm bbiinnaarryy ccooddeedd ddeecciimmaall ttoo bbiinnaarryy..

91. 91
Arithmetic IInnssttrruuccttiioonnss ((ccoonntt..))

92. 92
AAddddiittiioonn
BBiinnaarryy aaddddiittiioonn ooff ttwwoo bbyytteess oorr ttwwoo wwoorrddss aarree ppeerrffoorrmmeedd uussiinngg::
AADDDD dd,,ss
AADDDD aaddddss bbyytteess oorr wwoorrddss iinn dd aanndd ss aanndd ssttoorreess rreessuulltt iinn dd..
TThhee ooppeerraannddss dd aanndd ss ccaann uussee tthhee ssaammee aaddddrreessssiinngg mmooddeess aass iinn MMOOVV..
 AAddddiittiioonn ooff ddoouubbllee--wwoorrdd iiss aacchhiieevveedd bbyy uussiinngg tthhee ccaarrrryy bbiitt iinn tthhee FFLLAAGGSS rreeggiisstteerr.. TThhee
iinnssttrruuccttiioonn
AADDCC dd,,ss
aauuttoommaattiiccaallllyy iinncclluuddeess tthhee ccaarrrryy ffllaagg,, aanndd iiss uusseedd ttoo aadddd tthhee mmoorree ssiiggnniiffiiccaanntt wwoorrdd iinn aa
ddoouubbllee--wwoorrdd aaddddiittiioonn..
Addition
Example: addition of two double words stored at [x] and [y]
MOV AX, [x] ; Loads AX with the word stored at location [x]
MOV DX, [x+2] ; Loads the high order word
ADD AX, [y] ; Adds the low order word at [y]
ADC DX, [y+2] ; Add including the carry from the low order words

93. 93
AAddddiittiioonn ((ccoonntt..))
EExxaammppllee:: aaddddiittiioonn ooff ttwwoo ddoouubbllee wwoorrddss ssttoorreedd aatt [[xx]] aanndd [[yy]]
AAddddiittiioonn ooff bbiinnaarryy ccooddeedd ddeecciimmaall nnuummbbeerrss ((BBCCDD)) ccaann bbee ppeerrffoorrmmeedd bbyy uussiinngg AADDDD
oorr AADDCC ffoolllloowweedd bbyy tthhee DDAAAA iinnssttrruuccttiioonn ttoo ccoonnvveerrtt tthhee
nnuummbbeerr iinn rreeggiisstteerr AALL ttoo aa BBCCDD rreepprreesseennttaattiioonn.. ((sseeee eexxaammppllee))
AAddddiittiioonn ooff nnuummbbeerrss iinn tthheeiirr AASSCCIIII ffoorrmm iiss aacchhiieevveedd bbyy uussiinngg AAAAAA ((aasscciiii aaddjjuusstt
aafftteerr aaddddiittiioonn))..

94. 94
ASCII adjust for Addition (AAA)
ASCII codes for the numbers 0 to 9 are 30H to 39H respectively.
 The ascii adjust instructions convert the sum stored in AL to two-byte unpack BCD number
which are placed in AX.
 When 30H is added to each byte, the result is the ASCII codes of the digits representing the
decimal for the original number in AL.
Example: Register AL contains 31H (the ASCII code for 1), BL contains 39H (the ASCII code for 9).
ADD AL, BL ; produces the result 6AH which is kept in AL.
AAA ; converts 6AH in AL to 0100H in AX
Addition of 30H to each byte of AX produces the result 3130H (the ASCII code
for 10 which is the result of 1+9)

95. 95
Subtraction

96. 96
Multiplication

97. 97
Division

98. 98
SIGN EXTENDED INSTRUCTIONS

99. 99
Other Arithmetic Instructions

100. 100
III. Logic and bit MANIPULATION Instructions (12)

101. III. Logic and bit MANIPULATION Instructions (12) (Contd)
101

102. 102
Shift and Rotate

103. 103
Shift and Rotate(Contd)

104. List file of 8086 assembly language program to produce packed BCD from two ASCII
characters
104

105. 105
IV. Strings Instruction (6)

106. 107
IV. Instruction for moving strings(Contd)

107. 108
REP prefix

108. 109
LODS and STOS string instructions

109. 110
LODS and STOS string instructions(Contd)

110. 111
CMPS and SCAS string instructions

111. 112
V. Program Flow Instruction

112. 113
Program Flow Instruction

113. 114
Unconditional JUMP

114. 115
Unconditional JUMP (cont.)

115. List file of program Demonstrating “backward” JMP
116

116. List file of program demonstrating “forward” JMP
117

117. 118
Conditional Jumps

118. 119
8086 Conditional Jump Instructions

119. Ex.: Reading ASCII code when a strobe is present
120

120. Assembly language for Reading ASCII code when a strobe is present
121

121. 122
Loops

122. 123
Procedures and modular Programming

123. 124

124. 125

125. Procedures and modular Programming (Contd)
126

126. 127
Procedures

127. 128
Stack Diagram

128. 129
Using PUSH and POP instructions

129. 130
Interrupt Instructions

130. 131
Interrupt Instructions

131. 132

132. 133
Program Data and Storage
• Assembler directives for data storage
– DB - byte(s)
– DW - word(s)
– DD - doubleword(s)
– DQ - quadword(s)
– DT - tenbyte(s)

133. 134
Arrays
• Any consecutive storage locations of the
same size can be called an array
X DW 40CH,10B,-13,0
Y DB 'This is an array'
Z DD -109236, FFFFFFFFH, -1, 100B
• Components of X are at X, X+2, X+4, X+8
• Components of Y are at Y, Y+1, …, Y+15
• Components of Z are at Z, Z+4, Z+8, Z+12

134. 135
DUP
• Allows a sequence of storage locations to
be defined or reserved
• Only used as an operand of a define
directive
DB 40 DUP (?)
DW 10h DUP (0)
DB 3 dup ("ABC")
db 4 dup(3 dup (0,1), 2 dup('$'))

135. 136
Word Storage
• Word, doubleword, and quadword data are
stored in reverse byte order (in memory)
Directive Bytes in Storage
DW 256 00 01
DD 1234567H 67 45 23 01
DQ 10 0A 00 00 00 00 00 00 00
X DW 35DAh DA 35
Low byte of X is at X, high byte of X is at X+1

136. 137
EQU Directive
• name EQU expression
– expression can be string or numeric
– Use < and > to specify a string EQU
– these symbols cannot be redefined later in the
program
sample EQU 7Fh
aString EQU <1.234>
message EQU <This is a message>

137. 138

138. 139

139. 140

140. 141

141. 142

142. 143

143. 144

144. 145

145. 146

146. 147

147. 148

148. 149

149. 150

150. 151

151. 152

152. 153

153. 154
Macro definition:
name MACRO [parameters,...]
<instructions>
ENDM
MyMacro MACRO p1, p2, p3
MOV AX, p1
MOV BX, p2
MOV CX, p3
ENDM
ORG 100h
MyMacro 1, 2, 3
MyMacro 4, 5, DX
RET

154. The syntax for procedure declaration:
name PROC
155
; here goes the code
; of the procedure ...
RET
name ENDP

155. 156
ORG 100h
CALL m1
MOV AX, 2
RET ; return to Main Program.
m1 PROC
MOV BX, 5
RET ; return to caller.
m1 ENDP
END

156. 157
ORG 100h
MOV AL, 1
MOV BL, 2
CALL m2
CALL m2
CALL m2
CALL m2
RET ; return to operating system.
m2 PROC
MUL BL ; AX = AL * BL.
RET ; return to caller.
m2 ENDP
END

157. 158