This document provides a history of the MOSFET from its origins in the 1930s patents by Heil and Lilienfeld to its development through the 20th century. It describes key milestones like the invention of the BJT in 1947, the demonstration of the MOSFET in 1960, and the first integrated circuit in 1961. The document outlines technological advances that enabled Moore's Law like scaling of feature sizes from the 1970s to 2000s. It also discusses the physics challenges of scaling like short channel effects, leakage currents, and the transition to new transport models beyond drift-diffusion.
The document provides a historical perspective on microelectronics beginning with the invention of the solid state transistor in 1947. It discusses several important developments including the demonstration of oxidation in 1953, the invention of the integrated circuit in 1958, and scaling of integrated circuits throughout the late 20th century as feature sizes shrank dramatically according to Moore's Law. The document also summarizes several key unit processes used in VLSI fabrication such as oxidation, lithography, etching, doping, and thin film deposition.
Three-dimensional (3D) VLSI provides advantages over traditional two-dimensional (2D) VLSI by reducing chip size, power consumption, and signal delay through shorter, more direct interconnects between functional blocks stacked in three dimensions. While 3D VLSI faces challenges such as thermal management and difficulties in design and fabrication, its potential to continue increasing circuit density and transistor counts as predicted by Moore's Law makes it a promising long-term solution as 2D approaches its physical scaling limits.
The document summarizes the history of integrated circuit fabrication technology from the 1940s to 2000s. Some key events include:
- The invention of the transistor at Bell Labs in 1947 laid the foundation for integrated circuits.
- Jack Kilby at Texas Instruments built the first integrated circuit in 1958 combining resistors, capacitors and transistors on a silicon chip.
- In 1959, planar technology was developed allowing more complex circuits to be built on chips using insulating and conducting layers.
- The microprocessor was invented in 1971 combining processor and memory on a single chip, enabling the computer revolution. Feature sizes continued to shrink following Moore's Law, increasing transistor counts and capabilities of chips over the decades.
Integrated circuits (ICs) are microscopic arrays of electronic components integrated onto a single chip of semiconductor material. There are several types of ICs based on their structure and fabrication method. Thick and thin film ICs are formed on an insulating substrate using screen printing or vacuum deposition techniques and can contain resistors, capacitors, and inductors but not transistors or diodes. Monolithic ICs integrate all components onto a single silicon wafer using photolithography to diffusively dope regions of the wafer with impurities. Hybrid ICs combine monolithic and thick/thin film fabrication by first forming transistors on a silicon wafer, covering it with an insulating layer, and then adding passive film components and interconnecting them to the underlying
In this presentation of mine, a basic Design approach of VLSI has been explained. The ppt explains the market level of VLSI and also the fabrication process and also its various applications. An integration of various switches, gates, etc on Ic's has also been showcased in the same.
The document outlines the scope and topics covered in a course on advanced semiconductor devices. The course will consist of 12 lectures covering topics such as CMOS technology, advanced silicon devices, compound semiconductors, novel device platforms, and sensors and actuators. It will provide an introduction to semiconductor history and trends, as well as overview key fabrication techniques and characterization methods. The exam will be an oral exam where students can use their printed lecture notes.
The document provides a historical perspective on microelectronics beginning with the invention of the solid state transistor in 1947. It discusses several important developments including the demonstration of oxidation in 1953, the invention of the integrated circuit in 1958, and scaling of integrated circuits throughout the late 20th century as feature sizes shrank dramatically according to Moore's Law. The document also summarizes several key unit processes used in VLSI fabrication such as oxidation, lithography, etching, doping, and thin film deposition.
Three-dimensional (3D) VLSI provides advantages over traditional two-dimensional (2D) VLSI by reducing chip size, power consumption, and signal delay through shorter, more direct interconnects between functional blocks stacked in three dimensions. While 3D VLSI faces challenges such as thermal management and difficulties in design and fabrication, its potential to continue increasing circuit density and transistor counts as predicted by Moore's Law makes it a promising long-term solution as 2D approaches its physical scaling limits.
The document summarizes the history of integrated circuit fabrication technology from the 1940s to 2000s. Some key events include:
- The invention of the transistor at Bell Labs in 1947 laid the foundation for integrated circuits.
- Jack Kilby at Texas Instruments built the first integrated circuit in 1958 combining resistors, capacitors and transistors on a silicon chip.
- In 1959, planar technology was developed allowing more complex circuits to be built on chips using insulating and conducting layers.
- The microprocessor was invented in 1971 combining processor and memory on a single chip, enabling the computer revolution. Feature sizes continued to shrink following Moore's Law, increasing transistor counts and capabilities of chips over the decades.
Integrated circuits (ICs) are microscopic arrays of electronic components integrated onto a single chip of semiconductor material. There are several types of ICs based on their structure and fabrication method. Thick and thin film ICs are formed on an insulating substrate using screen printing or vacuum deposition techniques and can contain resistors, capacitors, and inductors but not transistors or diodes. Monolithic ICs integrate all components onto a single silicon wafer using photolithography to diffusively dope regions of the wafer with impurities. Hybrid ICs combine monolithic and thick/thin film fabrication by first forming transistors on a silicon wafer, covering it with an insulating layer, and then adding passive film components and interconnecting them to the underlying
In this presentation of mine, a basic Design approach of VLSI has been explained. The ppt explains the market level of VLSI and also the fabrication process and also its various applications. An integration of various switches, gates, etc on Ic's has also been showcased in the same.
The document outlines the scope and topics covered in a course on advanced semiconductor devices. The course will consist of 12 lectures covering topics such as CMOS technology, advanced silicon devices, compound semiconductors, novel device platforms, and sensors and actuators. It will provide an introduction to semiconductor history and trends, as well as overview key fabrication techniques and characterization methods. The exam will be an oral exam where students can use their printed lecture notes.
This document provides an introduction and background on Complementary Metal Oxide Semiconductor (CMOS) technology. It discusses key components of a CMOS circuit including NMOS, PMOS, photolithography, etching, chemical mechanical planarization, shallow trench isolation, contacts, vias, and interlayer dielectrics. The objectives of the project are to identify defects in a defective CMOS sample using electrical testing, scanning laser optical microscopy, passive voltage contrast under SEM, and focused ion beam with EDX to determine the root cause of the defect.
The document summarizes the history and evolution of semiconductor transistors from their inception to modern FinFET and GAA technologies. It traces transistors from early patents in the 1920s-1930s to the first working transistor in 1947. Key developments include the switch to silicon in the 1950s, the MOSFET in 1959, and planar processing techniques in the 1960s which led to MOSFET dominance by the 1970s. The document then discusses post-scaling innovations like strained silicon and high-k dielectrics in the 2000s. It introduces FinFETs which addressed short channel effects below 28nm with 3D tri-gate structures starting in 2007. Future technologies discussed include GAA which provides full gate control with nano-sheets to
Lecture 01 Introduction and applications of Electronics & SemiConductors.pdfAthar Baig
The document provides an overview of electronics and semiconductors. It discusses how electronics relies on semiconductors and the key semiconductor materials used - Germanium, Silicon, and Gallium Arsenide. Silicon is highlighted as the most widely used due to its abundance, low cost, and the decades of development into its processing technology. The document also reviews the history of electronics from vacuum tubes to transistors and integrated circuits, and how semiconductors replaced vacuum tubes as the fundamental building blocks of electronic devices.
This document provides information about the EC303 CMOS VLSI Design course at the National Institute of Technology Warangal. The course aims to teach students about MOSFET fabrication, CMOS inverter analysis and design, digital and analog circuit design using CMOS gates, and trends in CMOS technology. The syllabus covers topics such as MOSFET characteristics, inverters, digital circuits using techniques like pseudo NMOS and domino logic, analog circuits including amplifiers, and emerging technologies like FinFETs. Reading materials including textbooks on digital and analog CMOS IC design are also listed.
The Junctionless Transistor - George J. Ferko VGeorge Ferko
The document discusses the history and operation of the junctionless transistor. It begins by summarizing the limitations of conventional transistors as their size decreases and the need for an alternative. It then provides a brief history of transistor development, noting Julius Lilienfeld's early concept of a field-effect transistor in 1928. Recent work by a team at Tyndall National Institute demonstrated the first working junctionless nanowire transistor. The document concludes by explaining the theory and design of the junctionless transistor, which differs from conventional transistors by having uniform doping between the gate, channel and drain.
The document discusses integrated silicon photonics and its components. It covers the context of electronic-photonic integration and confinement techniques. It then describes passive devices like waveguides, couplers, and wavelength division multiplexing. Finally, it discusses active devices such as detectors, modulators, light sources and lasers, and integrating photonics. It provides information on the materials, geometries, losses and metrology of silicon photonic waveguides.
This document provides an introduction to semiconductor manufacturing and discusses its history and key challenges. It describes the development of early electronic devices like vacuum tubes and transistors. The first integrated circuits were developed in the late 1950s and combined multiple components on a single chip of germanium or silicon. Over time, components have been miniaturized according to Moore's Law, doubling in number every 18 months. This miniaturization and increasing component density is allowing for greater device functionality but also presents manufacturing challenges around smaller feature sizes.
The document discusses various aspects of integrated photonics including passive and active devices. It covers topics such as waveguides, couplers, wavelength division multiplexing using microrings, and materials used for photonic integration on the CMOS platform. Waveguide materials discussed include silicon, silicon nitride, and amorphous silicon. Coupling methods covered are tapers, grating couplers, and inverted tapers. Characterization techniques like the Fabry-Perot method for measuring waveguide losses are also summarized.
The document provides a history of semiconductor device evolution from the invention of the transistor in 1947 to modern VLSI technology. It discusses key developments like the integrated circuit in 1958, the MOSFET in 1960, and Moore's Law in 1965. The document also summarizes the basics of MOSFET structure and operation, comparing MOS to other technologies like BJT. It emphasizes that MOS technology is now the dominant choice for VLSI due to advantages in size, power dissipation, and manufacturing yield.
The document provides an overview of the evolution of electronics from vacuum tubes to modern semiconductors like transistors. It discusses the working of key electronic components like diodes, specifically PN junction diodes. The document covers the construction and V-I characteristics of diodes, and their usage in applications like rectification and voltage regulation using components like Zener diodes. Special diodes including LEDs and photodiodes are also introduced along with their working principles. The document thus provides a comprehensive introduction to electronics components and diodes.
The document provides information about transistors including their basics, history, comparison to vacuum tubes, and types. It discusses how transistors can amplify and switch electronic signals, and are composed of semiconductor material with at least three terminals. The history outlines how the transistor was invented in 1947 at Bell Labs as an improvement over vacuum tubes, with its smaller size and lower power consumption enabling many electronic devices. Transistors eventually replaced vacuum tubes in most applications. Transistors are also categorized in different ways such as by material, structure, polarity, power rating, and application.
This document summarizes research on integrating silicon photonics into bulk CMOS processes. Key points:
- Silicon photonic devices like modulators and detectors were fabricated in a standard 180nm CMOS process using polysilicon waveguides with losses over 60 dB/cm. Deep trench isolation was used to isolate photonic devices.
- Losses were reduced to under 10 dB/cm by optimizing the waveguide width, removing nitride cladding, and switching to selective epitaxial growth of 45% silicon-germanium for photodetectors.
- First photodetector made with 45% silicon-germanium showed a responsivity of 0.03 A/W at 1280nm and
- The document debunks several myths about memristors. It argues that the memristor is not a fundamental circuit element and that HP did not actually discover the memristor. HP's "memristor" device does not meet the strict mathematical definition.
- It also argues that memristive memory is unlikely to replace technologies like flash memory. Companies are supporting phase change memory rather than memristors for next-generation non-volatile memory.
- The document analyzes patent data and finds that companies like Samsung and Unity Semiconductor have more patents related to resistance memory technologies, while HP has none related to metal oxide memories.
The document provides an overview of semiconductor device fabrication processes. It discusses that silicon is the most common substrate used due to its insulating oxide properties and ease of growth. The Czochralski method is used to grow silicon crystals by pulling them slowly from molten silicon. Wafers are cut from ingots and polished in cleanrooms before fabrication begins using processes like lithography, etching, and doping. Photolithography is a key process that uses masks and light to selectively expose and develop photoresist on wafers. CMOS fabrication combines p-type and n-type MOSFETs and continues to shrink minimum feature sizes, currently at the 65nm level, bringing challenges of reliability, costs and process compatibility
This document outlines the topics to be covered in a course on basic electronics engineering. The course will cover the evolution of electronics from vacuum tubes to modern semiconductors. It will discuss materials used in electronics and introduce active and passive components. Key topics will include PN junction diodes, their construction and voltage-current characteristics, and their use as switches and rectifiers. Special purpose diodes like Zener diodes, LEDs, and photodiodes will also be examined along with their applications.
This document provides information about MOSFETs and CMOS technology. It contains 3 sections:
1. It defines MOSFET, describes its working principle involving an electric field attracting or repelling charge carriers, and shows its internal diagram with 3 terminals.
2. It then discusses the characteristic curves of MOSFETs including transfer and output curves.
3. The document also defines CMOS as a semiconductor technology used for integrated circuits, lists some common uses like digital/memory/analog circuits and SoCs, and provides two examples of implementing logic functions using CMOS transistors.
The document discusses photonic computing and silicon photonics. It describes three categories of photonic computing: photonic transistors, optical/quantum computing, and silicon photonics. Silicon photonics aims to integrate all optical transmission and reception functions directly onto silicon chips using standard CMOS fabrication techniques. This allows for the manufacturing of high-speed, low-cost photonic devices. The document examines the key components of silicon photonic devices, including lasers, modulators, and photodetectors. It explains how integrating these components enables data transmission speeds of 50 Gbps. Silicon photonics has applications in high-speed networking and computing. Major companies involved in developing these technologies include Intel, NEC, Samsung, and HP.
This document discusses photonic computing and silicon photonics. It describes three categories of photonic computing: photonic transistors, optical/quantum computing, and silicon photonics. Silicon photonics aims to integrate all optical transmission and reception components directly onto silicon chips using standard CMOS fabrication techniques. This allows the production of low-cost optical devices. The document then examines key silicon photonics components in detail, including lasers, modulators, and photodetectors. It explains how integrating these components can create an optical link capable of transmitting data at 50 Gbps. Major companies developing silicon photonics are also mentioned.
This document provides an overview of metallization for integrated circuits. It discusses the requirements and purposes of metallization, including interconnecting thousands of devices on chips. Two common metallization methods described are vacuum evaporation and sputter deposition. Vacuum evaporation locally heats a material source to vaporize and deposit the metal film, while sputter deposition uses ion momentum from a plasma to eject atoms from a target onto the substrate. The document outlines the apparatus and processes for each technique.
First op amps built in 1930’s-1940’s
Technically feedback amplifiers due to only having one useable input
Used in WW-II to help how to strike military targets
Buffers, summers, differentiators, inverters
Took ±300V to ± 100V to power
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
This document provides an introduction and background on Complementary Metal Oxide Semiconductor (CMOS) technology. It discusses key components of a CMOS circuit including NMOS, PMOS, photolithography, etching, chemical mechanical planarization, shallow trench isolation, contacts, vias, and interlayer dielectrics. The objectives of the project are to identify defects in a defective CMOS sample using electrical testing, scanning laser optical microscopy, passive voltage contrast under SEM, and focused ion beam with EDX to determine the root cause of the defect.
The document summarizes the history and evolution of semiconductor transistors from their inception to modern FinFET and GAA technologies. It traces transistors from early patents in the 1920s-1930s to the first working transistor in 1947. Key developments include the switch to silicon in the 1950s, the MOSFET in 1959, and planar processing techniques in the 1960s which led to MOSFET dominance by the 1970s. The document then discusses post-scaling innovations like strained silicon and high-k dielectrics in the 2000s. It introduces FinFETs which addressed short channel effects below 28nm with 3D tri-gate structures starting in 2007. Future technologies discussed include GAA which provides full gate control with nano-sheets to
Lecture 01 Introduction and applications of Electronics & SemiConductors.pdfAthar Baig
The document provides an overview of electronics and semiconductors. It discusses how electronics relies on semiconductors and the key semiconductor materials used - Germanium, Silicon, and Gallium Arsenide. Silicon is highlighted as the most widely used due to its abundance, low cost, and the decades of development into its processing technology. The document also reviews the history of electronics from vacuum tubes to transistors and integrated circuits, and how semiconductors replaced vacuum tubes as the fundamental building blocks of electronic devices.
This document provides information about the EC303 CMOS VLSI Design course at the National Institute of Technology Warangal. The course aims to teach students about MOSFET fabrication, CMOS inverter analysis and design, digital and analog circuit design using CMOS gates, and trends in CMOS technology. The syllabus covers topics such as MOSFET characteristics, inverters, digital circuits using techniques like pseudo NMOS and domino logic, analog circuits including amplifiers, and emerging technologies like FinFETs. Reading materials including textbooks on digital and analog CMOS IC design are also listed.
The Junctionless Transistor - George J. Ferko VGeorge Ferko
The document discusses the history and operation of the junctionless transistor. It begins by summarizing the limitations of conventional transistors as their size decreases and the need for an alternative. It then provides a brief history of transistor development, noting Julius Lilienfeld's early concept of a field-effect transistor in 1928. Recent work by a team at Tyndall National Institute demonstrated the first working junctionless nanowire transistor. The document concludes by explaining the theory and design of the junctionless transistor, which differs from conventional transistors by having uniform doping between the gate, channel and drain.
The document discusses integrated silicon photonics and its components. It covers the context of electronic-photonic integration and confinement techniques. It then describes passive devices like waveguides, couplers, and wavelength division multiplexing. Finally, it discusses active devices such as detectors, modulators, light sources and lasers, and integrating photonics. It provides information on the materials, geometries, losses and metrology of silicon photonic waveguides.
This document provides an introduction to semiconductor manufacturing and discusses its history and key challenges. It describes the development of early electronic devices like vacuum tubes and transistors. The first integrated circuits were developed in the late 1950s and combined multiple components on a single chip of germanium or silicon. Over time, components have been miniaturized according to Moore's Law, doubling in number every 18 months. This miniaturization and increasing component density is allowing for greater device functionality but also presents manufacturing challenges around smaller feature sizes.
The document discusses various aspects of integrated photonics including passive and active devices. It covers topics such as waveguides, couplers, wavelength division multiplexing using microrings, and materials used for photonic integration on the CMOS platform. Waveguide materials discussed include silicon, silicon nitride, and amorphous silicon. Coupling methods covered are tapers, grating couplers, and inverted tapers. Characterization techniques like the Fabry-Perot method for measuring waveguide losses are also summarized.
The document provides a history of semiconductor device evolution from the invention of the transistor in 1947 to modern VLSI technology. It discusses key developments like the integrated circuit in 1958, the MOSFET in 1960, and Moore's Law in 1965. The document also summarizes the basics of MOSFET structure and operation, comparing MOS to other technologies like BJT. It emphasizes that MOS technology is now the dominant choice for VLSI due to advantages in size, power dissipation, and manufacturing yield.
The document provides an overview of the evolution of electronics from vacuum tubes to modern semiconductors like transistors. It discusses the working of key electronic components like diodes, specifically PN junction diodes. The document covers the construction and V-I characteristics of diodes, and their usage in applications like rectification and voltage regulation using components like Zener diodes. Special diodes including LEDs and photodiodes are also introduced along with their working principles. The document thus provides a comprehensive introduction to electronics components and diodes.
The document provides information about transistors including their basics, history, comparison to vacuum tubes, and types. It discusses how transistors can amplify and switch electronic signals, and are composed of semiconductor material with at least three terminals. The history outlines how the transistor was invented in 1947 at Bell Labs as an improvement over vacuum tubes, with its smaller size and lower power consumption enabling many electronic devices. Transistors eventually replaced vacuum tubes in most applications. Transistors are also categorized in different ways such as by material, structure, polarity, power rating, and application.
This document summarizes research on integrating silicon photonics into bulk CMOS processes. Key points:
- Silicon photonic devices like modulators and detectors were fabricated in a standard 180nm CMOS process using polysilicon waveguides with losses over 60 dB/cm. Deep trench isolation was used to isolate photonic devices.
- Losses were reduced to under 10 dB/cm by optimizing the waveguide width, removing nitride cladding, and switching to selective epitaxial growth of 45% silicon-germanium for photodetectors.
- First photodetector made with 45% silicon-germanium showed a responsivity of 0.03 A/W at 1280nm and
- The document debunks several myths about memristors. It argues that the memristor is not a fundamental circuit element and that HP did not actually discover the memristor. HP's "memristor" device does not meet the strict mathematical definition.
- It also argues that memristive memory is unlikely to replace technologies like flash memory. Companies are supporting phase change memory rather than memristors for next-generation non-volatile memory.
- The document analyzes patent data and finds that companies like Samsung and Unity Semiconductor have more patents related to resistance memory technologies, while HP has none related to metal oxide memories.
The document provides an overview of semiconductor device fabrication processes. It discusses that silicon is the most common substrate used due to its insulating oxide properties and ease of growth. The Czochralski method is used to grow silicon crystals by pulling them slowly from molten silicon. Wafers are cut from ingots and polished in cleanrooms before fabrication begins using processes like lithography, etching, and doping. Photolithography is a key process that uses masks and light to selectively expose and develop photoresist on wafers. CMOS fabrication combines p-type and n-type MOSFETs and continues to shrink minimum feature sizes, currently at the 65nm level, bringing challenges of reliability, costs and process compatibility
This document outlines the topics to be covered in a course on basic electronics engineering. The course will cover the evolution of electronics from vacuum tubes to modern semiconductors. It will discuss materials used in electronics and introduce active and passive components. Key topics will include PN junction diodes, their construction and voltage-current characteristics, and their use as switches and rectifiers. Special purpose diodes like Zener diodes, LEDs, and photodiodes will also be examined along with their applications.
This document provides information about MOSFETs and CMOS technology. It contains 3 sections:
1. It defines MOSFET, describes its working principle involving an electric field attracting or repelling charge carriers, and shows its internal diagram with 3 terminals.
2. It then discusses the characteristic curves of MOSFETs including transfer and output curves.
3. The document also defines CMOS as a semiconductor technology used for integrated circuits, lists some common uses like digital/memory/analog circuits and SoCs, and provides two examples of implementing logic functions using CMOS transistors.
The document discusses photonic computing and silicon photonics. It describes three categories of photonic computing: photonic transistors, optical/quantum computing, and silicon photonics. Silicon photonics aims to integrate all optical transmission and reception functions directly onto silicon chips using standard CMOS fabrication techniques. This allows for the manufacturing of high-speed, low-cost photonic devices. The document examines the key components of silicon photonic devices, including lasers, modulators, and photodetectors. It explains how integrating these components enables data transmission speeds of 50 Gbps. Silicon photonics has applications in high-speed networking and computing. Major companies involved in developing these technologies include Intel, NEC, Samsung, and HP.
This document discusses photonic computing and silicon photonics. It describes three categories of photonic computing: photonic transistors, optical/quantum computing, and silicon photonics. Silicon photonics aims to integrate all optical transmission and reception components directly onto silicon chips using standard CMOS fabrication techniques. This allows the production of low-cost optical devices. The document then examines key silicon photonics components in detail, including lasers, modulators, and photodetectors. It explains how integrating these components can create an optical link capable of transmitting data at 50 Gbps. Major companies developing silicon photonics are also mentioned.
This document provides an overview of metallization for integrated circuits. It discusses the requirements and purposes of metallization, including interconnecting thousands of devices on chips. Two common metallization methods described are vacuum evaporation and sputter deposition. Vacuum evaporation locally heats a material source to vaporize and deposit the metal film, while sputter deposition uses ion momentum from a plasma to eject atoms from a target onto the substrate. The document outlines the apparatus and processes for each technique.
First op amps built in 1930’s-1940’s
Technically feedback amplifiers due to only having one useable input
Used in WW-II to help how to strike military targets
Buffers, summers, differentiators, inverters
Took ±300V to ± 100V to power
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
1. Department of Electrical and Computer Engineering
(i.e., A brief history of sand)
M. Fischetti
October 2, 2009
A (partial, biased?) history of the MOSFET
from a physicist’s perspective
2. 2Department of Electrical and Computer Engineering MVF October 2, 2009
This talk: Void where prohibited, limitations and restrictions apply
Technology (i.e., how do we make them?) vs. electronic operation (i.e., how do they work
and how do we make them better?)
Too much to cover
Talk about what I know
Major omissions (that is, a disclaimer*):
• Doping: Diffusion (theory and technology), ion implantation, high-doping effects
• Lithography, possibly a “technology enabler”: Optical, contact, phase-shift, X-ray…
• Metallization: Deposition/growth, DAMASCENE, electromigration
• Etching: Wet vs. dry, RIE, plasma
• Film growth: Epitaxy, CVD, PE-CVD, MBE, ALD,…
• Contacts: Silicides, salicides, FUSI,…
• Layout issues: Isolation (deep/shallow trenches), cross-talk, latch-up, design rules,
DRAM/SRAM design, power,…
• …
3. 3Department of Electrical and Computer Engineering MVF October 2, 2009
History of the MOSFET? What’s that?
Thanks to Jiseok Kim for having put me on the spot….
It’s OK… I wish him good luck in getting his PhD wherever ELSE he may wish to get it….
I’m not sure what he meant by “history”… So, let’s start from the beginning….
4. 4Department of Electrical and Computer Engineering MVF October 2, 2009
The main character of our story: The MOSFET
No other human artifact has been fabricated in larger numbers (except perhaps nails?)
“…some consider it one of the most important technological breakthroughs in human
history…” (Wikipedia, the source of all human knowledge)
5. 5Department of Electrical and Computer Engineering MVF October 2, 2009
Timeline I
1925: Julius Edgar Lilienfeld’s MESFET patent
1935: Oskar Heil’s MOSFET patent
194?: Unpublished Bell Labs MESFET
1947: Ge BJT (Bardeen, Brattain, Shockley, Bell Labs)
1954: Si BJT (Teal, Bell Labs)
1960: MOSFET (Atalla&Khang, Bell Labs)
1961: Integrated circuit (Kilby, TI)
1963: CMOS (Sah&Wanlass, Fairchild)
1964: Commercial CMOS IC (RCA)
1965: DRAM (Fairchild)
1968: Poly-Si gate (Faggin&Klein, Fairchild)
1968: 1-FET DRAM cell (Dennard, IBM)
1971: UV EPROM (Frohman, Intel)
1971: Full CPU in chip, Intel 8008 (Faggin, Intel)
1974: Digital watch
1974: Scaling theory (Gänsslen&Dennard, IBM)
1978: Use of ion implanter
1978: Flotox EEPROM (Perlegos, Intel)
1980: Ion-implanted CMOS IC
1980: Plasma etching
1984: Scaling theory <0.25 μm (Baccarani, U. Bologna)
1986: 0.1 μm Si MOSFET (Sai-Halasz, IBM)
1991: CMOS replaces BJT also at high-end
1993: DGFET scalable to 30 nm (theory, Frank et al.)
2007: Non-SiO2 (HfO2–based) MOSFET (Intel)
1955: Si, Ge conduction band (Herring&Vogt)
Deformation-potential, high-field (Bardeen&Shockley)
1957: BTE in semiconductors – impurities (Luttinger&Kohn),
phonons (Price, Argyles)
1964: Band structure calculations (Hermann)
Monte Carlo for semiconductors (Kurosawa)
1965: Linear-parabolic oxidation model (Deal&Grove)
1966: Observations of 2DEG (Fowler, Fang, Stiles, Stern,..)
1967: Conductance technique (Nicollian&Goetzberger)
1974: DDE device simulator (Cottrell&Buturla)
1975: Quantum Hall Effect predicted (Ando)
1979: Quantum Hall Effect observed (von Klitzing)
1981: Identification of native Nit: Pb-centers (Poindexter)
Full-band MC (Shichijo&Hess)
1982: Fractional QHE observed (Störmer&Tsui, Laughlin)
1988: Full-band MC device simulator (MVF&Laux)
1992: NEGF device simulator (Lake, Klimeck, et al.)
Technology Physics/Simulations
6. 6Department of Electrical and Computer Engineering MVF October 2, 2009
Timeline II
1975: 20 μm (tOX≈250 nm)
1980: 10 μm (tOX≈150 nm)
1985: 5 μm (tOX≈70 nm)
1990: 1 μm (tOX≈15 nm)
1995: 0.35 μm (tOX≈8 nm)
2000: 0.18 μm (tOX≈3 nm)
2005: 65 nm (tOX≈1.4 nm)
2010: 32 nm (tOX≈1.2 nm?)
SiO2 growth and instability: Ions, traps, interface
SiO2 instability during operation: electron trapping, NBTI
Hot electron effects: oxide trapping, VT shift, breakdown
Scaling: Short-channel effects (SCE), oxide, dopants
….life is good…
Scaling: SCE, insulator
Leakage: Insulator
Power: Alternative devices
Feature size Main Problems
↑
↓
7. 7Department of Electrical and Computer Engineering MVF October 2, 2009
Timeline III
1975: 20 μm
1980: 10 μm
1985: 5 μm
1990: 1 μm
1995: 0.5 μm
2000: 0.25 μm
2005: 63 nm
2010: 32 nm
2015: 16 nm ?
Feature size Transport Physics
Drift-Diffusion
Hydrodynamic/
Energy transport
Boltzmann
Quantum?
↓
↕
↓
8. 8Department of Electrical and Computer Engineering MVF October 2, 2009
Transistor prehistory
1935 Heil’s patent 1947 First BJT 1960 Atalla’s MOSFET
Bardeen, Shockley, Brattain (Bell Labs)
9. 9Department of Electrical and Computer Engineering MVF October 2, 2009
IC Prehistory
1961 Kilby’s first IC 1962 Fairchild IC 1964 First MOS IC
(RCA)
10. 10Department of Electrical and Computer Engineering MVF October 2, 2009
Moore’s law prehistory
Gordon Moore 1965: Cost vs time Moore’s law 1960-1975
11. 11Department of Electrical and Computer Engineering MVF October 2, 2009
Moore’s law
Number of transistors/die & feature size vs time
12. 12Department of Electrical and Computer Engineering MVF October 2, 2009
Microprocessor prehistory
1965: Federico Faggin 1968: Fairchild 8-bit μP 1971: Intel 8080 μP
13. 13Department of Electrical and Computer Engineering MVF October 2, 2009
Memory prehistory: DRAM and EPROM
Bob Dennard (1-FET DRAM cell, 1968; 1971 Frohman’s UV-erasable EPROM
scaling theory with Fritz Gänsslen,1974) (written by avalanche injection)
14. 14Department of Electrical and Computer Engineering MVF October 2, 2009
More historical trends
J. Armstrong (ca.1989)
15. 15Department of Electrical and Computer Engineering MVF October 2, 2009
Timeline II once more
1975: 20 μm (tOX≈250 nm)
1980: 10 μm (tOX≈150 nm)
1985: 5 μm (tOX≈70 nm)
1990: 1 μm (tOX≈15 nm)
1995: 0.35 μm (tOX≈8 nm)
2000: 0.18 μm (tOX≈3 nm)
2005: 65 nm (tOX≈1.4 nm)
2010: 32 nm (tOX≈1.2 nm?)
SiO2 growth and instability: Ions, traps, interface
SiO2 instability during operation: electron trapping, NBTI
Hot electron effects: oxide trapping, VT shift, breakdown
Scaling: Short-channel effects (SCE), oxide, dopants
….life is good…
Scaling: SCE, insulator
Leakage: Insulator
Power: Alternative devices
Feature size Main Problems
↑
↓
16. 16Department of Electrical and Computer Engineering MVF October 2, 2009
SiO2 growth and instability
Ionic contamination (K, Na): Unrecognized source of early problems
Fixed traps (oxygen vacancies?), especially near Si-SiO2 interface
Growth kinetics: Deal & Grove model: linear (reaction-limited) and parabolic (diffusion-limited)
regions; dry and wet oxidation rates
Interface-state passivation: Al (with H) Post Metallization Anneal (PMA, Peter Balk):
H2O → H+ + OH-
Si- + H+ → Si-H
Andrew Grove (left), Bruce Deal (center)
and Ed Snow (left)
Ed Snow’s cartoon, ca. 1966
about SiO2 instabilities
17. 17Department of Electrical and Computer Engineering MVF October 2, 2009
SiO2 growth and instability, as-grown and during operation
CV-plot instabilities (VFB or VT shifts):
Ions (mainly Na+ and K+, contamination in chambers, handling, gases, etc…)
Interface states generation (stretch-out, Lai, Feigl, Sandia group, Technion, Siemens,…)
Electron and hole traps (DiMaria, Young, Feigl):
• Neutral: H2O-related (mainly OH-) in wet oxides, radiation induced in processing,
σ ≈ 10-15 to 10-17 cm2
• Charged-attractive: Ionic contamination, σ ≈ 10-13 cm2 , field-dependent
• Charged-repulsive: Radiation-induced, σ ≈ 10-19 cm2
18. 18Department of Electrical and Computer Engineering MVF October 2, 2009
SiO2 instability during operation
Anomalous Positive Charge (APC):
Caused by electron injection (Avalanche, Fowler-Nordheim) and also hole injection
Related to Hydrogen: Boron deactivation in p-type substrates (Sah)
Related to hole back-injection from anode? Dependent on gate-metal workfunction -
Au vs. Al vs. Mg (MVF&Weinberg, Chenming Hu)
Occurring at Si-SiO2 interface even under negative bias: Neutral species such as
solitons, H2 diffusion…? (Weinberg).
Connected to wear-out and breakdown (DiMaria, Stathis)
Strongly correlated to interface traps (Pb-centers, Lenahan, Poindexter)
Oxygen deficiency (Revesz)? Broken Si-H bonds (Si-D experiment, Lyding&Hess)?
Negative Bias Temperature Instability (NBTI): No time to discuss, but big issue in high-κ
dielectrics
19. 19Department of Electrical and Computer Engineering MVF October 2, 2009
Understanding SiO2 degradation: Two approaches
MVF and DiMaria, INFOS 1989
20. 20Department of Electrical and Computer Engineering MVF October 2, 2009
SiO2 growth and instability: Injection techniques and damage generation
21. 21Department of Electrical and Computer Engineering MVF October 2, 2009
SiO2 growth and instability: Electronic transport in SiO2
Electrons:
Long-standing problems of high-field electron transport in polar insulators
(Karel Thornber’s 1970 PhD Thesis with Richard Feynman)
LO-phonon scattering run-away connected to dielectric breakdown
Experimental observations do not show predicted run-away at 2-3 MV/cm
Umklapp scattering with acoustic phonons keeps electron energy under
control (MVF, DiMaria, Theis, Kirtley, Brorson, 1985)
Holes: Small polaron (self-trapping) transport (Bob Hughes’ 1977 time-of-flight
experiments explained by David Emin’s 1975 theory).
MVF et al., PR B (1985)
22. 22Department of Electrical and Computer Engineering MVF October 2, 2009
Hot electron effects in constant-voltage-scaled MOSFETs
Two problems:
Understand origin/spectrum of hot carrier
Understand nature/process of damage generation
Practical problems:
Unnecessary and expensive burn-in
Wall Street “big glitch” in 1994
Theory:
Shockley’s “lucky-electron model” widespread in EE community in the ’80s
(publicized by Chenming Hu, UCB): Even the Gods can be wrong at times…
Full-band models (Sam Shichijo & Karl Hess, MVF&Laux, then others)
Basic physics of electron scattering, injection into SiO2, etc.
The mid-1990s “pseudo-full-band” frenzy (Bologna, UNC, Udine, Lille, TU-
Vienna, Aachen,..): Gain without pain… didn’t work…
23. 23Department of Electrical and Computer Engineering MVF October 2, 2009
Electron injection into SiO2
MVF, Laux, and Crabbé, JAP (1996)
24. 24Department of Electrical and Computer Engineering MVF October 2, 2009
Timeline III once more
1975: 20 μm
1980: 10 μm
1985: 5 μm
1990: 1 μm
1995: 0.5 μm
2000: 0.23 μm
2005: 63 nm
2010: 32 nm
2015: 16 nm ?
Feature size Transport Physics
Drift-Diffusion
Hydrodynamic/
Energy transport
Boltzmann
Quantum?
↓
↕
↓
25. 25Department of Electrical and Computer Engineering MVF October 2, 2009
Electron transport in Si at 3 eV: A big headache
Effective-mass approximation valid only for E ≈ a few kBT
Scattering rates at E ≥ {a few kBT} totally unknown
Moments of the BTE (DDE, Hydrodynamic) not sufficiently accurate
26. 26Department of Electrical and Computer Engineering MVF October 2, 2009
Electron transport in Si at 3 eV ca. 1992: A depressing picture…
The state-of-the art circa 1992
27. 27Department of Electrical and Computer Engineering MVF October 2, 2009
A good example of experiments-theory feedback
XPS (McFeely, Cartier, Eklund at the
Brookhaven IBM synchrotron line, 1993) Carrier separation (DiMaria, 1992)
Cartier et al. APL (1993)
28. 28Department of Electrical and Computer Engineering MVF October 2, 2009
Electron transport in Si at 3 eV ca. 1994: Much better…
The state-of-the art circa 1994
MVF et al., JAP (1996)
30. 30Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling
Electrostatic integrity (Well-tempered MOSFET, Antoniadis): SOI, DGFETs, FinFETs, NW-FETs
Reduce power, an example: The tunnel FET n (tFET)
Reduced leakage: High-κ gate-insulators
Improve (or, at least, maintain) performance: Alternative channel materials?
31. 31Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Electrostatic integrity: SOI
22 nm strained-Si nFET: SOI to prevent punch- through,
strained Si to improve performance (B. Doris, IBM, 2006)
32. 32Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Electrostatic integrity: Double gate FET
AIST (2003)
33. 33Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Electrostatic integrity: Multibridge FETs (TEM, SEM)
Samsung Electronics Ltd. (2005)
34. 34Department of Electrical and Computer Engineering MVF October 2, 2009
Multibridge FETs: Process flow
Samsung Electronics Ltd. (2005)
35. 35Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Electrostatic integrity: FinFETs
Freescale Semiconductors
36. 36Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Electrostatic integrity: Si Nanowire Transistors
KAIST (2007)
37. 37Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Reduce power: The tunnel-FET (tFET)
InAs Tunnel-FET: structure
(M. Haines, UMass 2009)
InAs Tunnel-FET: pair generation rate
(M. Haines, UMass 2009)
Stand-by power dissipation approaching “on”
power dissipation… Cannot continue like this!
60 mV/dec → ΔVG ≈ 250 mV for Ioff/Ion ≈ 10-4
VT + ΔVG ≥ 0.45 V at 300 K (nFETs)
Must increase slope (i.e., go below 60 mV/dec) if
we want the `Green’ FET (term coined by C. Hu)
Problem: Ion too low in all attempts (DARPA to
IBM, UCB, Stanford,…) so far
38. 38Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Reduce leakage
Off-leakage:
Accepted value increasing: Ioff/Ion ≈ 10-4 for the 32 nm node (used to be 10-6 or lower!)
Connected to electrostatic integrity (punch-through, junction leakage, gate leakage)
Gate leakage:
C = εox/tox, so if tox has reached its limit (≈ 1nm, too aggressive so far), scale εox:
High-κ insulators such as HfO2, ZrO2, Al2O3, etc.
Problem: Low mobility in high-κ MOS systems (scattering with interfacial optical phonons)
Metals with different workfunction needed!
Hi-res TEM from
Susanne Stemmer,
UCSB MVF et al., JAP (2001)
39. 39Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Reduce leakage: Gate oxide scaling at Intel
C. Hu et al., IEDM (1996)
40. 40Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Improve performance
Taken for granted early on (ca. 1986)
Slow realization that early optimism was unjustified
MVF and S. Laux, EDL (1987)
41. 41Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Improve performance
Look for high-velocity, low-effective mass semiconductors… or should we?
Problems:
High-energy (≈ 0.5 eV ≈ 20 kBT) DOS and rates identical in most fcc semiconductors
Low DOS → loss of transconductance
Low DOS → smaller density in quasi-ballistic conditions → lower Ion
Low DOS → less scattering in source → source starvation
42. 42Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Improve performance: DOS bottleneck
MVF and S. Laux, TED (1991)
43. 43Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Improve performance: Strained Si
MVF and S. Laux, JAP (1996)
44. 44Department of Electrical and Computer Engineering MVF October 2, 2009
Scaling – Improve performance: Strained Si
IBM 32 nm strained (tensile)
Si nFET on SiGe virtual substrate
Intel 45 nm strained (compressive)
Si pFET with regrown SiGe S/D
45. 45Department of Electrical and Computer Engineering MVF October 2, 2009
Why are sub-40 nm devices getting slower?
Power dissipation → reduce frequency or fry!
Parasitics play a bigger role (Antoniadis, MIT)
Higher oxide fields squeeze carriers against interface → increased scattering
(Antoniadis, MIT)
Intrinsic Coulomb effects!
MVF and S. Laux, JAP (2001)
46. 46Department of Electrical and Computer Engineering MVF October 2, 2009
Why are sub-40 nm devices getting slower? The effect of e-e interactions
47. 47Department of Electrical and Computer Engineering MVF October 2, 2009
Sub-32 nm Si CMOS devices: Where do we stand?
22 nm: Planar (Intel), SOIs (IBM), FinFETs doable but too expensive.
16 nm: Possibly FinFETs, still Si
Below 16 nm:
Ge pFETs and III-V nFETs (IMEC)? A pipedream…
Ge nFETs still lousy, improvements promised at Dec 2009 IEDM, we’ll see
III-Vs in the works:
• MIT (del Alamo): Great HEMTs, but huge S/D-gate gap not easily scalable
• SRC/UCSB MOSFETs: Wait and see…
48. 48Department of Electrical and Computer Engineering MVF October 2, 2009
The future and “post Si CMOS” devices: What do we need?
Three terminal devices (Josephson computers taught us something…!)
At least some gain (preserving signal over billions of devices, beating kBT)
At least a few devices must have high Ion to charge external loads
On/off behavior (Landauer’s water faucet analogy)
Low power, possibly non-charge-switching (spins, QCA,…). BUT: If we use ≈ kBT to
switch, the heat bath will switch for us even if we do not want to…
Notable historic failures:
Josephson: Excessively strict tolerances (on insulators), complicated 2-terminal logic
SETs: No output current (`a slight impedance matching issue’, as someone kindly put
it….)
Optical computers: Photons are huge! Clumsy 3-terminal devices
Resonant tunneling diodes and multi-state logic: Non off-off switches, impossible to
control manufacturing tolerances
High hopes:
Nanowires: They are just thin and narrow FinFETs
Long shots:
Spins and QCA: Low power but no gain
CNT: No current in single tube, must use many in parallel
III-Vs: Battle already lost in 1991 (DOS bottleneck),,, why bother again?
49. 49Department of Electrical and Computer Engineering MVF October 2, 2009
And by popular demand… The future of “post-Si CMOS” logic technology
50. 50Department of Electrical and Computer Engineering MVF October 2, 2009
More slides about the lunatic fringe….
51. 51Department of Electrical and Computer Engineering MVF October 2, 2009
The lunatic fringe: Exploratory devices
52. 52Department of Electrical and Computer Engineering MVF October 2, 2009
The lunatic fringe: Exploratory devices
53. 53Department of Electrical and Computer Engineering MVF October 2, 2009
The lunatic fringe: Exploratory devices
Carbon NanoTube (CNT) FET
IFF-Jülich, Germany (2004)
54. 54Department of Electrical and Computer Engineering MVF October 2, 2009
CNT Transistors
IFF-Jülich, Germany (2004)
55. 55Department of Electrical and Computer Engineering MVF October 2, 2009
CNT FET inverter
J. Appenzeller, IBM