module dma_controller_core ( input logic clk, input logic reset, input logic strt_transfer, input logic [7:0] source_addr_in, input logic [7:0] dest_addr_in, input logic [7:0] trans_size_in, output logic trans_complete, output logic trans_error, output logic interrupt, input logic bg, // Bus Grant from CPU output logic br, // Bus Request to CPU output logic rs, // Resource Select signal output logic ds, // Device Select signal output logic [7:0] status_reg, output logic mem_read, output logic mem_write, output logic [7:0] memory_addr, input logic [7:0] memory_data_in, output logic [7:0] memory_data_out, output logic periph_read, output logic periph_write, output logic [7:0] periph_addr, input logic [7:0] periph_data_in, output logic [7:0] periph_data_out ); typedef enum logic [2:0] { IDLE, SETUP, REQUEST_BUS, READ, WRITE, COMPLETE, ERROR } dma_state_t; dma_state_t state, next_state; logic bus_granted; // Internal copies of input ports logic [7:0] source_addr, dest_addr, transfer_size; // State update and signal initialization always_ff @(posedge clk or negedge reset) begin if (!reset) begin state <= IDLE; source_addr <= 0; dest_addr <= 0; transfer_size <= 0; trans_complete <= 0; trans_error <= 0; interrupt <= 0; br <= 0; rs <= 0; ds <= 0; bus_granted <= 0; end else begin state <= next_state; end if (bg) bus_granted <= 1; // Acknowledge bus grant within always_ff block end always_ff @(posedge clk) begin if (state == COMPLETE) begin trans_complete <= 1; end else begin trans_complete <= 0; end if (state == ERROR) begin trans_error <= 1; end else begin trans_error <= 0; end interrupt <= trans_complete | trans_error; if (state == SETUP) begin br <= 1; // Request bus access end else begin br <= 0; end if (state == REQUEST_BUS && bus_granted) begin rs <= 1; // Set Resource selection ds <= 1; // Set Device selection end else begin rs <= 0; ds <= 0; end end always_comb begin next_state = state; // Default next state is the current state case (state) IDLE: if (strt_transfer && transfer_size > 0) begin next_state = SETUP; end READ: if (memory_data_in) begin next_state = WRITE; end else begin next_state = ERROR; end WRITE:

1. module data_register #(
parameter int DATA_WIDTH = 8 // Parameter for data width allows flexibility
)(
input logic clk, // Clock input
input logic rst_n, // Active low asynchronous reset
input logic [DATA_WIDTH-1:0] data_in, // Input data
input logic data_in_valid, // Input valid signal
output logic reg_valid, // Output valid signal
output logic [DATA_WIDTH-1:0] reg_data // Output data
);
// Internal signals to hold the current state of the register and its validity
logic [DATA_WIDTH-1:0] internal_data;
logic internal_valid;
// Capture the incoming data on a valid signal and update the internal state
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// On reset, clear the internal register and valid flag
internal_data <= {DATA_WIDTH{1'b0}};
internal_valid <= 1'b0;
end else if (data_in_valid) begin
// Capture data when valid signal is asserted
internal_data <= data_in;
internal_valid <= 1'b1;
end
// No 'else' clause; we are holding the data and valid flag
// until the next valid data comes in or reset is asserted
end

2. // Assign internal states to outputs
assign reg_data = internal_data;
assign reg_valid = internal_valid;
endmodule