Introduction to logic gates

1. Logic Circuit and
Switching Theory
Introduction
Logic Gates
1

2. Review of Boolean algebra
• Complementation
known as NOT operation, denoted by an over bar
Ex. Complement of A = A
0 = 1
1 = 0
• Logical addition
known as OR operation, denoted by a plus sign
Ex. A + B
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
• Logical multiplication
known as AND operation, denoted by a dot sign
Ex. A • B
0 • 0 = 0
0 • 1 = 0
1 • 0 = 0
1 • 1 = 1 2

3. Basic Digital Logic
Digital signals have two (2) basic states
1 (Logic “high” H / “on” / TRUE / Positive)
0 (Logic “low” L / “off’ / FALSE / Negative)
Voltage are used to represent logic values
• A voltage present (called Vcc or Vdd) = 1
• Zero voltage or ground (called gnd or Vss) = 0
3

4. Logic Gates
• A digital computer is composed of nothing
more than digital circuit, buses, and sequential
logic elements.
• Digital circuit are composed of gates that are
wired together either fixed circuit or
reconfigurable.
• The basic elements of circuits are gates. Each
type of gate implements a Boolean operation
4

5. Logic gates are electronic digital circuit perform
logic functions. Commonly expected logic
functions are already having the corresponding
logic circuits in Integrated Circuit (I.C.) form.
In circuitry theory, NOT, AND, and OR gates are
the basic gates. Any circuit can be designed
using these gates. The circuits designed depend
only on the inputs, not on the output. In other
words, these circuits have no memory. Also
these circuits are called combinational circuits.
The symbols NOT gate, AND gate, and OR gate
are also considered as basic circuit symbols,
which are used to build general circuits. 5

6. OR Gate
Logic Symbol 
Truth table
A
B
Y
Y = A + B
INPUT OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
6

7. Input Output
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
A
B
Y
A
B
C
Y = A + B + C
An OR gate is logic gate with two or more input signals
and one output signal. If any input signal is high, the
output signal is high. Output is low if and only if all input
signals are low.
Y
7

8. AND Gate
Logic Symbol 
Truth table
A
B
INPUT OUTPUT
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
8

9. Input Output
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
A
B
C
An AND gate is logic gate with two or more input signals
and one output signal. If any input signal is low, the
output signal is low. Output is high if and only if all input
signals are high.
Y = A • B • C
or
Y = ABC
Y
9

10. NOT Gate / INVERTER
Logic Symbol 
Truth table
A Y
INPUT OUTPUT
A Y
0 1
1 0
Y = A
A NOT gate or also known as INVERTER is logic gate
with one input signal and one output signal. Output is just
the complement of the input.
10

11. NOR Gate
Logic Symbol 
Truth table
Y = A + B
INPUT OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
11

12. Input Output
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Y = A + B + C
A NOR gate is logic gate with two or more input signals
and one output signal. If any input signal is high, the
output is low. Output is high if and only if all input signals
are low.
A
B
C
12

13. NAND Gate
Logic Symbol 
Truth table
A
B
INPUT OUTPUT
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Y
Y = A • B or
Y = AB
13

14. Input Output
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
A
B
C
A NAND gate is logic gate with two or more input signals
and one output signal. If any input signal is low, the
output signal is high. Output is low if and only if all input
signals are high.
Y = A • B • C
or
Y = ABC
Y
14

15. Exclusive OR / XOR Gate
Logic Symbol 
Truth table
A
B
INPUT OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Y
Y = A • B+
15

16. Input Output
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
A
B
C
An Exclusive OR (XOR) gate is logic gate with two or
more input and one output signal. If input signals have an
odd parity, the output signal is high.
Odd parity – an odd number of 1’s in an input word
Y
Y = A B C+ +
16

17. Exclusive NOR / XNOR Gate
Logic Symbol 
Truth table
A
B
INPUT OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
Y
Y = A • B = A B+ •
17

18. Input Output
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
A
B
C
An Exclusive NOR (XNOR) gate is logic gate with two or
more input and one output signal. If input signals have an
even parity, the output signal is high.
Even parity – an even number of 1’s in an input word
Y
Y = A B C
or
Y = A B C
+ +
• •
18

19. C
A + B
F =
Input Output
A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A + B + C
19

20. C
A + B
F =
Input Output
A B C A + B F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
A + B + C
20

21. C
A + B
F =
Input Output
A B C A + B Y
0 0 0 1 0
0 0 1 1 0
0 1 0 0 1
0 1 1 0 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 1
1 1 1 0 0
A + B + C
21

22. C
A B
F =
Input Output
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
AB • C
B
A
22

23. C
A B
F =
Input Output
A B C A B Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
AB • C
B
A
23

24. C
A B
F =
Input Output
A B C A B F
0 0 0 1 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 1
1 1 1 0 1
AB • C
B
A
24

25. C
A + B
F =
Input Output
A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
(A + B) + C
A
B
Y
A
B
Y
A
B
25

26. C
A + B
F =
Input 1 Output
A B C A’ B’ A’ + B’ C’ F
0 0 0 1 1 1 1 1
0 0 1 1 1 1 0 1
0 1 0 1 0 1 1 1
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 0 1
1 1 0 0 0 0 1 1
1 1 1 0 0 0 0 0
A + B + C
A
B
Y
A
B
Y
A
B
26

27. C
A B
F =
Input Output
A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
(A B ) C
A
B
27

28. C
A B
F = (A B ) C
A
B
Input 1 Output
A B C A’ B’ A’ •B’ C’ Y
0 0 0 1 1 1 1 1
0 0 1 1 1 1 0 0
0 1 0 1 0 0 1 0
0 1 1 1 0 0 0 0
1 0 0 0 1 0 1 0
1 0 1 0 1 0 0 0
1 1 0 0 0 0 1 0
1 1 1 0 0 0 0 0
28

29. F =
Input Output
A B A’ B’ Y
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
A
B
Y
A
B
A + B
29

30. A NAND gate is equivalent to a BUBBLED OR
30

31. A B
Input Output
A B A’ B’ Y
0 0 1 1 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 0
31

32. A NOR gate is equivalent to a BUBBLED AND
32

33. DE MORGAN’s LAW
A NOR gate is equivalent to a BUBBLED AND
A NAND gate is equivalent to a BUBBLED OR
33

34. Summary
 An OR gate is logic gate with two or more input signals and one output
signal. If any input signal is high, the output signal is high. Output is low
if and only if all input signals are low.
 An AND gate is logic gate with two or more input signals and one output
signal. If any input signal is low, the output signal is low. Output is high if
and only if all input signals are high.
 A NOT gate or also known as INVERTER is logic gate with one input
signal and one output signal. Output is just the complement of the input.
 A NOR gate is logic gate with two or more input signals and one output
signal. If any input signal is high, the output is low. Output is high if and
only if all input signals are low.
 A NAND gate is logic gate with two or more input signals and one
output signal. If any input signal is low, the output signal is high. Output
is low if and only if all input signals are high.
34

35. Summary
Odd parity – an odd number of 1’s in an input word
An Exclusive OR (XOR) gate is logic gate with two or more input and
one output signal. If input signals have an odd parity, the output
signal is high.
Even parity – an even number of 1’s in an input word
An Exclusive NOR (XNOR) gate is logic gate with two or more input and
one output signal. If input signals have an even parity, the output signal
is high.
Under the DE MORGAN’s LAW
A NOR gate is equivalent to a bubbled AND
and A NAND gate is equivalent to a bubbled OR
35

36. BASIC LAW OF BOOLEAN ALGEBRA
X + 0 = X X + 1 = 1
X + X = X X + X’ = 1
X  0 = 0 X  1 = X
X  X = X X  X’ = 0
X’’ = X X’’’ = X’
X + Y = Y + X X  Y = Y  X
( X + Y ) + Z = X + ( Y + Z ) ( X  Y )  Z = X  ( Y  Z )
X ( Y + Z ) = XY + XZ (X + Y) (X + Z) = X + YZ
X + XY = X X ( X + Y ) = X
X ( X’ + Y ) = XY X + X’Y = X + Y
36

37. Gating network
1.
2.
F = XY + X’Y’
F
3.
X = ( A B ) + AC + (AB C) 37

38. Gating network
A
B
Y
F
F = XY’ + X’Y
38

39. INPUT 1 OUTPUT
X Y y’ XY’ F
0 0 1 0
0 1 0 0
1 0 1 1
1 1 0 0
F = XY’ + X’Y
39

40. INPUT 1 2 OUTPUT
X Y X’ y’ XY’ X’Y F
0 0 1 1 0 0
0 1 1 0 0 1
1 0 0 1 1 0
1 1 0 0 0 0
F = XY’ + X’Y
40

41. INPUT 1 2 OUTPUT
X Y X’ y’ XY’ X’Y F = 1+ 2
0 0 1 1 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 1
1 1 0 0 0 0 0
F = XY’ + X’Y
41

42. CONCLUSION
X’Y + XY’ = X Y
42

43. Gating network
Y
F = XY + X’Y’
F
43

44. INPUT 1 OUTPUT
X Y XY F
0 0 0
0 1 0
1 0 0
1 1 1
F = XY + X’Y’
44

45. INPUT 1 2 OUTPUT
X Y XY X’ Y’ X’Y’ F
0 0 0 1 1 1
0 1 0 1 0 0
1 0 0 0 1 0
1 1 1 0 0 0
F = XY + X’Y’
45

46. INPUT 1 2 OUTPUT
X Y XY X’ Y’ X’Y’ F = 1+ 2
0 0 0 1 1 1 1
0 1 0 1 0 0 0
1 0 0 0 1 0 0
1 1 1 0 0 0 1
F = XY + X’Y’
46

47. CONCLUSION
XY + X’Y’ = X Y
47

48. X = ( A B ) + AC + (AB C)
INPUT OUTPUT
A B C X
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Truth table
X =((A B ) + AC ) + (AB C)
48

49. X = ( A B ) + AC + (AB C)
INPUT 1 2 5 3 4 6 OUTPUT
A B C (A B) AC 1+2 AB C 3 4 X = 5 + 6
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0 49

50. X = ( A B ) + AC + (AB C)
INPUT 1 2 5 3 4 6 OUTPUT
A B C (A B) AC 1+2 AB C 3 4 X = 5 + 6
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1
1 1 0 0 0
1 1 1 0 1 50

51. X = ( A B ) + AC + (AB C)
INPUT 1 2 OUTPUT
A B C ( A B ) AC X
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1
1 1 0 0 0
1 1 1 0 1 51

52. X = ( A B ) + AC + (AB C)
INPUT 1 2 5 3 4 6 OUTPUT
A B C (A B) AC 1+2 AB C 3 4 X = 5 + 6
0 0 0 0 0 1
0 0 1 0 0 1
0 1 0 1 0 0
0 1 1 1 0 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 0 1 0 52

53. X = ( A B ) + AC + (AB C)
INPUT 1 2 5 3 4 6 OUTPUT
A B C (A B) AC 1+2 AB C 3 4 X = 5 + 6
0 0 0 0 0 1 1
0 0 1 0 0 1 1
0 1 0 1 0 0 1
0 1 1 1 0 0 1
1 0 0 1 0 0 1
1 0 1 1 1 0 1
1 1 0 0 0 1 0
1 1 1 0 1 0 0 53

54. X = ( A B ) + AC + (AB C)
INPUT 1 2 5 3 4 6 OUTPUT
A B C (A B) AC 1+2 AB C 3 4 X = 5 + 6
0 0 0 0 0 1 1 1 1
0 0 1 0 0 1 1 0 0
0 1 0 1 0 0 1 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 0 1 1 1
1 0 1 1 1 0 1 0 0
1 1 0 0 0 1 0 1 0
1 1 1 0 1 0 0 0 1 54

55. X = ( A B ) + AC + (AB C)
INPUT 1 2 5 3 4 6 OUTPUT
A B C (A B) AC 1+2 AB C 3 4 X = 5 + 6
0 0 0 0 0 1 1 1 1 1
0 0 1 0 0 1 1 0 0 1
0 1 0 1 0 0 1 1 1 1
0 1 1 1 0 0 1 0 0 0
1 0 0 1 0 0 1 1 1 1
1 0 1 1 1 0 1 0 0 0
1 1 0 0 0 1 0 1 0 1
1 1 1 0 1 0 0 0 1 1 55

56. F = ( xy z ) + (x ( y + z ))
INPUT OUTPUT
X Y Z F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
56

57. F = ( xy z ) + (x ( y + z ))
INPUT OUTPUT
X Y Z XY F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
57

58. F = ( xy z ) + (x ( y + z ))
INPUT OUTPUT
X Y Z
XY Z
F
0 0 0 1 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 1
1 1 1 0 0
58

59. F = ( xy z ) + (x ( y + z ))
INPUT 1 OUTPUT
X Y Z
XY Z (xy z ) F
0 0 0 1 1 0
0 0 1 1 0 1
0 1 0 1 1 0
0 1 1 1 0 1
1 0 0 1 1 0
1 0 1 1 0 1
1 1 0 0 1 1
1 1 1 0 0 0
59

60. F = ( xy z ) + (x ( y + z ))
INPUT 1 OUTPUT
X Y Z
XY Z (xy z ) ( y + z ) F
0 0 0 1 1 0 1
0 0 1 1 0 1 0
0 1 0 1 1 0 0
0 1 1 1 0 1 0
1 0 0 1 1 0 1
1 0 1 1 0 1 0
1 1 0 0 1 1 0
1 1 1 0 0 0 0
60

61. F = ( xy z ) + (x ( y + z ))
INPUT 1 OUTPUT
X Y Z
XY Z (xy z ) ( y + z ) x ( y + z ) F
0 0 0 1 1 0 1 0
0 0 1 1 0 1 0 1
0 1 0 1 1 0 0 1
0 1 1 1 0 1 0 1
1 0 0 1 1 0 1 1
1 0 1 1 0 1 0 0
1 1 0 0 1 1 0 0
1 1 1 0 0 0 0 0
61

62. F = ( xy z ) + (x ( y + z ))
INPUT 1 OUTPUT
X Y Z
XY Z (xy z ) ( y + z ) x ( y + z ) F
0 0 0 1 1 0 1 0 0
0 0 1 1 0 1 0 1 1
0 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 1
1 0 0 1 1 0 1 1 1
1 0 1 1 0 1 0 0 1
1 1 0 0 1 1 0 0 1
1 1 1 0 0 0 0 0 0
62