This document discusses high performance computing systems. It begins by asking basic questions about what constitutes high performance, who needs high performance systems, and how high performance can be achieved. It then discusses techniques for analyzing performance like simulation and experimentation. The document goes on to cover topics like execution time, factors that influence clock period, techniques for instruction level parallelism like pipelining, VLIW processors, and superscalar processors. It also discusses process level parallel architectures like shared memory multiprocessors and issues they present like cache coherence. Finally, it briefly outlines the history and quest for increasing supercomputer performance.
El Barcelona Supercomputing Center (BSC) fue establecido en 2005 y alberga el MareNostrum, uno de los superordenadores más potentes de España. Somos el centro pionero de la supercomputación en España. Nuestra especialidad es la computación de altas prestaciones - también conocida como HPC o High Performance Computing- y nuestra misión es doble: ofrecer infraestructuras y servicio de supercomputación a los científicos españoles y europeos, y generar conocimiento y tecnología para transferirlos a la sociedad. Somos Centro de Excelencia Severo Ochoa, miembros de primer nivel de la infraestructura de investigación europea PRACE (Partnership for Advanced Computing in Europe), y gestionamos la Red Española de Supercomputación (RES). Como centro de investigación, contamos con más de 456 expertos de 45 países, organizados en cuatro grandes áreas de investigación: Ciencias de la computación, Ciencias de la vida, Ciencias de la tierra y aplicaciones computacionales en ciencia e ingeniería.
These slides are a series of "best practices" for running on the Cray XT line of supercomputers. This talk was presented at the HPCMP meeting at SDSC on 11/5/2009
My ISCA 2013 - 40th International Symposium on Computer Architecture KeynoteDileep Bhandarkar
Keynote speech delivered in Tel Aviv on 25 June 2013.
I had the privilege of being the first speaker at the First Annual Symposium on Computer Architecture in 1973. Over the last 40 years I have worked on PDP-11, VAX, MIPS, Alpha, x86, Itanium, and ARM processors and systems.
Moore’s Law has enabled computer architects to increase the pace of innovation and the development of microprocessors with new instruction sets.
In the 1970s, minicomputers from Digital Equipment Corporation, Data General and Hewlett Packard started to challenge IBM mainframes. The introduction of the 32-bit VAX-11/780 in 1978 was a landmark event. The single chip MicroVAX was introduced in 1985.
The IBM PC was introduced on August 12, 1981, followed by many IBM PC compatible machines from Compaq and others. This led to the tremendous growth of x86 processors from Intel and AMD. Today, the x86 processor dominate the computer industry.
In 1987, the introduction of RISC processors based on Sun’s SPARC architecture spawned the now famous RISC vs CISC debates. RISC processors from MIPS, IBM (Power, Power PC), and HP (PA-RISC) started to gain market share. This forced Digital to first adopt MIPS processors, and later introduce Alpha in 1992.
The RISC supremacy continued until the introduction of the first out of order x86 Pentium Pro processor in 1995, expanding the role of x86 into workstations and servers. The x86 architecture was extended to 64 bits by AMD in the Opteron processor in 2003, forcing Intel to launch its own compatible processor.
Disruptive technologies usually come from below. We have seen users migrate from mainframes to minicomputers to RISC workstations and servers to desktop PCs and PC servers to notebooks and tablets. Volume economics has driven the industry. The next wave will be the technology used in smart phones. With over a billion chips sold annually, this technology will appear in other platforms. Several companies have announced plans for ARM based servers.
Moore’s Law has also enabled computer architects to advance the sophistication of microprocessors. We will review some of the significant milestones leading from the first Intel 4004 to today’s state of the art processors.
Google Never Dies Meetup ( Obbserv + SEMrush ) the vision of digital you Ravi Soni
A perspective of Obbserv to showcase the digital journey, observing the movement of human towards machines and observing the journey of digital from consumer to the brand.
El Barcelona Supercomputing Center (BSC) fue establecido en 2005 y alberga el MareNostrum, uno de los superordenadores más potentes de España. Somos el centro pionero de la supercomputación en España. Nuestra especialidad es la computación de altas prestaciones - también conocida como HPC o High Performance Computing- y nuestra misión es doble: ofrecer infraestructuras y servicio de supercomputación a los científicos españoles y europeos, y generar conocimiento y tecnología para transferirlos a la sociedad. Somos Centro de Excelencia Severo Ochoa, miembros de primer nivel de la infraestructura de investigación europea PRACE (Partnership for Advanced Computing in Europe), y gestionamos la Red Española de Supercomputación (RES). Como centro de investigación, contamos con más de 456 expertos de 45 países, organizados en cuatro grandes áreas de investigación: Ciencias de la computación, Ciencias de la vida, Ciencias de la tierra y aplicaciones computacionales en ciencia e ingeniería.
These slides are a series of "best practices" for running on the Cray XT line of supercomputers. This talk was presented at the HPCMP meeting at SDSC on 11/5/2009
My ISCA 2013 - 40th International Symposium on Computer Architecture KeynoteDileep Bhandarkar
Keynote speech delivered in Tel Aviv on 25 June 2013.
I had the privilege of being the first speaker at the First Annual Symposium on Computer Architecture in 1973. Over the last 40 years I have worked on PDP-11, VAX, MIPS, Alpha, x86, Itanium, and ARM processors and systems.
Moore’s Law has enabled computer architects to increase the pace of innovation and the development of microprocessors with new instruction sets.
In the 1970s, minicomputers from Digital Equipment Corporation, Data General and Hewlett Packard started to challenge IBM mainframes. The introduction of the 32-bit VAX-11/780 in 1978 was a landmark event. The single chip MicroVAX was introduced in 1985.
The IBM PC was introduced on August 12, 1981, followed by many IBM PC compatible machines from Compaq and others. This led to the tremendous growth of x86 processors from Intel and AMD. Today, the x86 processor dominate the computer industry.
In 1987, the introduction of RISC processors based on Sun’s SPARC architecture spawned the now famous RISC vs CISC debates. RISC processors from MIPS, IBM (Power, Power PC), and HP (PA-RISC) started to gain market share. This forced Digital to first adopt MIPS processors, and later introduce Alpha in 1992.
The RISC supremacy continued until the introduction of the first out of order x86 Pentium Pro processor in 1995, expanding the role of x86 into workstations and servers. The x86 architecture was extended to 64 bits by AMD in the Opteron processor in 2003, forcing Intel to launch its own compatible processor.
Disruptive technologies usually come from below. We have seen users migrate from mainframes to minicomputers to RISC workstations and servers to desktop PCs and PC servers to notebooks and tablets. Volume economics has driven the industry. The next wave will be the technology used in smart phones. With over a billion chips sold annually, this technology will appear in other platforms. Several companies have announced plans for ARM based servers.
Moore’s Law has also enabled computer architects to advance the sophistication of microprocessors. We will review some of the significant milestones leading from the first Intel 4004 to today’s state of the art processors.
Google Never Dies Meetup ( Obbserv + SEMrush ) the vision of digital you Ravi Soni
A perspective of Obbserv to showcase the digital journey, observing the movement of human towards machines and observing the journey of digital from consumer to the brand.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
I, a former op, would like to extend an invitation to all application developers to join the observability party will share these foundational concepts to build on:
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
Le nuove frontiere dell'AI nell'RPA con UiPath Autopilot™UiPathCommunity
In questo evento online gratuito, organizzato dalla Community Italiana di UiPath, potrai esplorare le nuove funzionalità di Autopilot, il tool che integra l'Intelligenza Artificiale nei processi di sviluppo e utilizzo delle Automazioni.
📕 Vedremo insieme alcuni esempi dell'utilizzo di Autopilot in diversi tool della Suite UiPath:
Autopilot per Studio Web
Autopilot per Studio
Autopilot per Apps
Clipboard AI
GenAI applicata alla Document Understanding
👨🏫👨💻 Speakers:
Stefano Negro, UiPath MVPx3, RPA Tech Lead @ BSP Consultant
Flavio Martinelli, UiPath MVP 2023, Technical Account Manager @UiPath
Andrei Tasca, RPA Solutions Team Lead @NTT Data
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
2. Some basic questions
– Rate of computation
• What is high
performance? – Time to compute
– Weather prediction,
• Who needs high
complex design, scientific
performance systems?
computation etc.
– Every one needs it.
• How do you achieve – Technology
high performance? – Circuit / logic design
– Architecture
– Theoretical models
• How to analyse or
– Simulation
evaluate performance?
– Experimentation
slide 2
Anshul Kumar, CSE IITD
3. Execution Time and Clock Period
Instruction execution time = Tinst = CPI* Δt
Δt
IF D RF EX/AG M WB
Program exec time = Tprog = N * Tinst
= N * CPI * Δt
N: Number of instructions
CPI : Cycles per instruction(Av)
Δt : Clock cycle time
slide 3
Anshul Kumar, CSE IITD
4. What influences clock period?
Tprog = N * CPI * Δt
Technology - Δt ⇓
⇓
Software - N
Architecture - N * CPI * Δt ⇓
Instruction set architecture (ISA)
N vs CPI * Δt
trade-off
Micro architecture (μA)
CPI vs Δt
trade-off
slide 4
Anshul Kumar, CSE IITD
5. Relative performance per unit cost
Relative performance per unit cost
Year Technology Perf/cost
1951 Vacuum tube 1
1965 Transistor 35
1975 Integrated circuit 900
1995 VLSI 2,400,000
slide 5
Anshul Kumar, CSE IITD
6. Increase in workstation performance
1200
DEC Alpha 21264/600
1100
1000
900
800
Performance
700
600
500
DEC Alpha 5/500
400
300
DEC Alpha 5/300
200
DEC Alpha 4/266
SUN-4/ MIPS IBM
MIPS IBM POWER 100
100
260 M2000 RS6000 DEC AXP/500
M/120
HP 9000/750
0
1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997
Year
slide 6
Anshul Kumar, CSE IITD
7. Growth in DRAM Capacity
100,000
64M
16M
10,000
4M
Kbit capacity
1M
1000
256K
100
64K
16K
10
1996
1976 1978 1980 1982 1984 1986 1988 1990 1992 1994
Year of introduction
slide 7
Anshul Kumar, CSE IITD
8. CPU-Memory Performance Gap
CPU-Memory
• Semiconductor
– Registers CPU speed
Random Access
– SRAM
– DRAM
– FLASH
• Magnetic Slow
– FDD
– HDD
• Optical Random + sequential
– CD Very slow
– DVD
slide 8
Anshul Kumar, CSE IITD
9. Memory Hierarchy Principle
hit
CPU
Speed Size Cost / bit
access
miss
Fastest Memory Smallest Highest
Temporal Locality
Memory
– References repeated in
time
Spatial Locality
– References repeated in
Slowest Memory Biggest Lowest
space
– Special case: Sequential
Locality
slide 9
Anshul Kumar, CSE IITD
16. Händler’s Classification
Händler’s Classification
< K x K’ , D x D’ , W x W’ >
control data word
dash → degree of pipelining
TI - ASC <1, 4, 64 x 8>
CDC 6600 <1, 1 x 10, 60> x <10, 1, 12> (I/O)
C.mmP <16,1,16> + <1x16,1,16> + <1,16,16>
PEPE <1 x 3, 288, 32>
Cray-1 <1, 12 x 8, 64 x (1 ~ 14)>
slide 16
Anshul Kumar, CSE IITD
17. Modern Classification
Modern Classification
Parallel
architectures
Function-parallel
Data-parallel
architectures
architectures
slide 17
Anshul Kumar, CSE IITD
18. Data Parallel Architectures
• SIMD Processors
– Multiple processing elements driven by a single
instruction stream
• Vector Processors
– Uni-processors with vector instructions
• Associative Processors
– SIMD like processors with associative memory
• Systolic Arrays
– Application specific VLSI structures
slide 18
Anshul Kumar, CSE IITD
20. Pipelining
Simple multicycle design :
•resource sharing across cycles
• all instructions may not take same cycles
IF D RF EX/AG M WB
• faster throughput with pipelining
slide 20
Anshul Kumar, CSE IITD
21. Limits of Pipelining
• Structural hazards
– Resource conflicts - two instruction require
same resource in the same cycle
• Data hazards
– Data dependencies - one instruction needs data
which is yet to be produced by another
instruction
• Control Hazards
– Decision about next instruction needs more
cycles
slide 21
Anshul Kumar, CSE IITD
22. ILP in VLIW processors
Cache/ Fetch
memory Unit Single multi-operation instruction
FU FU
FU
Register file
multi-operation instruction
slide 22
Anshul Kumar, CSE IITD
23. ILP in Superscalar processors
Decode
Cache/ Fetch
and issue
memory Unit
unit Multiple instruction
FU FU
FU
Sequential stream of instructions
Instruction/control
Register file
Data
FU Funtional Unit
slide 23
Anshul Kumar, CSE IITD
24. Superscalar and VLIW processors
Superscalar and VLIW processors
slide 24
Anshul Kumar, CSE IITD
25. Issues in ILP Architectures
FU FU FU
Register file
•Scalability with increase in number of register ports
•ILP detection – special compilers / special hardware
•Code compatibility
•Code density, Instruction encoding
•Maintaining consistency
slide 25
Anshul Kumar, CSE IITD
26. ILP and Multithreading
ILP Coarse MT Fine MT SMT
Hennessy and Patterson
slide 26
Anshul Kumar, CSE IITD
27. Why Process level Parallel Architectures?
Why Process level Parallel Architectures?
Function-parallel
Data-parallel
architectures
architectures
Instruction Thread Process
level PAs level PAs level PAs
(MIMDs)
Built using
general purpose
Shared
Distributed
processors
Memory
Memory
MIMD
MIMD
slide 27
Anshul Kumar, CSE IITD
28. Issues from user’s perspective
user’s
• Specification / Program design
– explicit parallelism or
– implicit parallelism + parallelizing compiler
• Partitioning / mapping to processors
• Scheduling / mapping to time instants
– static or dynamic
• Communication and Synchronization
slide 28
Anshul Kumar, CSE IITD
29. Parallel programming models
Concurrent Functional or Vector/array
control flow logic program operations
Concurrent
tasks/processes/threads/objects
Relationship between
With shared variables
programming model
or message passing
and architecture ?
slide 29
Anshul Kumar, CSE IITD
30. Issues from architect’s perspective
Issues from architect’s perspective
• Coherence problem in shared memory with
caches
• Efficient interconnection networks
slide 30
Anshul Kumar, CSE IITD
31. Shared Memory Multiprocessor
Shared Memory Multiprocessor
M M M M M M
M M
P P P P P P P P
Interconnection Network Interconnection Network
M M M M M M
Global Interconnection Network
M M M
slide 31
Anshul Kumar, CSE IITD
32. Cache Coherence Problem
Multiple copies of data may exist
⇒ Problem of cache coherence
Options for coherence protocols
• What action is taken?
– Invalidate or Update
• Which processors/caches communicate?
– Snoopy (broadcast) or directory based
• Status of each block?
slide 32
Anshul Kumar, CSE IITD
33. Interconnection Networks
• Architectural Variations:
– Topology
– Direct or Indirect (through switches)
– Static (fixed connections) or Dynamic (connections
established as required)
– Routing type store and forward/worm hole)
• Efficiency:
– Delay
– Bandwidth
– Cost
slide 33
Anshul Kumar, CSE IITD
34. Quest for Performance
1946 ENIAC ($0.5 M, 18K VTs, 150 kW)
add/sub 5000 per sec
mult 385 per sec
div 40 per sec
sqrt 3 per sec
1962 Atlas (Pipelined, Int + FPU)
200K FLOPs
1962 Burroughs D825 (4 CPUs 16 Mem)
1964 CDC 6600 (first supercomputer)
multiple FUs, dynamic scheduling
1972 ILLIAC-IV (64 PEs, 4 MFLOPs each)
slide 34
Anshul Kumar, CSE IITD
35. Fastest Supercomputer
(ref www.top500.org)
(ref www.top500.org)
• IBM’s Blue Gene/L at Lawrence Livermore Lab
topped in June 2006 with 280.6 teraflops
• Japan’s Earth simulator introduced in 2002 was
fastest with 35.8 teraflops till Blue Gene took over in
2004.
• Japan’s proposal (2005) to build a supercomputer 73
times faster than the current best. Target: 10
petaflops, budget $800 - $900 million, date 2011.
• Tata sons’ EKA entered 4th spot in 2007 with 132.8
teraflops
• Energy efficiency (max 488 mflopr/watt) also listed
in June 2008
slide 35
Anshul Kumar, CSE IITD
36. June 2008 list
June 2008 list
Site Computer
Rank
Roadrunner - BladeCenter QS22/LS21 Cluster,
1 DOE/NNSA/LANL United States PowerXCell 8i 3.2 Ghz / Opteron DC 1.8 GHz ,
Voltaire Infiniband, IBM (1026 teraflops)
2 DOE/NNSA/LLNL United States BlueGene/L - eServer Blue Gene Solution, IBM
Argonne National Laboratory
3 Blue Gene/P Solution, IBM
United States
Texas Advanced Computing
Ranger - SunBlade x6420, Opteron Quad 2Ghz,
4 Center/Univ. of Texas United
Infiniband, Sun Microsystems
States
DOE/Oak Ridge National
5 Jaguar - Cray XT4 QuadCore 2.1 GHz, Cray Inc.
Laboratory United States
6 Forschungszentrum Juelich (FZJ) JUGENE - Blue Gene/P Solution, IBM
New Mexico Computing
Encanto - SGI Altix ICE 8200, Xeon quad core
7 Applications Center (NMCAC)
3.0 GHz, SGI
United States
Computational Research EKA - Cluster Platform 3000 BL460c, Xeon 53xx
8
Laboratories, TATA SONS India 3GHz, Infiniband, HP (133 teraflops)
37. Blue Gene Supercomputer
• 32 x 32 x 64 3D torus (65,536 nodes)
• Global reduction tree - max/sum in a
few μs
• Fast synch across entire machine within
a few μs
• 1,024 gbps links to a global parallel file
system
slide 37
Anshul Kumar, CSE IITD
38. Blue Gene Supercomputer contd.
Blue Gene Supercomputer contd.
slide 38
Anshul Kumar, CSE IITD
39. Embedded vs GP Computing
• Fixed functionality
• Part of a larger system
• Interact with environment
• Real-time requirements
• Power constraints
• Environmental contraints
• Performance can not be increased simply by
increasing clock frequency
slide 39
Anshul Kumar, CSE IITD