The document describes the operation of a superscalar processor using scoreboarding to handle data dependencies between instructions. It shows the status of six instructions being issued and executed across five functional units in multiple cycles. The status includes which functional units are busy, the operations and operands being processed, and the status of instructions in the issue, execute, and writeback stages.

1. CSL718 : Superscalar
Processors
Handling Data Dependencies
2nd Feb, 2009
Anshul Kumar, CSE IITD

2. Illustration 1
CDC6600 : score-boarding scheme
• Dispatch bound fetch
• FUs : INT, MUL1, MUL2, ADD/SUB, DIV
• 1 RS per FU
• 1 RF
• In order issue, dispatch order trivial, out of
order execution
slide 2
Anshul Kumar, CSE IITD

3. Checking in dispatch bound fetch
Checking in dispatch bound fetch
decoded
instruction
check V bits of sources
Reservation
station
update Rd
Rs1,Rs2,Rd set V bit
OC Rs1 Rs2 Rd
reset V bit of Rd
Register
File
Os1
OC
(opcode)
Os2 (operand value)
EU
result, Rd
slide 3
Anshul Kumar, CSE IITD

4. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status LF F6, 34(R2)
LF F2, 45(R3)
MUL F0,F2,F4
SUB F8,F6,F2
DIVF10,F0,F6
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT
2 MUL1
3 MUL2
4 ADD
5 DIV
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No

5. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√
LF F2, 45(R3)
√
MUL F0,F2,F4
√
SUB F8,F6,F2
√
DIVF10,F0,F6
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT Y LF
2 MUL1 Y MUL
3 MUL2 N
4 ADD Y SUB
5 DIV Y DIV
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No

6. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√
LF F2, 45(R3)
√
MUL F0,F2,F4
√
SUB F8,F6,F2
√
DIVF10,F0,F6
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT Y LF F2 R3
2 MUL1 Y MUL F0 F2 F4
3 MUL2 N
4 ADD Y SUB F8 F6 F2
5 DIV Y DIV F10 F0 F6
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No

7. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√
LF F2, 45(R3)
√
MUL F0,F2,F4
√
SUB F8,F6,F2
√
DIVF10,F0,F6
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT Y LF F2 R3 Y Y
2 MUL1 Y MUL F0 F2 F4 1 N Y
3 MUL2 N
4 ADD Y SUB F8 F6 F2 1 Y N
5 DIV Y DIV F10 F0 F6 2 N Y
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 2 1 4 5

8. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √
LF F2, 45(R3)
√
MUL F0,F2,F4
√
SUB F8,F6,F2
√
DIVF10,F0,F6
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT Y LF F2 R3 N N
2 MUL1 Y MUL F0 F2 F4 1 N Y
3 MUL2 N
4 ADD Y SUB F8 F6 F2 1 Y N
5 DIV Y DIV F10 F0 F6 2 N Y
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 2 1 4 5

9. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √ √ √
LF F2, 45(R3)
√
MUL F0,F2,F4
√
SUB F8,F6,F2
√
DIVF10,F0,F6
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT N
2 MUL1 Y MUL F0 F2 F4 Y Y
3 MUL2 N
4 ADD Y SUB F8 F6 F2 Y Y
5 DIV Y DIV F10 F0 F6 2 N Y
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 2 4 5

10. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √ √ √
LF F2, 45(R3)
√ √
MUL F0,F2,F4
√ √ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT N
2 MUL1 Y MUL F0 F2 F4 N N
3 MUL2 N
4 ADD N
5 DIV Y DIV F10 F0 F6 2 N Y
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 2 5

11. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √ √ √
LF F2, 45(R3)
√ √
MUL F0,F2,F4
√ √ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
√
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT N
2 MUL1 Y MUL F0 F2 F4 N N
3 MUL2 N
4 ADD Y ADD F6 F8 F2 Y Y
5 DIV Y DIV F10 F0 F6 2 N Y
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 2 4 5

12. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √ √ √
LF F2, 45(R3)
√ √
MUL F0,F2,F4
√ √ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
√ √
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT N
2 MUL1 Y MUL F0 F2 F4 N N
3 MUL2 N
4 ADD Y ADD F6 F8 F2 N N
5 DIV Y DIV F10 F0 F6 2 N Y
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 2 4 5

13. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √ √ √
LF F2, 45(R3)
√ √
MUL F0,F2,F4
√ √ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
√ √ √
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT N
2 MUL1 Y MUL F0 F2 F4 N N
3 MUL2 N
4 ADD Y ADD F6 F8 F2 N N
5 DIV Y DIV F10 F0 F6 2 N Y
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 2 4 5

14. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √ √ √
LF F2, 45(R3)
√ √ √ √
MUL F0,F2,F4
√ √ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
√ √ √
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT N
2 MUL1 N
3 MUL2 N
4 ADD Y ADD F6 F8 F2 N N
5 DIV Y DIV F10 F0 F6 Y Y
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 4 5

15. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √ √ √
LF F2, 45(R3)
√ √ √ √
MUL F0,F2,F4
√ √ √ √
SUB F8,F6,F2
√ √
DIVF10,F0,F6
√ √ √
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT N
2 MUL1 N
3 MUL2 N
4 ADD Y ADD F6 F8 F2 N N
5 DIV Y DIV F10 F0 F6 N N
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 4 5

16. INSTRUCTION ISSUE READ OP EX COMPL WRITERES
Instruction status √ √ √ √
LF F6, 34(R2)
√ √ √ √
LF F2, 45(R3)
√ √ √ √
MUL F0,F2,F4
√ √ √ √
SUB F8,F6,F2
√ √
DIVF10,F0,F6
√ √ √ √
ADD F6,F8,F2
No NAME BUSY OP Fi Fj Fk Qj Qk Rj Rk
Functional Units
1 INT N
2 MUL1 N
3 MUL2 N
4 ADD N
5 DIV Y DIV F10 F0 F6 N N
F0 F2 F4 F6 F8 F10 F12 F14
RF
FU No 5

17. Illustration 2
IBM 360/91 - Tomasulo’s scheme
• Issue bound fetch
• FUs : LOAD, STORE, 3 x ADD/SUB,
2 x MUL/DIV
• Group RS’s with 1 slot per FU
• 1 RF
• In order issue, out of order execution
slide 17
Anshul Kumar, CSE IITD

18. Checking in issue bound fetch
Checking in issue bound fetch
decoded update Rd, set V bit
Rs1,Rs2,Rd
instruction reset V bit of Rd
Register
File
Os1
Os2 (operand value)
check Vs1, Vs2
Reservation station
OC, Os1, Os2, Rd
OC Os1/Is1 Vs1 Os2/Is2 Vs2 Rd
associative update of
EU
Is1, Is2 with Rd, set Vs bits
result, Rd
slide 18
Anshul Kumar, CSE IITD

19. INSTRUCTION ISSUE EX COMPL WRITERES
Instruction status LF F6, 34(R2)
LF F2, 45(R3)
MUL F0,F2,F4
SUB F8,F6,F2
DIVF10,F0,F6
ADD F6,F8,F2
NAME BUSY OP Vj Vk Qj Qk
Functional Units
ADD1
ADD2
ADD3
MUL1
MUL2
F0 F2 F4 F6 F8 F10 F12 F14
RF
Qi

20. INSTRUCTION ISSUE EX COMPL WRITERES
Instruction status √ √ √
LF F6, 34(R2)
√
LF F2, 45(R3)
√
MUL F0,F2,F4
√
SUB F8,F6,F2
√
DIVF10,F0,F6
√
ADD F6,F8,F2
NAME BUSY OP Vj Vk Qj Qk
Functional Units
ADD1 Y SUB
ADD2 Y ADD
ADD3 N
MUL1 Y MUL
MUL2 Y DIV
F0 F2 F4 F6 F8 F10 F12 F14
RF
Qi

21. INSTRUCTION ISSUE EX COMPL WRITERES
Instruction status √ √ √
LF F6, 34(R2)
√
LF F2, 45(R3)
√
MUL F0,F2,F4
√
SUB F8,F6,F2
√
DIVF10,F0,F6
√
ADD F6,F8,F2
NAME BUSY OP Vj Vk Qj Qk
Functional Units
ADD1 Y SUB (LD1) LD2
ADD2 Y ADD ADD1 LD2
ADD3 N
MUL1 Y MUL (F4) LD2
MUL2 Y DIV (LD1) MUL1
F0 F2 F4 F6 F8 F10 F12 F14
RF
Qi MUL1 LD2 ADD2 ADD1 MUL2

22. INSTRUCTION ISSUE EX COMPL WRITERES
Instruction status √ √ √
LF F6, 34(R2)
√ √ √
LF F2, 45(R3)
√
MUL F0,F2,F4
√
SUB F8,F6,F2
√
DIVF10,F0,F6
√
ADD F6,F8,F2
NAME BUSY OP Vj Vk Qj Qk
Functional Units
ADD1 Y SUB (LD1) (LD2)
ADD2 Y ADD (LD2) ADD1
ADD3 N
MUL1 Y MUL (LD2) (F4)
MUL2 Y DIV (LD1) MUL1
F0 F2 F4 F6 F8 F10 F12 F14
RF
Qi MUL1 ADD2 ADD1 MUL2

23. INSTRUCTION ISSUE EX COMPL WRITERES
Instruction status √ √ √
LF F6, 34(R2)
√ √ √
LF F2, 45(R3)
√
MUL F0,F2,F4
√ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
√
ADD F6,F8,F2
NAME BUSY OP Vj Vk Qj Qk
Functional Units
ADD1 N
ADD2 Y ADD (ADD1) (LD2)
ADD3 N
MUL1 Y MUL (LD2) (F4)
MUL2 Y DIV (LD1) MUL1
F0 F2 F4 F6 F8 F10 F12 F14
RF
Qi MUL1 ADD2 MUL2

24. INSTRUCTION ISSUE EX COMPL WRITERES
Instruction status √ √ √
LF F6, 34(R2)
√ √ √
LF F2, 45(R3)
√ √
MUL F0,F2,F4
√ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
√ √
ADD F6,F8,F2
NAME BUSY OP Vj Vk Qj Qk
Functional Units
ADD1 N
ADD2 Y ADD (ADD1) (LD2)
ADD3 N
MUL1 Y MUL (LD2) (F4)
MUL2 Y DIV (LD1) MUL1
F0 F2 F4 F6 F8 F10 F12 F14
RF
Qi MUL1 ADD2 MUL2

25. INSTRUCTION ISSUE EX COMPL WRITERES
Instruction status √ √ √
LF F6, 34(R2)
√ √ √
LF F2, 45(R3)
√ √
MUL F0,F2,F4
√ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
√ √ √
ADD F6,F8,F2
NAME BUSY OP Vj Vk Qj Qk
Functional Units
ADD1 N
ADD2 N
ADD3 N
MUL1 Y MUL (LD2) (F4)
MUL2 Y DIV (LD1) MUL1
F0 F2 F4 F6 F8 F10 F12 F14
RF
Qi MUL1 MUL2

26. INSTRUCTION ISSUE EX COMPL WRITERES
Instruction status √ √ √
LF F6, 34(R2)
√ √ √
LF F2, 45(R3)
√ √ √
MUL F0,F2,F4
√ √ √
SUB F8,F6,F2
√
DIVF10,F0,F6
√ √ √
ADD F6,F8,F2
NAME BUSY OP Vj Vk Qj Qk
Functional Units
ADD1 N
ADD2 N
ADD3 N
MUL1 N
MUL2 Y DIV (MUL1) (LD1)
F0 F2 F4 F6 F8 F10 F12 F14
RF
Qi MUL2

27. Reference
1. D.A. Patterson, J.L. Hennessy, quot;Computer
Architecture : A Quantitative Approachquot;,
Morgan Kaufmann Publishers, 2006.
slide 27
Anshul Kumar, CSE IITD