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 The sources of power consumption on a CMOS chip can be classified as
dynamic power, short circuit and static current. But at algorithm level we are
consider only dynamic power and rest are determined at the circuit level.
Using the smart circuit techniques ,we can reduce the dissipation due to short
circuit currents to less than 15% of the entire power.
The power dissipated can given by the equation,
Power = Ceff V2f
Ceff = aC
 Algorithm level analysis are to be used for guiding design as its help in
magnitude improvement, accuracy and give accurate relative information.

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POWER DISSIPATION
Algorithm Inherent
Dissipation
Implementation
Overhead
 The AID comprises the power of the execution units and
memory. This is inherent in the sense that it necessary to achieve
the basic functionality of the algorithm.
 The IO includes control interconnect and registers. The power
consumed by this component depends largely on the choice of
architecture and implementation.

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 The AID refers to the power consumed by the execution units and memory. This
component is fundamental to a given algorithm and is the prime factor for comparison
between different algorithms as well as for the qualifying the effect of algorithm level
design decisions.
 Its dissipation can be estimated by a weighted sum of the number of operations in
the algorithm. The weights used for the different operations must reflect the respective
capacitances switched.
To estimate the capacitance switched at this level it is necessary to ignore the
statistics of the applies data and to employ a white noise model i.e. random data.
Switching statistics are strongly influenced by the hardware architecture. The mapping
of operators onto the hardware resources effects the temporal correlations between
signals.

5. ASET
 The implementation overhead consists of the control Interconnect and
implementation related memory/register power. The power consumed by these
components depends on the specific architecture platform chosen and on the
mapping of the algorithm onto the hardware.
 Since this overhead is not essential to the basic functionality of a given algorithm,
several estimation tools ignore its effect for algorithm level comparisons. The
power consumed by these components is often comparable if not greater than the
AID.
 So, its important to get reasonable estimates of the implementation overhead for
realistic comparisons algorithms and to guide high level decisions.

6. ASET
The implementation dependant power consumption is strongly correlated to a number of
properties of the algorithm. For example, structural property of an algorithm may affect
the amount of his overhead is the locality of reference.
SPATIAL LOCALITY TEMPORAL LOCALITY
1. It refers to the extent to which an
alog. can be partitioned into natural
clusters based on connectivity.
2. A spatially local alog. renders itself more
easily to efficient partitioning on
hardware, allowing highly capacitive
global buses to be used sparingly.
3. In terms of memory/registers access,
spatial locality refers to the distance
between the address of items referenced
close together in time.
4. A spatially local memory access pattern
allows portioning of memory into smaller
blocks that require less power per access.
1. It refers to the average lifetimes of
variables.
2. It tends to require less temporary
Storage and have small registers files
leading to lower capacitances.
3. It refers to the probability of future
access to items referenced in the
past.
4. Its does not allow any portioning
of memory into smaller blocks.

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After examining methods for estimating power consumption at the algorithm level,
The next logical step is to examine power minimization techniques at this level.
The general approaches for power minimization are:
1. Voltage Reduction: At the algorithm level, functional pipelining, retiming, algebraic
transformations and loop transformations can be used to increase the speed and
allow lower voltages but these approaches often translate into larger silicon area
Implementations and hence this approach is called as trading area for power.
2. Avoiding Wasteful Activity: At the algorithm level the size and complexity of a given
algorithm(operation counts word lengths) determine the activity. If there are several
algorithm for a given task the one with least number of operations is preferable.

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This category includes:
 Operation Reduction : It includes common sub expression elimination, algebraic
transformations, dead code elimination.
 Strength Reduction: It refers to replacing energy consuming operations by a
combination of simpler operations. The most common in this category is expansion of
multiplications by constraint into shift and add operations. Its results in low power but
sometimes it results opposite if there is increase in the critical path.
 Memory Path: Algorithm level transformations for minimizing the power
consumption of memories present in. These include conversion of background
memory to foreground register files and reduction of memory size using loop
reordering and loop merging transformations.

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 It is a more challenging problem as these algorithm posses structural properties
such as locality and regularity and we have to detect these properties.
 Spatial Locality can be detected and used to guide portioning . Regular algorithm
typically require less control and interconnect overhead.
 Other way to reduce the implementation overhead is to reduce the chip area as
this typically translates into reduced bus capacitances.

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The effect of data correlation on power dissipation often depends on the
numerical representation of the digital system.
 If the data sample is positively correlated, successive data sample values
are very close in their binary representation.
 UNIFORM WHITE NOISE REGION: If the LSB bits toggle at
approximately half the maximum frequency as bits are toggle in the random
fashion.
 on MSB side, the bits have a very low toggle rate and they are called the
SIGN BIT REGION as most of the toggling in this region are sign change
and have very high Switching Frequency.
 GREY REGION is the area between two regions where the toggle
frequency changes from WHITE NOISE to SIGN BIT.

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