Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.509-513509 | P a g eStudy of Existing Full Adders and To Design a LPFA (Low PowerFull Adder)Pardeep Kumar, Susmita Mishra, Amrita Singh1Department of ECE, B.M.S.E.C, Muktsar, 2,3Asstt. Professor, B.M.S.E.C, MuktsarAbstractThis paper describes the different logicstyle used for CMOS full adders and differentequation used to implement the required Booleanlogic for full adders. This paper also describesthat the speed of the design is limited by size ofthe transistors, parasitic capacitance and delayin the critical path. Power consumption andspeed are two important but conflicting designaspects; hence a better metric to evaluate circuitperformance is power delay product (PDP).Thedriving capability of a full adder is veryimportant, because, full adders are mostly usedin cascade configuration, where the output of oneprovides the input for other. If the full adderslack Driving capability then it requiresadditional buffer, which consequently increasesthe power dissipation. At last a new LPFADesign is proposed with comparisons betweenthe various full adders to show the betterperformance of LPFA in terms of powerconsumption, area (number of transistors) anddelay. The LPFA and all other various fulladders are designed and simulated using mentorgraphics tool in 0.18 μm technology. Thefrequency used is 100 MHz. the voltage and allthe various full adders and others designs aresimulated at a voltage supply of 1.8V at samefrequency.Keywords: CMOS Transmission Gate (TG),PassTransistor Logic (PTL), Complementary Pass-transistor Logic (CPL), Gate Diffusion Input (GDI),LPFA (Low Power Full Adder), GDI based fulladder Power, Delay1. IntroductionADDITION is one of the fundamentalarithmetic operations. It is used extensively in manyVLSI systems such as application-specific DSParchitectures and microprocessors. In addition to itsmain task, which is adding binary numbers, it is thenucleus of many other useful operations such assubtraction, Multiplication, division, addressescalculation, etc. In most of these systems the adderis part of the critical path that determines the overallperformance of the system. That is why enhancingthe performance of the 1-bit full-adder cell (thebuilding block of the binary adder) is a significantgoal.The choice of logic style to design digital circuitsstrongly influences the circuit performance. Thedelay time depends on the size of transistors, thenumber of transistors per stack, the parasiticcapacitance including intrinsic capacitance andcapacitance due to intracell and intercell routing,and the logic depth (i.e., number of logic gates inthe critical path). The dynamic power consumptiondepends on the switching activity and the numberand size of transistors. Among other things, the diearea depends on the number and size of transistorsand routing complexity.At the system level, in many synchronousimplementations of microprocessors, the adder liesin the critical path because it is a key element in awide range of arithmetic units such as ALUs andmultipliers.Extensive variants of full adders have beeninvestigated by the academic and industrial researchcommunities. The usual performance evaluationsare speed, power consumption, and area. However,since mobile and embedded applications haveprioritized the power consumption to stand at thetop of circuit and system performance evaluations,the goal of many of these full-adder variants hastraditionally been the reduction of transistor count.However, Chang et al. have shown in that althoughsome of these full adders feature good behaviorwhen implementing a 1-bit cell, they may showperformance degradation when used to implementmore complex structures.Recently, building low-power VLSIsystems has emerged as highly in demand becauseof the fast growing technologies in mobilecommunication and computation. The batterytechnology doesn’t advance at the same rate as themicroelectronics technology. There is a limitedamount of power Available for the mobile systems.So designers are faced with more constraints: highspeed, high throughput, small silicon area, and atthe same time, low-power consumption. So buildinglow-power, high-performance adder cells is of greatinterest.2. Equation used in CMOS full addersA full adder performs the addition of twobits A and B with the Carry (Cin) bit generated inthe previous stage. The integer equivalent of thisrelation is shown by:
Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.509-513510 | P a g eA+B+Cin=2xCout +Sum (1)The conventional logic equation for Sum and Carryare:Cout= (A∙B) + (A+B)∙Cin (2)Sum= (A∙B∙Cin) + (A+B+Cin) ∙Cout (3)By modifying the equations (2) and (3) thefollowing logics were proposed:-Sum= A B Cin (4)Cout= Cin (A B) +A∙(A B) (5)Sum= A B Cin (6)Sum= (Cin∙(A B)) + (Cin∙(A B) (7)Cout= Cin (A∙B) + Cin∙(A+B) (8)Full Adder using CMOS Logic and will be called as“Conventional CMOS design”.3. Existing full adder circuitsThere are standard implementations for thefull-adder cell that are used from last few yearssome of them among these adders there are thefollowing:-Figure.1- The Conventional CMOS full-adderThe CMOS full adder (CMOS) has 28 transistorsand is based on the regular CMOS structureThe Mirror logic  style based full adder has 28transistorsFigure-2: Mirror logic style based full adderThe DPL logic  style based full adder has 28transistorsA Transmission gate full adder  using 18transistorsA full adder cell using 14 transistorsA full adder cell using 10 transistorsFigure: 3-DPL logic style based full adderFigure-4: Transmission gate full adder
Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.509-513511 | P a g eThe DPL provides a saving power of about 2% overthe conventional CMOS based full adder. But theygenerally do not provide good advantage over thedelay. So the main advantage in PDP (power delayproduct) is only due to lesser power consumingLogic style. The TG-FA provides a power saving of1% and delay reduction of about 2% over theconventional CMOS Based full adder..Fig-5:14-T full adder cell Figure-6:10-T fulladder cell4. Design of Low Power XOR and LowPower XNORThe improved versions are illustrated inFig. 11 and Fig.12.In the improved versions bothdesigns use 4transistors to achieve the samefunctions of XOR and XNOR.Fig:-11: LP XOR gate Fig 12:-: LP XNOR gateAnalysis on XOR structure, the outputsignals in the cases of input signal AB = 01, 10, 11will be complete. When AB = 00, each PMOS willbe on and will pass a poor “LO’ signal level to theoutput end. That is, if AB = 00, the output end willdisplay a voltage, threshold voltage ~Vpth, a littlehigher than “LO”. For the XNOR function, theoutput signal in the case of AB = 00, 01, 10 will becomplete. While AB = 11, each NMOS will be onand pass the poor “HI” signal level to the outputend. The analysis of driving capability is the sameas XOR structure. The structures stated above arethe versions of 4 transistors without a drivingoutput.Fig:-13: LP XOR gate Fig 14:-: LP XNOR gateWith driving outputs with driving outputsBy cascading a standard inverter to the LPXNOR circuit, a new type of XOR, as shown in Fig.13 and Fig 14, will have a driving output, and thesignal level at the output end will be perfect in allcases. The same property is present in the XNORstructure.The output waveforms for XOR andXNOR for are given inputs A and B are shown inFig 15, 16 and Fig 17.Fig-15:-showing the input signals A and B.Fig:-16:- Showing the output of 6-transistorXOR.Fig:-17:- Showing the output of 6-transistorXNOR
Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.509-513512 | P a g e5. Design of Low Power Adder Using LPXOR and XNORThe Low power full adder which takeslesser number of transistors than the all otherpreviously discussed configurations. The majordrawback of this method is that although it utilizeslesser number of transistors but it does not providefull swing at the output which is needed to drive anyexternal load. So to avoid this type of problem wewill form the XOR by using XNOR followed by aninverter. Figure:-50 shown below is the schematicfor the LOW POWER FULL ADDER (LPFA).Figure 50:- LPFA (Low Power Full Adder)schematicNow next we will show the sum and carry outputwaveform of LPFA (Low Power Full Adder).Figure 51:-Input and Sum output waveform ofLPFAFigure 52:- Input and Carry output waveform ofLPFAFigure 53:-Showing average current of LPFANow we will use this average current waveform tofind the dynamic power dissipation.Dynamic power dissipation P= (average current)x (voltage supply (Vdd))SoP = (10.5152µA) x (1.8V) =18.92736 µW6. Conclusion and Future workAs observed from the discussion aboutthe full adder that various designs have their ownadvantage and disadvantage in terms of area, delayand power consumption. So reducing any of theseparameters will leads to a high performance designof full adder design.
Pardeep Kumar, Susmita Mishra, Amrita Singh / International Journal of EngineeringResearch and Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.509-513513 | P a g eHence we can see that LPFA (Low Power FullAdder) is better than all the other full adder designsin terms of Power consumption, Area (Number ofTransistor), Delay, PDP (Power Delay Product.Future work will be focused on thereduction of any of the parameter shown above i.e.Area, Delay and Power. There is also another termi.e. PDP (power delay product) this is generallyused for to make a trade-off between powerconsumption and delay.Table 5:- Showing the comparison ofperformance Conventional CMOS full Adder,BBL-PT based full adder, HYBRID FULLADDER and LPFADesignDelay(ps)StaticPowerDissipation(pW)DynamicPowerDissipation(µW)TotalPower(µW)TransistorCountConventionalCMOS fulladder124 143.59223.744323.7444328BBL-PTlogicbasedfulladder110.3 126.30822.6063822.60650627Hybrid fulladder142 158.67429.787129.78725830LowPower fulladder(LPFA)101.2113.86918.9273618.92747326Figure-5References. I.Hassoune, A.Neve, J.Legat, andD.Flandre, “Investigation of low-powercircuit techniques for a hybrid full-addercell,” in Proc. PATMOS 2004, pp. 189–197, Springer-Verlag. A.M.Shams, Tarek k.darwish,”performance analysis of low-power 1-bitCMOS full adder cells IEEE Trans. VeryLarge Scale Integ. (VLSI) Syst vol. 10 no.1, pp.20-29, feb.2002.. C.-H. Chang, M. Zhang, “A review of0.18 m full adder performances for treestructured arithmetic circuits,” I EEETrans. Very Large Scale Integration.(VLSI) Syst. vol. 13, no. 6, pp. 686–694,Jun. 2005.. M.aguir re, M.linares “an alternativelogic app roach to implement high speedlow power full adder cells”SBBCI SEP2005 PP. 166-171. A.K. Aggarwal, S. wairya, andS.Tiwari,”a new full adder for highspeed low power digital circuits “worldscience of journal 7 special issue ofcomputer and IT: June 2009,pp.- 138-144. M.Hossein, R.F.Mirzaee, K.Navi andT.Nikoubin” new high performancemajority function based full adder cell” 14inter national CSI conference 2009, pp.100- 104. A.M.Shams,” A new full adder cell forlow power applications“ centre foradvance computer studies, university ofsouthwestern Louisiana. D.Radhakrishnan,” low power CMOS fulladder” IEE proc: - circuits devices systemvol. 148 no. 1 Feb. 2001.pp- 19-24. John p. Uyemura “Introduction to VLSIcircuits and systems”