The document describes and compares self-calibration techniques for high-resolution pipeline ADCs. It discusses purely digital, purely analog, and mixed-signal calibration approaches. A mixed-signal technique is proposed that calibrates the multi-bit first stage of an ADC without modifications, using on-chip thermal noise as the analog input stimulus and a calibration algorithm that does not require explicit multiplications. Experimental results show the technique improves SFDR by over 14 dB and THD by over 10 dB for a 13-bit ADC, achieving a peak ENOB of 11.3 bits.

1. Purely-Digital versus Mixed-Signal Self-Calibration
Techniques in High-Resolution Pipeline ADCs
J. Goes1, 2, N. Paulino1, 2, M. Figueiredo1, E. Santin1 M. Rodrigues2, P. Faria2, B. Vaz2, R. Monteiro2
1 2
− Dept. of Electrical Engineering and CTS-UNINOVA − S3 Group
Faculty of Sciences and Technology (FCT) Madan Parque, Rua dos Inventores
Universidade Nova de Lisboa (UNL) 2825-182 Caparica, PORTUGAL
Campus da FCT/UNL, 2825-114 Caparica, PORTUGAL joao.goes@s3group.com
jg@uninova.pt
Abstract—This paper describes and compares some of the most limited by the gain-error (GE) and static linearity errors (LE)
energy and area efficient self-calibration techniques reported of the MDAC in the first stage, caused by capacitor mismatch
over the past years. Additional techniques used to further errors in the DAC and by the finite DC gain of the residue
improve power dissipation are briefly described as well. A amplifier. The accuracy required for this first MDAC is that of
robust mixed-signal self-calibration technique is proposed, in the overall ADC and it is progressively relaxed in the
which, the multi-bit first stage in the ADC is calibrated without following stages.
requiring any modifications, as long as the ideal conversion
characteristic of this stage is known. A novel Gaussian Noise Without using digital factory trimming [2], self-
Generator is used as the input analog stimulus and, on the configuring schemes [3] or self-calibration techniques, the
digital side, the calibration algorithm does not require explicit overall resolution of these ADCs is bounded to 10 bits by the
multiplications, which greatly simplifies the digital circuitry. capacitor’s matching accuracy provided by most CMOS
Experimental measurements of a 13-bit ADC fabricated in 90 processes available today. This accuracy is limited by the
nm CMOS, after calibration and at 40 MS/s, show that the lithography and subsequent processing steps [4]. As factory
SFDR is improved by over 14 dB (to 84 dB), the THD is trimming can add to the manufacturing costs, self-calibration
improved by over 10 dB (to −80 dB), achieving a peak ENOB of techniques, applied in the field, must be considered for
11.3 bits for a 10 MHz input and with a 1.2 V power supply. extending the resolution beyond 10-bits.
I. INTRODUCTION
An alternative to using trimming or self-calibration, is to
High resolution analog-to-digital converters (ADCs) with employ active [5, 6] or passive [7-10] capacitor error-
sampling rates in the range of 40 to 160 MS/s are required in averaging (CEA) or mismatch-insensitive (MI) [11-13]
high-quality imaging and modern digital communication techniques. However, all these solutions either trade time for
systems. Low-voltage, low-power, and low area are of great accuracy by using more than one clock cycle to provide the
importance in the design of these ADCs. For single battery accurate amplified residue value [5-10], or they use additional
operated systems, low power dissipation is necessary to ensure amplifiers [11] or they increase hardware complexity and
a reasonable battery lifetime. Finally, silicon area is of thermal noise [12, 13]. Thus, all these averaging solutions lead
paramount importance since it is directly related with the cost to ADCs with lower energy-efficiency, although they allow
of the integrated circuit (IC). reasonable conversion rates [6, 10]. Although these techniques
When very high conversion rates are envisaged, the ADCs are not covered in this paper, the authors believe that, they will
usually employ pipelining to relax the speed requirements of become a very efficient alternative to self-calibration to be
the analog components. A cascade of stages is used, each taken into account, for effective-number-of-bits (ENOB) of
consisting of a low resolution flash quantizer and a low the order of 11-to-13 bit, even when high sampling rates are
resolution multiplying digital-to-analog (DAC) converter targeted. Provided that, significant research efforts are to be
(MDAC), which computes and amplifies the residue to be applied in order to propose new MI 1.5-bit resolution MDAC
quantized by the following stages [1]. The flash quantizer circuits with speed and noise performances comparable to the
typically comprises a bank of comparators and the MDAC existing conventional topologies.
employs an amplifier (opamp) with a capacitor feedback It is possible to use self-calibration techniques to
network to provide linear voltage amplification. The DC compensate for the variations inherent in IC processing. They
offsets in the opamps and comparators do not affect the work in two steps: first measuring the LE and GE in a given
overall linearity of a pipeline ADC, if redundancy and proper ADC, and in a second step applying, in a post-calibration
output encoding are adopted. Hence, the accuracy is mainly mode, the corresponding correction countermeasures.
978-1-4244-8278-8/10/$26.00 c 2010 IEEE

2. Self-calibration techniques can be classified into three applying near-trip point reference voltages to the analog input
main groups, depending on whether the referred calibration and forcing the pre-ADC’s digital output to 1, 0, and -1.
steps are performed in the analog, digital, or mixed-signal These constants are saved and used for correction. Noise is
domains. suppressed by taking an average of various measurements.
Purely analog techniques (AA) are less attractive, since Two extra stages are added to reduce the quantization errors
they require high-accuracy analog components [14-17], such near the trip points of each stage. All digital circuits that
as a linear pulse-counting DAC [17], calibrating-DACs and conduct measuring and storing are implemented on an FPGA.
high-accuracy comparators [14-17]. In some cases, a reference The second technique employed by the ADC reported in
refreshing [18] or reference feed-forward [19] may be required [24] is the adaptive bias optimization. This optimization takes
to compensate the GE in the different MDACs, which
advantage of the digital calibration system to reduce the
complicates heavily the analog signal processing and the
dedicated analog circuitry to assist the calibration algorithms. dissipated power by approximately 20 to 30 %. The
Complex analog processing in prior works has limited the procedure for optimization is as follows (Fig. 1b): a bias
maximum operating speed; e.g. in [17] the speed was 5 MS/s. current is applied to each stage and the calibration constants
are measured. Each bias current is then adjusted iteratively
Since digital circuitry shrinks with the evolution of CMOS until the smallest calibration constants are achieved. The
technology, it is a good strategy to reduce analog circuit optimum bias point is reached when the constants stop
complexity at the expense of increased digital complexity. varying. The first four stages have individual adaptive bias
Hence, both purely digital and mixed-signal techniques have circuits, while stages 5 through 16 have a shared adaptive
been intensively investigated over the past years. bias circuit. The extra analog circuitry for each bias circuit,
This paper is organized as follows. In section II the most such as switches and resistors, is negligible. Furthermore, no
well known purely digital calibration techniques are described. sample-and-hold (S/H) circuit was used for extra power
Section III describes the few mixed-signal self-calibration savings.
techniques reported. Section IV shows, for the first time, a
practical example based on experimental silicon results, of an
efficient mixed-signal calibration technique in which, on-chip
thermal noise is used as the analog input stimulus. Finally,
section V draws the main conclusions and compares the
measured energy and area efficiencies among the different
calibration techniques.
II. PURELY DIGITAL SELF-CALIBRATION TECHNIQUES
Purely digital calibration techniques (DD) do not require
additional complex analog circuitry but they do require (a)
adding redundancy to the ADC by either adding additional
stages or stages with increased resolution. This extra
redundancy provides the required accuracy for the GE and LE
measurements and also overcomes the loss in effective
resolution produced by digital truncation errors during
calibration [20-32]. The “bit-weight digitisation” self-
calibration technique originally described in [20] and
improved in [21-25] only applies to single-bit first stages (i.
e. with 1.5-b per stage) and it requires extra pipeline stages
because at least 2 bits are lost due to extra redundancy for
calibration.
In [24] a 14-bit digitally self-calibrated pipelined ADC
(b)
featuring adaptive bias optimization for reduced power
dissipation is presented. This ADC employs two techniques Figure 1. (a) Nonideal pre-ADC transfer function and digital correction
method; (b) block diagram of the ADC showing adaptive bias controller and
that enhance its energy efficiency. Primarily, foreground the digital self-calibration circuit used in [24].
digital self-calibration is used to compensate for inter-stage
GE caused by finite amplifier gain and capacitor mismatch, Digital calibration of multi-bit stages has been proposed
and also compensates for DC offset in each stage. The in [27-29] (“code-weight digitisation”) but, again, at two or
calibration algorithm is similar to the one proposed in [20], more bits are lost due to digital truncations. Moreover, the
given that it recursively calibrates each stage from the least first MDACs have to be modified (by introducing many
significant to the most significant stage. Contrary to [20], additional switches to assist calibration) and inter-stage gain
here all stages are calibrated except the last one. The “distribution” techniques are necessary to overcome the
calibration constants, Qc, are measured by digitizing the effects of inter-stage gain errors (i. e., the different GEs of the
output of the pre-ADC using the post-ADC (Fig. 1a), while

3. pipelined stages are not calibrated and the have to be globally dithered (re)quantizers; average, gain and dump blocks; a 32-b
distributed over the full conversion range). counter; numerous adders and multipliers.
Although the technique described in [30] is demonstrated
in a 14-b ADC and reached good energy efficiency, it does
not allow calibration of the capacitor mismatches in the first
multi-bit MDAC, since only the finite DC gain and the gain
nonlinearity of the amplifier in this MDAC are corrected.
This technique allows good differential non-linearity (DNL)
characteristic and good spurious-free dynamic-range (SFDR)
but, in multi-sample statistical testing, the integral non-
linearity characteristic (INL), the total-harmonic distortion
(THD), the signal-to-noise plus distortion-ratio (SNDR) and
the ENOB will not be compatible with more than 10-to-10.5
bits (i. e., in a 3-sigma testing, the THD of some samples will
be bound to -68 to -71 dB, thus limiting the ENOB to about
10-to-10.5 bits).
The most energy efficient application of a DD technique in Figure 2. Illustrative block diagram of the HDC, DNC, and DEM
a self-calibrated ADC was recently reported in [31]. This work techniques used in the ADC described in [31].
presents a 14-b pipeline ADC which incorporates two fully
integrated digital techniques: harmonic distortion correction
(HDC) and DAC noise cancellation (DNC). HDC is used to III. MIXED-SIGNAL SELF-CALIBRATION TECHNIQUES
compensate for residue amplifier GE and nonlinearity, while Purely digital calibration techniques are becoming
DNC is used to compensate for DAC capacitor mismatches popular due to the scaling advantages in fine geometry
(LE). Both techniques operate in background. The HDC CMOS processes, which allow powerful digital algorithms to
correction algorithm implicitly assumes that the residue be incorporated, in a small area, in the same die as the ADC.
amplifier is the main source of nonlinearity of the circuit, thus However, as stated before, these algorithms are limited by
the ADC also employs dynamic element matching (DEM) to finite word length truncation errors and by the accuracy with
eliminate the DAC as a significant source of nonlinear which the errors are measured. They also require extra
distortion. The HDC technique consists of two portions of redundancy in the ADC circuit. Purely analog techniques, on
operation: estimation and correction. The estimation portion the other hand, require special analog circuits, but do not
consists of adding a known four-level calibration sequence to
require more ADC stages, since redundancy is not needed.
estimate the nonlinear distortion coefficients. These estimates
Hence, several mixed-signal techniques (AD) have been
are then used to compensate for the distortion. The ADC
consists of six stages, where the first three stages use the HDC proposed in order to combine the best of the two worlds. As
and DNC algorithms. The coefficient estimation process is suggested in [32] these AD techniques may be divided into
first implemented in stage 3, then stage 2, and finally in stage three different categories: A) channel error identification
1, where after the process is repeated. The DNC algorithm (CEI); B) correlation-based techniques (CB); C) digital-
estimates and cancels out the noise by the DEM DAC. domain correction using an accurate analog input (AAI).
Most of the enhancements required to implement HDC are In the CEI approach [33, 34] the error function is
digital, except that the DAC must be modified, in order not to constructed from the outputs of two different paths [32]. An
be the dominant source of nonlinearity. Therefore, the DACs additional slow, but accurate (inherently linear) reference
where implemented using DEM. The segmented DEM ADC, usually generates the desired response which acts as an
encoder is implemented with 2 layers of parallel transmission ideal reference for calibration. In [33, 34] Delta-Sigma
gates, combinatorial logic and a pseudo-random number Converters are normally used as the reference ADC. As
generator. Regarding other analog circuits, the opamp was stated in [32], the main disadvantage of this approach is its
implemented with very low gain (43 dB) and no S/H was high sensitivity to the gain and offset mismatching between
employed. channels, which requires an extra pre-calibration cycle.
Hence, as illustrated in Fig. 2, the conventional ADC A very complete survey of CB techniques has been
architecture employed has to be highly modified. Sixty-five presented in [32]. The most relevant ADCs employing CB are
level DACs (equivalent to 6-bit MDACs with a modified reported in [35-42]. With CB techniques a digital
residue amplification gain of 4 rather than the usual gain of
pseudorandom sequence (PRS) with zero mean and not
32) and nine-level DACs (equivalent to 3-bit MDACs) all
correlated with the input signal is injected at the input (“input
employing DEM have to be used in the first 3 stages and in
the remaining 2 back-end stages, respectively. Moreover, the modulation”) [35], at the local quantizer (“sub-ADC
local quantizers have also to be modified in order to provide 9 modulation”), at the MDAC (“MDAC modulation”) [38, 41],
levels of comparison for extra redundancy. Moreover, the or at a pipeline stage (“stage modulation”) [36, 42]. Hence,
digital implementation of the HDC technique is quite building-blocks of the pipeline ADC have to be modified to
complex, as it implements the following digital circuitry: allow introduction of this sequence. Moreover, the signal

4. range is normally reduced (to accommodate the dither signal demonstrated in a 10-bit 10 MS/s ADC and the improvement
added) and a few bits (two or even more) are normally lost by in the INL is significant. In [44] and in [45] a set of discrete
digital truncation. DC values (256 and 128, respectively) are provided as the
AAI, produced by an auxiliary SC DAC circuit. However, in
In [42] an AD, CB background calibration scheme, is
[45], the reached ENOB is below 11 bits.
presented to compensate for the GE and LE in the first two
An AD AAI queue based calibration applied to a pipeline
high accuracy stages of a 14-bit pipelined ADC. The block
ADC is proposed in [44]. To allow background calibration
diagram of the calibration scheme proposed in [42]
using a queue composed of only one S/H requires that the
(exemplified only for the first pipeline stage of the ADC) is
clock of the ADC (fc) is, at least, one and a half times larger
shown in Fig. 3, and it is described as follows. The PRS is
than the clock of the input S/H (fs). The samples from an
generated digitally and applied to the summing node of the
accurate (more than the overall resolution of the ADC)
MDAC by means of a DAC sub-converter (DASCcal).
calibration signal (Vcal) are used to calibrate the gain and
Additionally, this PRS is multiplied in the digital domain by
slew-rate limiting errors of the ADC. The architecture allows
an estimated gain (Gd) and subtracted from the digital word
Vin and Vcal to be quantized separately, which reduces the
generated by the backend ADC, which comprises the
calibration convergence time since the input does not have to
remaining pipelined stages. The resulting signal is correlated
averaged out during calibration. Besides a Vcal generator and
with the PRS sequence and the correlation output (err) is
a multiplexer (MUX), the calibration algorithm requires a
used to tune the estimated digital gain. When the signal “err”
radix converter, a calibration engine (custom
converges to zero, the gain Gd and inter-stage gain of the
microprocessor), and a random-access memory (RAM),
amplifier (Ga) are matched, and hence, the GE of the stage is
which inevitably leads to large hardware overhead.
estimated. The DASCcal is efficiently implemented with an
additional calibration capacitor, and associated switches, in
the already present DASC1, thus minimizing hardware
overhead. The DASC1 error caused by the capacitors
mismatch errors is calculated according to the individual
DAC weight estimate of the capacitors comprising DASC1,
including the calibration capacitor. Since each capacitor is
evaluated at a time using the same circuitry employed for GE
estimation, an additional capacitor selecting multiplexer (not
shown in Fig. 3) precedes the DASC1. The difference in the
calculated Gd values of every capacitor is an estimate of the
DAC error [42].
To decrease the power dissipation, and, therefore, to Figure 4. Simplified diagram of queue based calibration used in [44].
enhance the energy efficiency, the work in [42] removes the
power hungry front-end S/H. To avoid the drawbacks
IV. A MIXED-SIGNAL CALIBRATION TECHNIQUE USING
associated with this option, a charge compensation circuitry,
THERMAL NOISE AS THE ANALOG INPUT STIMULUS
composed simply of an additional dummy capacitor, is used.
A robust mixed-signal AAI self-calibration technique is
described here, in which a multi-bit first stage in the ADC
can be calibrated without any modifications in the stage, as
long as the ideal conversion characteristic is known. Four
requirements have been set: 1) ADC should not be internally
modified; 2) An energy efficiency better than 0.5 pJ/conv.-
step (including reference buffers); 3) simple digital-domain
correction algorithm without multipliers; 4) pure logic 90nm
CMOS process and small silicon area (for low-cost). This
work demonstrates, experimentally, a histogram-based
calibration technique conceptually described in [46], for
CMOS pipeline ADCs using thermal (Gaussian) noise as the
calibrating input.
Figure 3. Simplified block diagram of the AD-CB calibration used in [42]. A. ADC Architecture
Fig. 5 shows how the 13-bit pipeline ADC is associated to
A few AD AAI techniques have recently been reported [43- a Gaussian Noise Generator (GNG) and a 16-bit sub-binary
46]. They have in common that, besides an input analog programmable-gain amplifier (PGA). For flexibility in
multiplexer for input selection, no modifications are required testing, an FPGA implements the calibration algorithm. The
in the ADC under calibration. In [43] an on-chip ramp 13-bit ADC employs a front-end S/H, using 2 sampling
generator is proposed as the AAI stimulus. The technique is capacitors with CS = 10 pF, followed by a first 3.5-bit pipeline

5. stage with a 3.5-bit MDAC comprising 14 unit-capacitors stages rely on NMOS differential-pairs loaded by PMOS
with, CU = 1.4 pF and by a 1.5-bit/stage 10-bit backend cascoded current sources, followed by two enhanced voltage-
pipeline ADC. The 14 output bits are digitally synchronized, followers (EVFs) that efficiently drive the PGA. The thermal
and 13 bits are available after digital correction. With this noise of the large input resistors (Rn) is amplified with a gain
architecture, the ADC’s overall GE and LE are limited equal to R2/R1. To remove accumulated offset and 1/f noise,
mainly by the mismatches in the 3.5-bit first stage. the 3-stages are AC coupled through Cd and Rd. Dedicated
active continuous-time CMFB circuits are used in each
amplifying stage. Optimum nested-Miller compensation
guarantees that over 99% of the output referred noise is
generated by resistors Rn. The GNG block consumes 5.8 mA
in typical conditions (2 mA is drawn by the two EVFs) but
this block is powered-down after the calibration is concluded.
Since the noise standard-deviation (σ ≅42 mV) is process-
supply and temperature (PVT) dependent, a SC 16-bit sub-
binary PGA adjusts the σ to half the differential reference
voltage (≅250 mV) with 10-bit accuracy.
C. Calibration Algorithm
The calibration algorithm consists of 3 main steps:
Figure 5. Block diagram of the self-calibrated ADC.
i) The first step is used to determine the offset of the
The resolution per stage in the ADC was carefully noise source and of the ADC: in offset-measurement mode (A
tailored by using an optimization methodology, in order to switches in Fig. 5 are ON), the inputs are zeroed and 32 input
meet the best trade-off between ADC’s thermal noise, power samples are digitized and averaged; the averaged value is
dissipation, calibration requirements and die area. This then used in the subsequent calibration steps as the offset of
methodology provided optimized capacitance values as well the ADC.
as main specifications for the active building blocks in the
pipeline stages (opamps and comparators). All opamps are ii) The second step is used to calibrate the amplitude
efficiently shared across adjacent stages and were optimized (σ) of the noise signal: in configuration-mode B (B switches
in the time-domain. The resolution of 13 bits was adopted to ON), the GNG noise is applied to the ADC through the PGA
set the input referred quantization noise at 35.2 μVrms, and the number of occurrences in the code bin intervals
assuming a full-scale (FS) differential signal of 1 Vp-p. {89 , 90 ,… , 600} and {7592 , 7593 ,… ,8103} , for a total of 226
input samples are measured. These two symmetrical bins with
a width of 511 codes are located in the outermost segments of
the conversion characteristic and, they are only affected by
the GE of the first stage of the ADC. The accumulated
number of occurrences provides an estimation of the σ of the
−+ −+ −+ noise source. The minimum number of samples required to
+ − + − + −
obtain a good estimative of σ was determined through a high-
level C++ model of the entire calibration system. Depending
on the estimated value of σ being higher or lower than the
desired value the PGA gain is either increased or decreased
through the SAA. This process can be repeated up to 16 times
(it stops whenever σ reaches the desired value) determining
the gain setting for the PGA (defined by a 16 bit word); at the
end of the second step, the value of σ is adjusted to the
desired value with a precision of 10 bits.
iii) The third step is used to determine the GE and the
LE of the first stage: Still in mode B, the ADC is stimulated
with the GNG, as before, through the PGA programmed with
Figure 6. New on-chip Gaussian noise generator (biasing and CMFB the previously determined gain, and the calibrating codes are
circuitry not shown). extracted from the output histogram, to calibrate the GE and
LEs of the ADC. In this third step, since there are only 14
B. Analog Building Blocks Required to Assist the Mixed- possible transitions in the first 3.5-bit stage, only 14 bins (Nb
Signal Calibration Algorithm = 14) are considered, defined around 14 code transitions
The proposed new GNG circuit (Fig. 6) consists of a 3- equally spaced and centred in codes Cbin(k) = 767 + k ⋅ 512 (k
stage nested-Miller compensated OTA, where the first two = 0…13). To avoid losing a transition due to the random

6. offsets in threshold voltages of the comparators, a large bin- only 48.5 mW and 38.2 mW, respectively, for the 1.2 V and
width, Bw = 64 codes, is used. A Gaussian shaped histogram 1.0 V power supplies (the power of the GNG and of the PGA
H(i) is obtained (“measured”), which has deviations D(i) are not included since both blocks are powered-down after
from the ideal one due to the GE and LEs in the 3.5-bit stage. the calibration is completed). A peak FOM better than 0.41
For a large number of samples, NS = 230 in our case D(i) is: pJ/conv.-step was reached at 40 MS/s with a single supply
voltage of 1.0 V (a measured ENOB of 11.2 bits was
D(i) = [H(i) P-1(i) - NS ].Bw/NS (2)
achieved after calibration).
where P(i), stored in a ROM with 14 positions, is the
truncated probability (an accuracy of four digits was used for
16-bit precision) of the bins in the ideal histogram obtained
from a Gaussian distribution function with σ = 4096 LSB and
σ = 2048 LSB according to
− ( x − μ )2
(σ ⋅ )
Cbin ( i )+ Bw 2 −1 Bandgap and Ref. Buffers
2σ 2
P(i) = ∫ 2π e dx (3)
Cbin ( i )− Bw 2 10-bit BE ADC
10- 3.5-bit FE Stage
3.5-
The 14 values of D(i) are used to calculate the deviations 16-bit
16- S/H
from the ideal transfer characteristic and the 15 calibrating GNG PGA
codes. By exploring symmetry of the first pipeline stage
characteristic, the 14+1 calibrating codes (since, calcode(1)
results from the sum of the 14 values of D(i)) are obtained as
follows:
calcode(1) = −GE = −0.5 ⋅ ∑7=1 [D (i) + D(16 − i)]
i
calcode(i) = calcode(i − 1) + 0.5 ⋅ [D(i − 1) + D (17 − i)], 2 ≤ i ≤ 7 (4) Figure 7. Die photo of the test chip.
calcode(i) = −calcode(16 − i ), 9 ≤ i ≤ 15; calcode(8) = 0. 0
-10
The resulting calibrating codes are stored in a memory, which 16,384 points FFT
(16 averages)
fIN = 10.105 MHz
AIN = −0.5 dBFS
during normal conversion mode (C switches ON) is -20
Coherent sampling SNR = 69.37 dB
SFDR = 69.88 dB
addressed by the 4-bit output of the first 3.5-bit quantizer, and -30
THD = −69.57 dB
the 15 output calibrating codes are added to the un-calibrated -40 SNDR = 66.45 dB
ENOB = 10.7 bits
AMPLITUDE (dB)
13-bit output. Digital multipliers are not explicitly required -50
since only addition, subtraction, multiplication by constants -60
and division by powers of two are used. -70
-80
D. Integrated Prototype and Measured Results -90
An ADC prototype IC (micrograph shown in Fig. 7) was -100
fabricated in a 90 nm 1P 8M CMOS logic process. As stated -110
before, for flexibility testing purposes, the digital calibration 0 5 10 15 20
circuitry has been completely implemented using a Virtex-5 ANALOG INPUT FREQUENCY (MHz) (a)
FPGA. Notice that the FPGA was required to operate, at 0
least, at 40 MHz to enable real time (on the fly) silicon -10
16,384 points FFT
verification in conjunction with the ADC chip. Since the -20
(16 averages)
fIN = 10.105 MHz
AIN = −0.5 dBFS
digital circuitry is relatively small, one of the smallest FPGAs Coherent sampling SNR = 69.91 dB
-30 SFDR = 84.03 dB
of this family (e.g., a Virtex 2) could have been used. The THD = −80.0 dB
-40 SNDR = 69.50 dB
hardware synthesis has also been performed for a Xilinx ENOB = 11.25 bits
AMPLITUDE (dB)
Spartan 3 FPGA, but it was not able to meet the 40 MHz -50
speed-of-operation requirement. The estimated gate count of -60
the complete digital calibration circuitry in a future -70
implementation using standard cells is below 2,000 gates. -80
-90
Figure 8 displays a measured FFT for a 10 MHz input -100
signal frequency (fin) and 40 MS/s sampling frequency (FS) -110
before and after calibration for a worst-case chip sample (i. e.,
0 5 10 15 20
in which the performance before calibration is worse and ANALOG INPUT FREQUENCY (MHz) (b)
where the benefits from the calibration are more perceptible).
Figure 8. Measured FFT results for fin = 10 MHz (@-0.5 dBFS) and FS = 40
The IC occupies an active area as small as 0.88 mm2 (all MS/s before calibration (a) and after calibration (b).
included except the I/O PAD ring) and dissipates, at 40 MS/s,

7. V. CONCLUSIONS is about two times higher than the most energy efficient self-
Table I summarizes a comparison of FOM of high- calibrated ADCs reported and highlighted in Table I.
resolution pipeline ADCs with: FS ≥ 5 MS/s and The mixed-signal technique described in this paper, in
which thermal noise is used as the input analog stimulus, the
ENOB ≥ 11 bits , reported in the literature (J-SSC, T-INST. AND uniform power spectral density of the noise allows full-speed
MEAS., T-CAS I AND II, ISSCC, VLSI, CICC, ESSCIRC and dynamic calibration [46], and the use of a histogram
ASSCC) over the past 20 years. As it can be observed, the eliminates uncertainties of the calibrating-codes due to noise
most energy and area efficient ADCs employ either DD [24, [47]. Moreover, since the AAI is not periodic (like a ramp or
30, 31] or AD-AAI [42] self-calibration techniques. a sine-wave), there is no need for a circular sampling and, the
However, all of them have advantages and drawbacks. The histogram test is still sensitive to both static and dynamic
works reported in [24], [30] and the AD-AAI technique errors of the ADC within the frequency range of the noise
described in this paper reach, simultaneously, good area and source. However, since it operates only in foreground mode,
good energy efficiencies but, they are only able to operate in it is only suited for a limited number of applications.
foreground mode. Moreover, in [30], the DAC capacitors’
mismatch errors are not calibrated. The work described in ACKNOWLEDGMENT
[31] has good energy efficiency but the die area is relatively The authors would like to thank Dr. Boris Glass (from
larger than the other approaches, although all digital circuitry ESTEC-ESA) for his helpful feedback during the design and
to assist the calibration algorithm is included on-chip. experimental evaluation of the ADC, Mr. Nuno Penetra for
However, this technique is able to run either in background or layout work, Mr. Erik Snelling for the testing results and, Prof.
in foreground mode. The AD-CB calibration technique M. Medeiros Silva for the many suggestions that improved the
reported in [42] also works in background mode and it quality of this paper.
exhibits good area efficiency. However, the power dissipation
TABLE I: COMPARISON OF FOM IN THE MOST RELEVANT HIGH-RESOLUTION PIPELINE ADCS, WITH FS ≥ 5MS/S AND ENOB ≥ 11
BITS. (FOUND IN J-SSC, T-INST. AND MEAS., T-CAS I AND II, ISSCC, VLSI, CICC, ESSCIRC AND ASSCC OVER THE PAST 20 YEARS).
Ref. N FS Tech. Calibration used? Power Area SNR SFDR THD ENOB FOM
(bit) (MS/s) (μm) No/Type (if Yes) (mW) (mm2) (dB) (dB) (dB) (bits) (pJ)
if ≥ 5 if ≥ 11
[6] 14 20 0.5 No, active CEA 720 @5V 10.8 75.5 90.1 -86.3 12.2 7.6
[10] 14 12 0.18 No, passive, CEA 98 @1.8V 10 75.5 101 -94.5 12.3 1.6
[17] 14 5 0.6 AA 100 @5V 10 10 80 -78 12.5 3.4
[24] 15 5 1.4 DD 95 @5V 27 86.9 93 -87 13.8 1.3
[23] 14 30 0.09 DD 106 @3.3 0.75 - 83.7 - 11.2 1.5
[24] 14 10 0.18 DD 19.2 @2.8V 1.15§ 73.7 - -76 11.6 0.61
[25] 16 10 0.065 DD 79.2 @3.3V 1.32 75.8 90.5 - 12.2 1.68
[26] 15 30 0.25 DD, but capacitor 123 @2.5V 6.4 - 87 - 12.2 0.87
matching > 12 bits
[30] 14 100 0.09 DD, but capacitor 250 @1.2 1¥ 73 90 -82 11.8 0.68
matching > 12 bits
[31] 14 100 0.09 DD 130 @1.2 4 70 86 -85 11.3 0.52
[36] 15 40 0.18 AD-CB 400 @1.8V 20 72 90 -88 11.6 3.2
[38] 15 40 0.25 AD-CB 370 @2.5V 13.7 74 93.3 - 11.9 2.4
[39] 15 50 0.25 AD-CB 780 @2.5V 5.55§ 75 96 - 12.0 3.8
[40] 15 125 0.18 AD-CB 909 @1.8V 18.5 70 91.9 - 11.3 2.9
[41] 12 20 0.18 AD-CB 285 @1.8V 3.91 73 98 -92 11.8 4.0
[42] 14 100 0.13 AD-CB 224 @1.5V 1.02§ 70 - -79.1 11.0 1.12
[44] 12 80 0.25 AD-AAI 755 @2.5V 22.6 - 79.6 - 11.8 2.65
[This work
@1.2V] 13 40 0.09 AD-AAI 48.5 @1.2V 0.88§ 70.2 84.4 -80.6 11.3 0.48
[This work
@1.0V] 13 40 0.09 AD-AAI 38.2@1.0V(*) 0.88§ 70.2 80.3 -77.3 11.2 0.41
§
- Digital circuitry to assist self-calibration is off-chip.
¥
- Digital circuitry to assist self-calibration is on-chip but not included in the shown area figure (ADC core only).
(*)
– Measurements done with all supply voltages (VDDA, VDDM and VDDD) reduced from 1.2V down to 1.0V.
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