DPDK Summit - 08 Sept 2014 - Intel - Networking Workloads on Intel ArchitectureJim St. Leger
Venky Venkatesan presents information on the Data Plane Development Kit (DPDK) including an overview, background, methodology, and future direction and developments.
This document provides an introduction to the Intel Data Plane Development Kit (DPDK) and discusses:
- DPDK addresses the challenges of high-speed packet processing on Intel architectures by eliminating kernel and interrupt overheads through a userspace polling model.
- DPDK is open source under a BSD license, allowing free use and modification of the code.
- DPDK optimizes packet processing performance through techniques like huge pages, prefetching, and affinity of threads to CPU cores.
Evolving Cyberinfrastructure, Democratizing Data, and Scaling AI to Catalyze ...inside-BigData.com
In this deck from the Stanford HPC Conference, Nick Nystrom and Paola Buitrago provide an update from the Pittsburgh Supercomputing Center.
Nick Nystrom is Chief Scientist at the Pittsburgh Supercomputing Center (PSC). Nick is architect and PI for Bridges, PSC's flagship system that successfully pioneered the convergence of HPC, AI, and Big Data. He is also PI for the NIH Human Biomolecular Atlas Program’s HIVE Infrastructure Component and co-PI for projects that bring emerging AI technologies to research (Open Compass), apply machine learning to biomedical data for breast and lung cancer (Big Data for Better Health), and identify causal relationships in biomedical big data (the Center for Causal Discovery, an NIH Big Data to Knowledge Center of Excellence). His current research interests include hardware and software architecture, applications of machine learning to multimodal data (particularly for the life sciences) and to enhance simulation, and graph analytics.
Watch the video: https://youtu.be/LWEU1L1o7yY
Learn more: https://www.psc.edu/
and
http://www.hpcadvisorycouncil.com/events/2020/stanford-workshop/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
The document discusses how DDN A3I storage solutions and Nvidia's SuperPOD platform can enable HPC at scale. It provides details on DDN's A3I appliances that are optimized for AI and deep learning workloads and validated for Nvidia's DGX-2 SuperPOD reference architecture. The solutions are said to deliver the fastest performance, effortless scaling, reliability and flexibility for data-intensive workloads.
Versal Premium ACAP for Network and Cloud Accelerationinside-BigData.com
Today Xilinx announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry’s highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.
Versal is the industry’s first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC’s 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to- market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.
Learn more: https://insidehpc.com/2020/03/xilinx-announces-versal-premium-acap-for-network-and-cloud-acceleration/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Ligato - A platform for development of Cloud-Native VNF's - SDN/NFV London me...Haidee McMahon
1. The document discusses the need for cloud-native network functions (CNFs) and proposes a platform called Ligato to develop CNFs.
2. Ligato provides lifecycle management, high-performance networking and forwarding, and easy installation and operation for container-based CNFs.
3. It describes how Ligato enables service function chaining by orchestrating CNFs and uses containers, VPP, and overlays for high performance networking between CNFs.
DPDK Summit 2015 - Intro - Tim O'DriscollJim St. Leger
DPDK Summit 2015 in San Francisco.
Introductory comments and kick-off by Tim O'Driscoll, Intel.
For additional details and the video recording please visit www.dpdksummit.com.
DPDK Summit - 08 Sept 2014 - Intel - Networking Workloads on Intel ArchitectureJim St. Leger
Venky Venkatesan presents information on the Data Plane Development Kit (DPDK) including an overview, background, methodology, and future direction and developments.
This document provides an introduction to the Intel Data Plane Development Kit (DPDK) and discusses:
- DPDK addresses the challenges of high-speed packet processing on Intel architectures by eliminating kernel and interrupt overheads through a userspace polling model.
- DPDK is open source under a BSD license, allowing free use and modification of the code.
- DPDK optimizes packet processing performance through techniques like huge pages, prefetching, and affinity of threads to CPU cores.
Evolving Cyberinfrastructure, Democratizing Data, and Scaling AI to Catalyze ...inside-BigData.com
In this deck from the Stanford HPC Conference, Nick Nystrom and Paola Buitrago provide an update from the Pittsburgh Supercomputing Center.
Nick Nystrom is Chief Scientist at the Pittsburgh Supercomputing Center (PSC). Nick is architect and PI for Bridges, PSC's flagship system that successfully pioneered the convergence of HPC, AI, and Big Data. He is also PI for the NIH Human Biomolecular Atlas Program’s HIVE Infrastructure Component and co-PI for projects that bring emerging AI technologies to research (Open Compass), apply machine learning to biomedical data for breast and lung cancer (Big Data for Better Health), and identify causal relationships in biomedical big data (the Center for Causal Discovery, an NIH Big Data to Knowledge Center of Excellence). His current research interests include hardware and software architecture, applications of machine learning to multimodal data (particularly for the life sciences) and to enhance simulation, and graph analytics.
Watch the video: https://youtu.be/LWEU1L1o7yY
Learn more: https://www.psc.edu/
and
http://www.hpcadvisorycouncil.com/events/2020/stanford-workshop/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
The document discusses how DDN A3I storage solutions and Nvidia's SuperPOD platform can enable HPC at scale. It provides details on DDN's A3I appliances that are optimized for AI and deep learning workloads and validated for Nvidia's DGX-2 SuperPOD reference architecture. The solutions are said to deliver the fastest performance, effortless scaling, reliability and flexibility for data-intensive workloads.
Versal Premium ACAP for Network and Cloud Accelerationinside-BigData.com
Today Xilinx announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry’s highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.
Versal is the industry’s first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC’s 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to- market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.
Learn more: https://insidehpc.com/2020/03/xilinx-announces-versal-premium-acap-for-network-and-cloud-acceleration/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Ligato - A platform for development of Cloud-Native VNF's - SDN/NFV London me...Haidee McMahon
1. The document discusses the need for cloud-native network functions (CNFs) and proposes a platform called Ligato to develop CNFs.
2. Ligato provides lifecycle management, high-performance networking and forwarding, and easy installation and operation for container-based CNFs.
3. It describes how Ligato enables service function chaining by orchestrating CNFs and uses containers, VPP, and overlays for high performance networking between CNFs.
DPDK Summit 2015 - Intro - Tim O'DriscollJim St. Leger
DPDK Summit 2015 in San Francisco.
Introductory comments and kick-off by Tim O'Driscoll, Intel.
For additional details and the video recording please visit www.dpdksummit.com.
InfiniBand In-Network Computing Technology and Roadmapinside-BigData.com
In this video from the UK HPC Conference, Richard Graham from Mellanox presents: InfiniBand In-Network Computing Technology and Roadmap.
"In-Network Computing transforms the data center interconnect to become a "distributed CPU", and "distributed memory", enables to overcome performance barriers and to enable faster and more scalable data analysis. HDR 200G InfiniBand In-Network Computing technology includes several elements - Scalable Hierarchical Aggregation and Reduction Protocol (SHARP), smart Tag Matching and rendezvoused protocol, and more. These technologies are in use at some of the recent large scale supercomputers around the world, including the top TOP500 platforms. The session will discuss the InfiniBand In-Network Computing technology and performance results, as well as view to future roadmap."
Watch the video:
Learn more: http://mellanox.com
and
http://hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Preparing to program Aurora at Exascale - Early experiences and future direct...inside-BigData.com
In this deck from IWOCL / SYCLcon 2020, Hal Finkel from Argonne National Laboratory presents: Preparing to program Aurora at Exascale - Early experiences and future directions.
"Argonne National Laboratory’s Leadership Computing Facility will be home to Aurora, our first exascale supercomputer. Aurora promises to take scientific computing to a whole new level, and scientists and engineers from many different fields will take advantage of Aurora’s unprecedented computational capabilities to push the boundaries of human knowledge. In addition, Aurora’s support for advanced machine-learning and big-data computations will enable scientific workflows incorporating these techniques along with traditional HPC algorithms. Programming the state-of-the-art hardware in Aurora will be accomplished using state-of-the-art programming models. Some of these models, such as OpenMP, are long-established in the HPC ecosystem. Other models, such as Intel’s oneAPI, based on SYCL, are relatively-new models constructed with the benefit of significant experience. Many applications will not use these models directly, but rather, will use C++ abstraction libraries such as Kokkos or RAJA. Python will also be a common entry point to high-performance capabilities. As we look toward the future, features in the C++ standard itself will become increasingly relevant for accessing the extreme parallelism of exascale platforms.
This presentation will summarize the experiences of our team as we prepare for Aurora, exploring how to port applications to Aurora’s architecture and programming models, and distilling the challenges and best practices we’ve developed to date. oneAPI/SYCL and OpenMP are both critical models in these efforts, and while the ecosystem for Aurora has yet to mature, we’ve already had a great deal of success. Importantly, we are not passive recipients of programming models developed by others. Our team works not only with vendor-provided compilers and tools, but also develops improved open-source LLVM-based technologies that feed both open-source and vendor-provided capabilities. In addition, we actively participate in the standardization of OpenMP, SYCL, and C++. To conclude, I’ll share our thoughts on how these models can best develop in the future to support exascale-class systems."
Watch the video: https://wp.me/p3RLHQ-lPT
Learn more: https://www.iwocl.org/iwocl-2020/conference-program/
and
https://www.anl.gov/topic/aurora
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Building efficient 5G NR base stations with Intel® Xeon® Scalable Processors Michelle Holley
Speaker: Daniel Towner, System Architect for Wireless Access, Intel Corporation
5G brings many new capabilities over 4G including higher bandwidths, lower latencies, and more efficient use of radio spectrum. However, these improvements require a large increase in computing power in the base station. Fortunately the Xeon Scalable Processor series (Skylake-SP) recently introduced by Intel has a new high-performance instruction set called Intel® Advanced Vector Extensions 512 (Intel® AVX-512) which is capable of delivering the compute needed to support the exciting new world of 5G.
In his talk Daniel will give an overview of the new capabilities of the Intel AVX-512 instruction set and show why they are so beneficial to supporting 5G efficiently. The most obvious difference is that Intel AVX-512 has double the compute performance of previous generations of instruction sets. Perhaps surprisingly though it is the addition of brand new instructions that can make the biggest improvements. The new instructions mean that software algorithms can become more efficient, thereby enabling even more effective use of the improvements in computing performance and leading to very high performance 5G NR software implementations.
What are latest new features that DPDK brings into 2018?Michelle Holley
We will provide an overview of the new features of the latest DPDK release including source code browsing and API listing of top two new features of latest DPDK release. And on top of that, there will be a hands-on lab, on the Intel® microarchitecture servers, to learn how getting started with DPDK will become much simpler and powerful.
Vector Packet Technologies such as DPDK and FD.io/VPP revolutionized software packet processing initially for discrete appliances and then for NFV use cases. Container based VNF deployments and it's supporting NFV infrastructure is now the new frontier in packet processing and has number of strong advocates among both traditional Comms Service Providers and in the Cloud. This presentation will give an overview of how DPDK and FD.io/VPP project are rising to meet the challenges of the Container dataplane. The discussion will provide an overview of the challenges, recent new features and what is coming soon in this exciting new area for the software dataplane, in both DPDK and FD.io/VPP!
About the speaker: Ray Kinsella has been working on Linux and various other open source technologies for about twenty years. He is recently active in open source communities such as VPP and DPDK but is a constant lurker in many others. He is interested in the software dataplane and optimization, virtualization, operating system design and implementation, communications and networking.
Intel® QuickAssist Technology Introduction, Applications, and Lab, Including ...Michelle Holley
Abstract: Intel® QuickAssist Technology improves performance and efficiency across the data center and other computing platforms by handling the compute-intensive operations of bulk cryptography, public key cryptography, and data compression. In this course, we will give an overview of the technology along with the summary of resources to get started with integrating Intel® QAT into your platform solutions. We will also demonstrate using Intel® QAT with applications such as OpenSSL, NGINX, and HAProxy, with a hands-on lab.
Speaker Bios:
Joel Auernheimer, a Platform Application Engineer at Intel, has been focused on enabling customers to integrate Intel® QuickAssist Technology in their platform solutions. Joel is a native of Phoenix, Arizona and enjoys hiking, basketball, soccer, singing, and spending time with friends and family.
Joel Schuetze has been with Intel since 1996. For the last 9+ years he has worked as Platform Application Engineer supporting customers with Intel QuickAssist Technology.
Development, test, and characterization of MEC platforms with Teranium and Dr...Michelle Holley
Mobile edge computing delivers cloud computing at the edge of the cellular network to drive services quality and innovation. The ability for CSPs and ISVs to effectively develop, deliver, and deploy MEC services on a given platform directly correlates with the availability and maturity of associated tools and test environment. Dronava is a hyper-connected, web-scale network reference design for the 5G mobile network, suitable for use as a test and development socket for cloud applications developed for MEC platforms with tools such as the Intel NEV SDK. With Dronava, developers can drive the application with real traffics from the network edge to the EPC core, and if need be, connect with services in the core network in order to fully characterize the functionalities, latency, and throughput of the platform and application.Teranium is an integrated development environment that simplifies the development, packaging, and deployment/management of cloud applications. Teranium can be utilized to develop and deploy MEC applications on a number of platforms. Together with Dronava, Teranium helps to reduce complexity and improve efficiency in the ability of CSPs and ISVs to adopt and deploy MEC-base services.
Mellanox is a supplier of interconnect solutions headquartered in Israel with worldwide offices and over 2,700 employees. It provides adapters, switches, cables, and transceivers for high-speed InfiniBand and Ethernet connectivity. Mellanox's solutions accelerate high performance computing and artificial intelligence workloads through technologies like GPUDirect, RDMA, and in-network computing capabilities. Mellanox's products are used to build several of the world's fastest supercomputers and its technologies help unlock the power of artificial intelligence for leading companies.
State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA CampFPGA Central
The panelists discussed their views on the current state and future of FPGAs. Mark expressed concerns about soft error rates and power densities in high-end FPGAs. Gordon said the industry is healthy but the race to more logic cells has pushed single architectures. Daniel said the line between FPGAs and ASICs is blurring and more niche and application-specific solutions will emerge. Chris said higher-level design flows will be needed to meet complexity demands. Umar viewed FPGAs as programmable processing engines well-suited for product architecture risk.
Enabling new protocol processing with DPDK using Dynamic Device PersonalizationMichelle Holley
The document provides a legal disclaimer for information presented about Intel products. It states that no license is granted to any intellectual property and Intel assumes no liability for products or fitness for particular purposes. Product specifications and descriptions are subject to change without notice. The document contains a copyright notice for Intel Corporation.
SCFE 2020 OpenCAPI presentation as part of OpenPWOER TutorialGanesan Narayanasamy
This document introduces hardware acceleration using FPGAs with OpenCAPI. It discusses how classic FPGA acceleration has issues like slow CPU-managed memory access and lack of data coherency. OpenCAPI allows FPGAs to directly access host memory, providing faster memory access and data coherency. It also introduces the OC-Accel framework that allows programming FPGAs using C/C++ instead of HDL languages, addressing issues like long development times. Example applications demonstrated significant performance improvements using this approach over CPU-only or classic FPGA acceleration methods.
Xilinx provides adaptable acceleration platforms for data centers. Their Alveo product lineup includes the U280, U250, U200, and low-profile U50 accelerator cards. The cards feature FPGAs with up to 1.3 million logic cells and high-speed memory. Xilinx also offers the U25 SmartNIC which combines an FPGA, ARM CPU, and dual 25GbE ports. These platforms accelerate workloads such as AI, databases, storage, and networking using reconfigurable and adaptable hardware. Xilinx supports deployment from their devices to cloud platforms using a unified software stack.
Intel développe une "ONP" (Open Network Platform) dit autrement un switch ouvert offrant les fonctions de base nécessaires au SDN. Si vous souhaitez connaitre le matériel utilisé, les stack logicielle exploitée et les compatibilité avec notamment les orchestrateurs, ce doc est fait pour vous.
In this deck from ATPESC 2019, James Moawad and Greg Nash from Intel present: FPGAs and Machine Learning.
"Neural networks are inspired by biological systems, in particular the human brain. Through the combination of powerful computing resources and novel architectures for neurons, neural networks have achieved state-of-the-art results in many domains such as computer vision and machine translation. FPGAs are a natural choice for implementing neural networks as they can handle different algorithms in computing, logic, and memory resources in the same device. Faster performance comparing to competitive implementations as the user can hardcore operations into the hardware. Software developers can use the OpenCL device C level programming standard to target FPGAs as accelerators to standard CPUs without having to deal with hardware level design."
Watch the video: https://wp.me/p3RLHQ-lnc
Learn more: https://extremecomputingtraining.anl.gov/archive/atpesc-2019/agenda-2019/
and
https://www.intel.com/content/www/us/en/products/programmable/fpga.html
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In the design of electronics and semiconductors, challenges are compounded by the integration of AI, multi-core, real-time software, network, connectivity, diagnostics, and security. Performance limits, battery life, and cost are adoption barriers. It is extremely important to have tools and processes that deliver efficiency throughout the design cycle.
Continuous verification from planning to development addresses the multi-discipline needs of hardware, software, and networks. This unique approach accelerates the design phase, defines the test efforts, and finds defects during specification. Architecture modeling is required to meet timing deadlines, generate the lowest power consumption, and attain the highest Quality-of-Service. optimize the electronic design system and designing of custom components.
Closed Loop Network Automation for Optimal Resource Allocation via Reinforcem...Liz Warner
In this talk, we present a closed-loop automation approach to dynamically adjust LLC cache allocation (Intel RDT) between high priority VNFs and BE workloads using reinforcement learning. The results demonstrated improved server utilization while maintaining required service level agreement for high priority VNFs.
Closed Loop Platform Automation - Tong Zhong & Emma CollinsLiz Warner
Closed-loop automation would dramatically help with the network transformation which is central to our business. Building a general analytics workflow to support various use cases (such as power management, fault prediction, networking slicing, etc.) is a critical component in the overall platform.
In this deck, Paul Isaacs from Linaro presents: State of ARM-based HPC. This talk provides an overview of applications and infrastructure services successfully ported to Aarch64 and benefiting from scale.
"With its debut on the TOP500, the 125,000-core Astra supercomputer at New Mexico’s Sandia Labs uses Cavium ThunderX2 chips to mark Arm’s entry into the petascale world. In Japan, the Fujitsu A64FX Arm-based CPU in the pending Fugaku supercomputer has been optimized to achieve high-level, real-world application performance, anticipating up to one hundred times the application execution performance of the K computer. K was the first computer to top 10 petaflops in 2011."
Watch the video: https://wp.me/p3RLHQ-lIT
Learn more: https://www.linaro.org/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Google and Intel speak on NFV and SFC service delivery
The slides are as presented at the meet up "Out of Box Network Developers" sponsored by Intel Networking Developer Zone
Here is the Agenda of the slides:
How DPDK, RDT and gRPC fit into SDI/SDN, NFV and OpenStack
Key Platform Requirements for SDI
SDI Platform Ingredients: DPDK, IntelⓇRDT
gRPC Service Framework
IntelⓇ RDT and gRPC service framework
Optimized HPC/AI cloud with OpenStack acceleration service and composable har...Shuquan Huang
Today data scientist is turning to cloud for AI and HPC workloads. However, AI/HPC applications require high computational throughput where generic cloud resources would not suffice. There is a strong demand for OpenStack to support hardware accelerated devices in a dynamic model.
In this session, we will introduce OpenStack Acceleration Service – Cyborg, which provides a management framework for accelerator devices (e.g. FPGA, GPU, NVMe SSD). We will also discuss Rack Scale Design (RSD) technology and explain how physical hardware resources can be dynamically aggregated to meet the AI/HPC requirements. The ability to “compose on the fly” with workload-optimized hardware and accelerator devices through an API allow data center managers to manage these resources in an efficient automated manner.
We will also introduce an enhanced telemetry solution with Gnnochi, bandwidth discovery and smart scheduling, by leveraging RSD technology, for efficient workloads management in HPC/AI cloud.
InfiniBand In-Network Computing Technology and Roadmapinside-BigData.com
In this video from the UK HPC Conference, Richard Graham from Mellanox presents: InfiniBand In-Network Computing Technology and Roadmap.
"In-Network Computing transforms the data center interconnect to become a "distributed CPU", and "distributed memory", enables to overcome performance barriers and to enable faster and more scalable data analysis. HDR 200G InfiniBand In-Network Computing technology includes several elements - Scalable Hierarchical Aggregation and Reduction Protocol (SHARP), smart Tag Matching and rendezvoused protocol, and more. These technologies are in use at some of the recent large scale supercomputers around the world, including the top TOP500 platforms. The session will discuss the InfiniBand In-Network Computing technology and performance results, as well as view to future roadmap."
Watch the video:
Learn more: http://mellanox.com
and
http://hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Preparing to program Aurora at Exascale - Early experiences and future direct...inside-BigData.com
In this deck from IWOCL / SYCLcon 2020, Hal Finkel from Argonne National Laboratory presents: Preparing to program Aurora at Exascale - Early experiences and future directions.
"Argonne National Laboratory’s Leadership Computing Facility will be home to Aurora, our first exascale supercomputer. Aurora promises to take scientific computing to a whole new level, and scientists and engineers from many different fields will take advantage of Aurora’s unprecedented computational capabilities to push the boundaries of human knowledge. In addition, Aurora’s support for advanced machine-learning and big-data computations will enable scientific workflows incorporating these techniques along with traditional HPC algorithms. Programming the state-of-the-art hardware in Aurora will be accomplished using state-of-the-art programming models. Some of these models, such as OpenMP, are long-established in the HPC ecosystem. Other models, such as Intel’s oneAPI, based on SYCL, are relatively-new models constructed with the benefit of significant experience. Many applications will not use these models directly, but rather, will use C++ abstraction libraries such as Kokkos or RAJA. Python will also be a common entry point to high-performance capabilities. As we look toward the future, features in the C++ standard itself will become increasingly relevant for accessing the extreme parallelism of exascale platforms.
This presentation will summarize the experiences of our team as we prepare for Aurora, exploring how to port applications to Aurora’s architecture and programming models, and distilling the challenges and best practices we’ve developed to date. oneAPI/SYCL and OpenMP are both critical models in these efforts, and while the ecosystem for Aurora has yet to mature, we’ve already had a great deal of success. Importantly, we are not passive recipients of programming models developed by others. Our team works not only with vendor-provided compilers and tools, but also develops improved open-source LLVM-based technologies that feed both open-source and vendor-provided capabilities. In addition, we actively participate in the standardization of OpenMP, SYCL, and C++. To conclude, I’ll share our thoughts on how these models can best develop in the future to support exascale-class systems."
Watch the video: https://wp.me/p3RLHQ-lPT
Learn more: https://www.iwocl.org/iwocl-2020/conference-program/
and
https://www.anl.gov/topic/aurora
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Building efficient 5G NR base stations with Intel® Xeon® Scalable Processors Michelle Holley
Speaker: Daniel Towner, System Architect for Wireless Access, Intel Corporation
5G brings many new capabilities over 4G including higher bandwidths, lower latencies, and more efficient use of radio spectrum. However, these improvements require a large increase in computing power in the base station. Fortunately the Xeon Scalable Processor series (Skylake-SP) recently introduced by Intel has a new high-performance instruction set called Intel® Advanced Vector Extensions 512 (Intel® AVX-512) which is capable of delivering the compute needed to support the exciting new world of 5G.
In his talk Daniel will give an overview of the new capabilities of the Intel AVX-512 instruction set and show why they are so beneficial to supporting 5G efficiently. The most obvious difference is that Intel AVX-512 has double the compute performance of previous generations of instruction sets. Perhaps surprisingly though it is the addition of brand new instructions that can make the biggest improvements. The new instructions mean that software algorithms can become more efficient, thereby enabling even more effective use of the improvements in computing performance and leading to very high performance 5G NR software implementations.
What are latest new features that DPDK brings into 2018?Michelle Holley
We will provide an overview of the new features of the latest DPDK release including source code browsing and API listing of top two new features of latest DPDK release. And on top of that, there will be a hands-on lab, on the Intel® microarchitecture servers, to learn how getting started with DPDK will become much simpler and powerful.
Vector Packet Technologies such as DPDK and FD.io/VPP revolutionized software packet processing initially for discrete appliances and then for NFV use cases. Container based VNF deployments and it's supporting NFV infrastructure is now the new frontier in packet processing and has number of strong advocates among both traditional Comms Service Providers and in the Cloud. This presentation will give an overview of how DPDK and FD.io/VPP project are rising to meet the challenges of the Container dataplane. The discussion will provide an overview of the challenges, recent new features and what is coming soon in this exciting new area for the software dataplane, in both DPDK and FD.io/VPP!
About the speaker: Ray Kinsella has been working on Linux and various other open source technologies for about twenty years. He is recently active in open source communities such as VPP and DPDK but is a constant lurker in many others. He is interested in the software dataplane and optimization, virtualization, operating system design and implementation, communications and networking.
Intel® QuickAssist Technology Introduction, Applications, and Lab, Including ...Michelle Holley
Abstract: Intel® QuickAssist Technology improves performance and efficiency across the data center and other computing platforms by handling the compute-intensive operations of bulk cryptography, public key cryptography, and data compression. In this course, we will give an overview of the technology along with the summary of resources to get started with integrating Intel® QAT into your platform solutions. We will also demonstrate using Intel® QAT with applications such as OpenSSL, NGINX, and HAProxy, with a hands-on lab.
Speaker Bios:
Joel Auernheimer, a Platform Application Engineer at Intel, has been focused on enabling customers to integrate Intel® QuickAssist Technology in their platform solutions. Joel is a native of Phoenix, Arizona and enjoys hiking, basketball, soccer, singing, and spending time with friends and family.
Joel Schuetze has been with Intel since 1996. For the last 9+ years he has worked as Platform Application Engineer supporting customers with Intel QuickAssist Technology.
Development, test, and characterization of MEC platforms with Teranium and Dr...Michelle Holley
Mobile edge computing delivers cloud computing at the edge of the cellular network to drive services quality and innovation. The ability for CSPs and ISVs to effectively develop, deliver, and deploy MEC services on a given platform directly correlates with the availability and maturity of associated tools and test environment. Dronava is a hyper-connected, web-scale network reference design for the 5G mobile network, suitable for use as a test and development socket for cloud applications developed for MEC platforms with tools such as the Intel NEV SDK. With Dronava, developers can drive the application with real traffics from the network edge to the EPC core, and if need be, connect with services in the core network in order to fully characterize the functionalities, latency, and throughput of the platform and application.Teranium is an integrated development environment that simplifies the development, packaging, and deployment/management of cloud applications. Teranium can be utilized to develop and deploy MEC applications on a number of platforms. Together with Dronava, Teranium helps to reduce complexity and improve efficiency in the ability of CSPs and ISVs to adopt and deploy MEC-base services.
Mellanox is a supplier of interconnect solutions headquartered in Israel with worldwide offices and over 2,700 employees. It provides adapters, switches, cables, and transceivers for high-speed InfiniBand and Ethernet connectivity. Mellanox's solutions accelerate high performance computing and artificial intelligence workloads through technologies like GPUDirect, RDMA, and in-network computing capabilities. Mellanox's products are used to build several of the world's fastest supercomputers and its technologies help unlock the power of artificial intelligence for leading companies.
State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA CampFPGA Central
The panelists discussed their views on the current state and future of FPGAs. Mark expressed concerns about soft error rates and power densities in high-end FPGAs. Gordon said the industry is healthy but the race to more logic cells has pushed single architectures. Daniel said the line between FPGAs and ASICs is blurring and more niche and application-specific solutions will emerge. Chris said higher-level design flows will be needed to meet complexity demands. Umar viewed FPGAs as programmable processing engines well-suited for product architecture risk.
Enabling new protocol processing with DPDK using Dynamic Device PersonalizationMichelle Holley
The document provides a legal disclaimer for information presented about Intel products. It states that no license is granted to any intellectual property and Intel assumes no liability for products or fitness for particular purposes. Product specifications and descriptions are subject to change without notice. The document contains a copyright notice for Intel Corporation.
SCFE 2020 OpenCAPI presentation as part of OpenPWOER TutorialGanesan Narayanasamy
This document introduces hardware acceleration using FPGAs with OpenCAPI. It discusses how classic FPGA acceleration has issues like slow CPU-managed memory access and lack of data coherency. OpenCAPI allows FPGAs to directly access host memory, providing faster memory access and data coherency. It also introduces the OC-Accel framework that allows programming FPGAs using C/C++ instead of HDL languages, addressing issues like long development times. Example applications demonstrated significant performance improvements using this approach over CPU-only or classic FPGA acceleration methods.
Xilinx provides adaptable acceleration platforms for data centers. Their Alveo product lineup includes the U280, U250, U200, and low-profile U50 accelerator cards. The cards feature FPGAs with up to 1.3 million logic cells and high-speed memory. Xilinx also offers the U25 SmartNIC which combines an FPGA, ARM CPU, and dual 25GbE ports. These platforms accelerate workloads such as AI, databases, storage, and networking using reconfigurable and adaptable hardware. Xilinx supports deployment from their devices to cloud platforms using a unified software stack.
Intel développe une "ONP" (Open Network Platform) dit autrement un switch ouvert offrant les fonctions de base nécessaires au SDN. Si vous souhaitez connaitre le matériel utilisé, les stack logicielle exploitée et les compatibilité avec notamment les orchestrateurs, ce doc est fait pour vous.
In this deck from ATPESC 2019, James Moawad and Greg Nash from Intel present: FPGAs and Machine Learning.
"Neural networks are inspired by biological systems, in particular the human brain. Through the combination of powerful computing resources and novel architectures for neurons, neural networks have achieved state-of-the-art results in many domains such as computer vision and machine translation. FPGAs are a natural choice for implementing neural networks as they can handle different algorithms in computing, logic, and memory resources in the same device. Faster performance comparing to competitive implementations as the user can hardcore operations into the hardware. Software developers can use the OpenCL device C level programming standard to target FPGAs as accelerators to standard CPUs without having to deal with hardware level design."
Watch the video: https://wp.me/p3RLHQ-lnc
Learn more: https://extremecomputingtraining.anl.gov/archive/atpesc-2019/agenda-2019/
and
https://www.intel.com/content/www/us/en/products/programmable/fpga.html
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In the design of electronics and semiconductors, challenges are compounded by the integration of AI, multi-core, real-time software, network, connectivity, diagnostics, and security. Performance limits, battery life, and cost are adoption barriers. It is extremely important to have tools and processes that deliver efficiency throughout the design cycle.
Continuous verification from planning to development addresses the multi-discipline needs of hardware, software, and networks. This unique approach accelerates the design phase, defines the test efforts, and finds defects during specification. Architecture modeling is required to meet timing deadlines, generate the lowest power consumption, and attain the highest Quality-of-Service. optimize the electronic design system and designing of custom components.
Closed Loop Network Automation for Optimal Resource Allocation via Reinforcem...Liz Warner
In this talk, we present a closed-loop automation approach to dynamically adjust LLC cache allocation (Intel RDT) between high priority VNFs and BE workloads using reinforcement learning. The results demonstrated improved server utilization while maintaining required service level agreement for high priority VNFs.
Closed Loop Platform Automation - Tong Zhong & Emma CollinsLiz Warner
Closed-loop automation would dramatically help with the network transformation which is central to our business. Building a general analytics workflow to support various use cases (such as power management, fault prediction, networking slicing, etc.) is a critical component in the overall platform.
In this deck, Paul Isaacs from Linaro presents: State of ARM-based HPC. This talk provides an overview of applications and infrastructure services successfully ported to Aarch64 and benefiting from scale.
"With its debut on the TOP500, the 125,000-core Astra supercomputer at New Mexico’s Sandia Labs uses Cavium ThunderX2 chips to mark Arm’s entry into the petascale world. In Japan, the Fujitsu A64FX Arm-based CPU in the pending Fugaku supercomputer has been optimized to achieve high-level, real-world application performance, anticipating up to one hundred times the application execution performance of the K computer. K was the first computer to top 10 petaflops in 2011."
Watch the video: https://wp.me/p3RLHQ-lIT
Learn more: https://www.linaro.org/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Google and Intel speak on NFV and SFC service delivery
The slides are as presented at the meet up "Out of Box Network Developers" sponsored by Intel Networking Developer Zone
Here is the Agenda of the slides:
How DPDK, RDT and gRPC fit into SDI/SDN, NFV and OpenStack
Key Platform Requirements for SDI
SDI Platform Ingredients: DPDK, IntelⓇRDT
gRPC Service Framework
IntelⓇ RDT and gRPC service framework
Optimized HPC/AI cloud with OpenStack acceleration service and composable har...Shuquan Huang
Today data scientist is turning to cloud for AI and HPC workloads. However, AI/HPC applications require high computational throughput where generic cloud resources would not suffice. There is a strong demand for OpenStack to support hardware accelerated devices in a dynamic model.
In this session, we will introduce OpenStack Acceleration Service – Cyborg, which provides a management framework for accelerator devices (e.g. FPGA, GPU, NVMe SSD). We will also discuss Rack Scale Design (RSD) technology and explain how physical hardware resources can be dynamically aggregated to meet the AI/HPC requirements. The ability to “compose on the fly” with workload-optimized hardware and accelerator devices through an API allow data center managers to manage these resources in an efficient automated manner.
We will also introduce an enhanced telemetry solution with Gnnochi, bandwidth discovery and smart scheduling, by leveraging RSD technology, for efficient workloads management in HPC/AI cloud.
Dataplane networking acceleration with OpenDataplane / Максим Уваров (Linaro)Ontico
HighLoad++ 2017
Зал «Москва», 7 ноября, 13:00
Тезисы:
http://www.highload.ru/2017/abstracts/2909.html
OpenDataPlane (ODP, https://www.opendataplane.org) является open-source-разработкой API для сетевых data plane-приложений, представляющий абстракцию между сетевым чипом и приложением. Сейчас вендоры, такие как TI, Freescale, Cavium, выпускают SDK с поддержкой ODP на своих микросхемах SoC. Если проводить аналогию с графическим стеком, то ODP можно сравнить с OpenGL API, но только в области сетевого программирования.
...
PLNOG 17 - Nicolai van der Smagt - Building and connecting the eBay Classifie...PROIDEA
The document summarizes the migration of eBay Classifieds' infrastructure to a hybrid cloud architecture using OpenStack and Contrail. A 3-way partnership between eBay Classifieds, Infradata, and Juniper Networks built the cloud in 6 months. It integrated with the legacy infrastructure and launched initially with limited features in a single datacenter. The architecture includes OpenStack for orchestration, a Juniper underlay fabric, Contrail for SDN overlay, and L3VPN connectivity to the legacy MPLS backbone for a hybrid cloud. The cloud is now in production serving 300 nodes and expanding to additional regions.
Introduction to Programmable Networks by Clarence Anslem, IntelMyNOG
This document discusses programmable networks and introduces key concepts:
- Programmable networks allow for innovation by enabling the writing of packet processing algorithms rather than relying on fixed-function hardware. This is done through programmable switches and protocol-independent packet processors.
- P4 is a language that allows defining packet parsing, headers, tables, and processing logic in a target-independent way. It enables protocol and target independence.
- Programmable switches implement the PISA model with a parser, match-action tables, and deparser. They can be programmed through a P4 program that is compiled for the target hardware.
- Example applications discussed are in-band network telemetry and 5G
Example application providing guidelines for using the Cryptography Device Library framework.
Showcase DPDK cryptodev framework performance with a real world use case scenario.
Author: Georgi Tkachuk
DPDK IPSec performance benchmark ~ Georgii TkachukIntel
This document provides an overview of the DpdkIPSecsecuritygateway application, which is an Intel DPDK sample application that demonstrates using the Cryptography Device Library (cryptodev) framework to implement an IPSec security gateway with encryption and authentication. The application shows the flow of outbound and inbound traffic through the gateway and the use of security policies and security associations to classify and process packets. It also discusses performance considerations for running the application and maximizing throughput.
Packet processing in the fast path involves looking up bit patterns and deciding on an actions at line rate. The complexity of these functions at Line Rate, have been traditionally handled by ASICs and NPUs. However with the availability of faster and cheaper CPUs and hardware/software accelerations, it is possible to move these functions onto commodity hardware. This tutorial will talk about the various building blocks available to speed up packet processing both hardware based e.g. SR-IOV, RDT, QAT, VMDq, VTD and software based e.g. DPDK, Fd.io/VPP, OVS etc and give hands on lab experience on DPDK and fd.io fast path look up with following sessions. 1: Introduction to Building blocks: Sujata Tibrewala
Hari Krishna Vetsa has over 2 years of experience in RTL design including timing analysis, verification, testing, debugging, and logic minimization. He has knowledge of Tomasulo processors, PCI, UART, AXI4, SPI, I2C protocols, cache coherency, DDR3, slack borrowing, time stealing, and non-linear/wave pipelining. He has implemented Verilog and VHDL designs for modulation modules and an SDR platform on Xilinx FPGAs. He holds a Masters in Electrical Engineering from USC with a GPA of 3.9.
The document discusses using Lagopus software-defined networking (SDN) switches to demonstrate an SDN internet exchange (IX) at the Interop Tokyo 2015 technology show. Key points:
- Two Lagopus SDN switches were deployed as the core switches in an SDN IX to enable automated provisioning of inter-autonomous system layer 2 connectivity and on-demand packet filtering between internet service providers.
- The Lagopus switches achieved an average throughput of 2Gbps with no packet drops over a week during the show, demonstrating the potential for software switches in next-generation SDNs.
- Previous work to optimize the Lagopus switch performance through techniques like hardware offloading to FPGAs helped enable its
DPDK Summit 2015 - NTT - Yoshihiro NakajimaJim St. Leger
DPDK Summit 2015 in San Francisco.
NTT presentation by Yoshihiro Nakajima.
For additional details and the video recording please visit www.dpdksummit.com.
How our Cloudy Mindsets Approached Physical RoutersSteffen Gebert
The document discusses how EMnify integrated a pair of Juniper routers into their existing cloud-based workflows and monitoring tools. They deployed the routers using Ansible playbooks for configuration management and leveraged existing tools like Prometheus, Grafana, and CloudWatch for monitoring metrics, logs, and alerts. While the integration worked well, they note some challenges around testing configurations and limitations of the monitoring tools for high data volumes. The overall approach focused on minimizing new processes and tools by bridging the routers into their existing cloud-centric tooling.
The document describes the ADAM-3600 expansion wireless intelligent RTU. It has a powerful 32-bit processor, memory, operating system, and SD card slot for data storage. It supports various programming and communication protocols. It has built-in analog and digital I/O and four expansion slots. It supports both wireless and wired communication modules. The device provides a rich I/O system with on-board and expansion I/O. It is presented as a cost-effective intelligent RTU for various applications.
Anuta ATOM is a network automation platform that provides closed-loop automation, assurance, telemetry, and orchestration for multi-vendor, multi-domain networks. It offers model-driven automation, analytics, and assurance through microservices that scale to support millions of devices from over 45 vendors. Anuta ATOM allows for network automation, telemetry collection, analytics and reporting, and can be deployed in public, private, or hybrid clouds.
Oracle provides a comprehensive cloud infrastructure platform with compute, storage, networking and database services. Key features include fast NVMe SSD storage both locally and network attached, high performance bare metal and VM instances with GPU and AMD EPYC options, autonomous database services, and advanced networking capabilities like low latency and RDMA. Oracle's regional architecture and dedicated fast interconnects enable high availability across availability domains and regions.
The TMS320C6472 DSP is a six-core, fixed-point DSP from Texas instrument and two of these are integrated onto the Sundance EVP6472. Each DSP Core is a 700MHz DSP and can used for a many applications, requiring Embedded DSP Processing
The Intel QuickAssist Adapter 8960/8970 provides up to 100Gbps of hardware acceleration for data center applications. It utilizes Intel QuickAssist Technology software libraries and APIs to support network functions like IPsec and SSL/TLS. The adapter supports PCIe Gen3, virtualization with SR-IOV, and offers acceleration for security algorithms, compression, and wireless standards.
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2021/08/flexible-machine-learning-solutions-with-lattice-fpgas-a-presentation-from-lattice-semiconductor/
Sreepada Hegade, Senior Manager for ML Software and Solutions at Lattice Semiconductor, presents the “Flexible Machine Learning Solutions with Lattice FPGAs” tutorial at the May 2021 Embedded Vision Summit.
The ability to perform neural network inference in resource-constrained devices is fueling the growth of machine learning at the edge. But application solutions require more than just inference—they also incorporate aggregation and pre-processing of input data, and post-processing of inference results. In addition, new neural network topologies are emerging rapidly. This diversity of functionality and quick evolution of topologies means that processing engines must have the flexibility to execute different types of workloads. I/O flexibility is also key, to enable system developers to choose the best sensor and connectivity options for their applications.
In this talk, Hegade explores how the configurable nature of Lattice FPGAs and the soft cores implemented on them allow for quick adoption of emerging neural network topologies, efficient execution of pre- and post-processing functions, and flexible I/O interfacing. He also shows how his company optimizes network topologies and its compiler to get the best out of FPGAs.
A session in the DevNet Zone at Cisco Live, Berlin. Flare allows users with mobile devices to discover and interact with things in an environment. It combines multiple location technologies, such as iBeacon and CMX, with a realtime communications architecture to enable new kinds of user interactions. This session will introduce the Flare REST and Socket.IO API, server, client libraries and sample code, and introduce you to the resources available on DevNet and GitHub. Come visit us in the DevNet zone for a hands-on demonstration.
Similar to In-Memory Key Value Store (KVS) in FPGA for Ultra Low Latency and High Throughput (20)
Tom Diederich portfolio presentation (updated Nov. 18, 2016)Tom Diederich
I created this presentation to highlight some of the milestones in my career as an online community builder over the past 15 years. I hope it can also help other community managers and executives tasked with building and/or growing an online community.
This talk includes
* Tips for building and growing a new community from scratch
* Tips for resurrecting a floundering community
* How to connect Support to your community via Slack and other social tools
* The perks of a social listening program
* How to turn social rants into customer service tickets
* The importance of gamification
* And much more!
My name is Tom Diederich and this presentation is a timeline of sorts highlighting my experiences in the field of online community management, which started in 2005 when I joined an internal team at Intuit that created one of the world’s first online customer communities – a forums-based question-and-answer space for TurboTax customers.
The following year, I took everything I learned in that project and joined Symantec -- then the third-largest software company in the world -- where I assembled a nimble team of three and together we designed, launched and managed the organization’s first social media presence and online community in 2006. Yes, I am proud to say that I was Symantec's first community manager and first social media strategist.
I’ve been building and managing large corporate communities ever since. I hope this deck helps you in your work with online communities. Please feel free to contact if you'd like to ask any questions, etc.
How to build & grow online communities: with Tom DiederichTom Diederich
The document provides tips for building and growing a new online community. It recommends starting small with a specific goal, designing for members, preventing anonymity, seeding early content, gaining influencer support, incentivizing participation, appointing a community manager, planning for growth, allowing organic evolution, making registration easy, connecting to outside resources, and creating a superuser program for top members.
"Troubleshooting Apache Ignite (and best practices)" with Stan Lukyanov, [software engineer at GridGain Systems].
ummary: Whether you are getting started with Apache Ignite or have already deployed, this session is for you. Stan will explain how to set up deployments to make them easier to monitor, manage and keep up and running properly. He'll also hare best practice examples on how to:
* Configure Ignite and GridGain for deployment, management and monitoring
* Leverage log files during troubleshooting
* Use monitoring interfaces and tools such as JMX, Visor and Web Console
* Identify and fix top errors for newly installed and existing deployments
How to build a production-ready in-memory-based application in 1 hourTom Diederich
This document provides an overview of the Hypi platform, which uses GraphQL and Apache Ignite to provide a serverless backend API that can integrate with any public or private cloud. It discusses key aspects of GraphQL and Apache Ignite, and demonstrates how to build a TODO application using the Hypi platform, focusing on creating, completing, commenting on, and searching TODO items. The document also provides details on how data is stored and queries are routed in Hypi's architecture.
Ingesting streaming data for analysis in apache ignite (stream sets theme)Tom Diederich
Apache Ignite provides a distributed platform for a wide variety of workloads, but often the issue is simply in getting data into the database in the first place. The wide variety of data sources and formats presents a challenge to any data engineer; in addition, 'data drift', the constant and inevitable mutation of the incoming data's structure and semantics, can break even the most well-engineered integration.
This session, aimed at data architects, data engineers and developers, will explore how we can use the open source StreamSets Data Collector to build robust data pipelines. Attendees will learn how to collect data from cloud platforms such as Amazon and Salesforce, devices, relational databases and other sources, continuously stream it to Ignite, and then use features such as Ignite's continuous queries to perform streaming analysis.
We'll start by covering the basics of reading files from disk, move on to relational databases, then look at more challenging sources such as APIs and message queues. You will learn how to:
* Build data pipelines to ingest a wide variety of data into Apache Ignite
* Anticipate and manage data drift to ensure that data keeps flowing
* Perform simple and complex ad-hoc queries in Ignite via SQL
* Write applications using Ignite to run continuous queries, combining data from multiple sources
Machine learning and deep learning with Apache IgniteTom Diederich
Apache Ignite technology evangelist Akmal Chaudhri provides An overview of the machine learning and deep learning algorithms and how they work; examples of how to implement each machine learning and deep learning algorithm; along with tips and tricks for getting the most performance out of machine learning and deep learning.
Apache Ignite is an open-source distributed database, caching and processing platform designed to store and compute on large volumes of data across a cluster of nodes.
Apache Ignite has built-in machine learning (ML) and deep learning (DL). It eliminates any delays caused by transferring data to a different database or store. It also delivers near real-time performance by running a variety of ML and DL algorithms in place, in memory, that are optimized for collocated processing.
Heimdall Data: "Increase Application Performance with SQL Auto-Caching; No Co...Tom Diederich
This document discusses a SQL database proxy called Heimdall Data that provides several benefits such as automated failover, SQL read/write splitting, reducing network latency, and automated caching and cache invalidation. It describes Heimdall's software options, use cases including SQL results caching, automated failover, and horizontal scaling out databases. The document also summarizes how Heimdall's distributed deployment works and how it can perform end-to-end SQL analytics.
Improving Apache Spark™ In-Memory Computing with Apache Ignite™Tom Diederich
GridGain Systems Lead Architect Valentin (Val) Kulichenko presented the following talk at the May 17 Bay Area In-Memory Computing Meetup: Improving Apache Spark™ In-Memory Computing with Apache Ignite™
Val explained how Apache Ignite™ simplifies development and improves performance for Apache Spark™. He'll demonstrate how Apache Spark and Ignite are integrated, and how they are used to together for analytics, stream processing and machine learning.
The following was covered:
* How Apache Ignite’s native RDD and new native DataFrame APIs work
* How to use Ignite as an in-memory database and massively parallel processing (MPP) style collocated processing for preparing and managing data for Spark
* How to leverage Ignite to easily share state across Spark jobs using mutable RDDs and DataFrames
* How to leverage Ignite distributed SQL and advanced indexing in memory to improve SQL performance
Comparing Apache Ignite and Cassandra for Hybrid Transactional/Analytical Pro...Tom Diederich
Dmitriy Setrakyan, founder and Chief Product Officer at GridGain, delivered this talk during the April 11 Bay Area In-Memory Computing Meetup.
Abstract: The 10x growth of transaction volumes, 50x growth in data volumes -- along with the drive for real-time visibility and responsiveness over the last decade -- have pushed traditional technologies including databases beyond their limits. Your choices are either buy expensive hardware to accelerate the wrong architecture, or do what other companies have started to do and invest in technologies being used for modern hybrid transactional/analytical processing (HTAP).
This presentation covered:
* The requirements for real-time, high volume HTAP
* Architectural best practices, including how in-memory computing fits in and has eliminated tradeoffs between consistency, speed and scale
* A detailed comparison of Apache Ignite and GridGain® for HTAP
“Building consistent and highly available distributed systems with Apache Ign...Tom Diederich
Summary: It is well known that there is a tradeoff between data consistency and high availability. However, there are many applications that require very strong consistency guarantees, and making such applications highly available can be a significant challenge.
In this session, attendees will be given an overview of Apache Ignite and GridGain capabilities that allow the delivery of high availability, while not breaking data consistency. Specific guidelines will be presented on how to build such systems covering topics such as:
• In-memory backups.
• Data persistence.
• Data center replication.
• Full and incremental snapshots.
At the end of this session, attendees will have better understanding of how Apache Ignite and GridGain work, and how to use different features of these products to build applications that are both consistent and highly available.
This document summarizes a MySQL Meetup that took place on September 8th, 2014. It includes the agenda for the meetup which involved registration, a speaker presentation on quick performance checks, and a networking session. The speaker Wayne Leutwyler presented on useful views for checking database performance and provided thresholds and recommendations for optimizing various MySQL variables if certain metrics were not within acceptable ranges. The document also briefly discussed some command line tools for system monitoring and ended by thanking the event sponsors.
STATATHON: Unleashing the Power of Statistics in a 48-Hour Knowledge Extravag...sameer shah
"Join us for STATATHON, a dynamic 2-day event dedicated to exploring statistical knowledge and its real-world applications. From theory to practice, participants engage in intensive learning sessions, workshops, and challenges, fostering a deeper understanding of statistical methodologies and their significance in various fields."
The Ipsos - AI - Monitor 2024 Report.pdfSocial Samosa
According to Ipsos AI Monitor's 2024 report, 65% Indians said that products and services using AI have profoundly changed their daily life in the past 3-5 years.
Codeless Generative AI Pipelines
(GenAI with Milvus)
https://ml.dssconf.pl/user.html#!/lecture/DSSML24-041a/rate
Discover the potential of real-time streaming in the context of GenAI as we delve into the intricacies of Apache NiFi and its capabilities. Learn how this tool can significantly simplify the data engineering workflow for GenAI applications, allowing you to focus on the creative aspects rather than the technical complexities. I will guide you through practical examples and use cases, showing the impact of automation on prompt building. From data ingestion to transformation and delivery, witness how Apache NiFi streamlines the entire pipeline, ensuring a smooth and hassle-free experience.
Timothy Spann
https://www.youtube.com/@FLaNK-Stack
https://medium.com/@tspann
https://www.datainmotion.dev/
milvus, unstructured data, vector database, zilliz, cloud, vectors, python, deep learning, generative ai, genai, nifi, kafka, flink, streaming, iot, edge
Beyond the Basics of A/B Tests: Highly Innovative Experimentation Tactics You...Aggregage
This webinar will explore cutting-edge, less familiar but powerful experimentation methodologies which address well-known limitations of standard A/B Testing. Designed for data and product leaders, this session aims to inspire the embrace of innovative approaches and provide insights into the frontiers of experimentation!
Global Situational Awareness of A.I. and where its headedvikram sood
You can see the future first in San Francisco.
Over the past year, the talk of the town has shifted from $10 billion compute clusters to $100 billion clusters to trillion-dollar clusters. Every six months another zero is added to the boardroom plans. Behind the scenes, there’s a fierce scramble to secure every power contract still available for the rest of the decade, every voltage transformer that can possibly be procured. American big business is gearing up to pour trillions of dollars into a long-unseen mobilization of American industrial might. By the end of the decade, American electricity production will have grown tens of percent; from the shale fields of Pennsylvania to the solar farms of Nevada, hundreds of millions of GPUs will hum.
The AGI race has begun. We are building machines that can think and reason. By 2025/26, these machines will outpace college graduates. By the end of the decade, they will be smarter than you or I; we will have superintelligence, in the true sense of the word. Along the way, national security forces not seen in half a century will be un-leashed, and before long, The Project will be on. If we’re lucky, we’ll be in an all-out race with the CCP; if we’re unlucky, an all-out war.
Everyone is now talking about AI, but few have the faintest glimmer of what is about to hit them. Nvidia analysts still think 2024 might be close to the peak. Mainstream pundits are stuck on the wilful blindness of “it’s just predicting the next word”. They see only hype and business-as-usual; at most they entertain another internet-scale technological change.
Before long, the world will wake up. But right now, there are perhaps a few hundred people, most of them in San Francisco and the AI labs, that have situational awareness. Through whatever peculiar forces of fate, I have found myself amongst them. A few years ago, these people were derided as crazy—but they trusted the trendlines, which allowed them to correctly predict the AI advances of the past few years. Whether these people are also right about the next few years remains to be seen. But these are very smart people—the smartest people I have ever met—and they are the ones building this technology. Perhaps they will be an odd footnote in history, or perhaps they will go down in history like Szilard and Oppenheimer and Teller. If they are seeing the future even close to correctly, we are in for a wild ride.
Let me tell you what we see.
The Building Blocks of QuestDB, a Time Series Databasejavier ramirez
Talk Delivered at Valencia Codes Meetup 2024-06.
Traditionally, databases have treated timestamps just as another data type. However, when performing real-time analytics, timestamps should be first class citizens and we need rich time semantics to get the most out of our data. We also need to deal with ever growing datasets while keeping performant, which is as fun as it sounds.
It is no wonder time-series databases are now more popular than ever before. Join me in this session to learn about the internal architecture and building blocks of QuestDB, an open source time-series database designed for speed. We will also review a history of some of the changes we have gone over the past two years to deal with late and unordered data, non-blocking writes, read-replicas, or faster batch ingestion.