IGBT gate driver power supply has been designed based on flyback topology. Design steps are given and has been verified using LTspice simulations.

1. IGBT Gate Driver Flyback Power Supply:
Design and Simulation using LTspice
Kunwar Aditya
January 06, 2019

2. Design
Features
 Supports 3 IGBT Gate Drivers for Three-Phase Inverter
 Operates with regulated (within 10%) 18 V supply
 Output Power: 2 W per Gate Driver
 Output Voltage: 24 V output per Gate Driver with ripple less than 1%
 Split of 24 V rail into 16 V and -8V rails using a Zener diode and a series
resistor
 Constant switching frequency of 100 kHz
 External enable/disable circuit

3. Power supply Specifications
 Vin: 15～19VDC
 Vout: 3 output of 24VDC at 260 mA total
 Total Output Power, Pout: 6.2 W
 Switching Frequency, fs: 100 kHz
 Output Ripple Voltage ∆Vo: 240mVp-p
Fig: Simplified Flyback schematic
LP LS
Iout

4. Design Steps: Determining operating mode
ITEM DCM CCM
Transformer
Inductance: down,
Size: down, Cost: down
Inductance: up, Size:
up, cost: up
Rectifier Diode FRD, Cost: down Ultra-FRD, Cost: up
MOSFET
Power: up, Size: up,
Cost: up
Power: down, Size:
down, Cost: down
Output Capacitor
Ripple current: up,
Size: up
Ripple current: down,
Size: up,
Efficiency
Switching loss: down*,
Efficiency: up
Switching loss: up,
Efficiency: down
Transient Response** Faster slower
Compensation** Much Simpler simple
Ts DTs D2Ts
(1-D-D2)Ts
IP
IS
Vds
CCM DCM
t
t
t
t
n*Vout
Vin
* ZCS at MOSFET turn on, ZCS at diode turn off.
**CCM mode has a significant RHP Zero which introduces phase lag therefore its close loop bandwidth is
limited and response is slower compared to DCM in which RHP zero is not significant.
Based on above comparison DCM is preferred choice for low power SMPS
Table: DCM Vs CCM

5. Design Steps: Calculation of circuit parameters
1. Set the reflected/flyback voltage (VOR):
 When VOR is determined, turns ratio (n) and maximum duty cycle (Dmax) are fixed
 Higher the duty ratio (D), smaller the primary current
 Too high value of VOR increases voltage stress on MOSFET; too low value increases voltage stress on diode
 Key Equations:
𝑁 𝑃
𝑁 𝑆
= 𝑛 =
𝑉 𝑂𝑅
𝑉𝑜𝑢𝑡+𝑉 𝑓
(I) 𝐷 𝑚𝑎𝑥 =
𝑉 𝑂𝑅
𝑉 𝑖𝑛_𝑚𝑖𝑛+𝑉 𝑂𝑅
(II)
 If Dmax becomes > 0.5 at minimum input voltage (Vin_min) and maximum load, VOR needs to be adjusted to
keep it below 0.5
 Dmax is usually decided by PMIC datasheet; 0.46 and 0.95 are typical values mentioned in PMIC datasheet
 In deciding VOR margin must be given to consider forward recovery of the diode in clamp circuit as well as
load transients
 For this power supply: VOR=12.5V, This gives Dmax=0.4545 and Assuming Vf=1V , n = 0.5
***Vf is forward voltage drop in rectifier diode

6. Design Steps: Calculation of circuit parameters
2. Calculate critical value of secondary inductance: LS, and secondary peak current: ISPK
𝐿 𝑆 =
𝑉𝑜𝑢𝑡+𝑉 𝑓 × 1−𝐷 𝑚𝑎𝑥
2
2×𝐼 𝑜𝑚𝑎𝑥×𝑓𝑠
(III)
 To provide for a margin, such as an over-load protection point, the maximum load current Iomax should be 1.2
times the Iout.
 Putting together all values, Ls =119 µH
𝐼𝑆𝑃𝐾 =
2×𝐼 𝑜𝑚𝑎𝑥
1−𝐷 𝑚𝑎𝑥
= 1.2125 𝐴 (IV)
3. Calculate primary inductance LP and primary peak current IPPK
𝐿 𝑃 = 𝐿 𝑆 × 𝑛2
= 29.750 µ𝐻 (V)
𝐼 𝑃𝑃𝐾 = 𝐼𝑆𝑃𝐾 × 𝑛 = 2.425 𝐴 (VI)
 Calculate RMS value of primary current IPRMS
𝐼 𝑃𝑅𝑀𝑆 = 𝐼 𝑃𝑃𝐾 ×
𝐷 𝑚𝑎𝑥
3
= 0.9746 𝐴 (VII) **This is total secondary peak current

7. Design Steps: Calculation of circuit parameters
4. Calculate duty cycle, D and D2 for any input and output voltage
𝐷 =
2𝑃 𝑂 𝐿 𝑃 𝑓𝑠
𝑉 𝑖𝑛
(VIII)
𝐷2 =
𝑉 𝑖𝑛×𝐷
𝑛× 𝑉𝑜𝑢𝑡+𝑉 𝑓
(IX)
 Verify that D+D2 < 1 for DCM
5. Calculate auxiliary winding turn ratio
𝑛 𝑎𝑢𝑥 = 𝑛 ×
𝑉𝑜𝑢𝑡+𝑉 𝑓
𝑉𝑎𝑢𝑥+𝑉 𝑓
(X)
Here, Vaux is output of aux winding, naux is primary to aux turn ratio
 For Vaux=24 V, naux= 0.5
 Load on aux winding is usually the IC bias and MOSFET gate drive (~0.1 A)

8. Design Steps: Selection of MOSFET
 Vds of MOSFET is calculated by the following eq:
𝑉𝑑𝑠 𝑚𝑎𝑥 = 𝑉𝑖𝑛𝑚𝑎𝑥 + 𝑉𝑂𝑅 + 𝑉𝑆𝑝𝑖𝑘𝑒
= 19 + 12.5 + 1 ∗ 12.5
= 44 𝑉 (I)
 Vspike is voltage spike due to leakage inductance.
Assuming that a snubber will be added, a typical design
value is ½ of the flyback voltage (VOR). However, for this
power supply Vspike equal to VOR has been considered.
 Current rating is usually selected to be twice of primary
peak current IPPK
Fig: Typical MOSFET Vds

9. Design Steps: Selection of Rectifier Diode
 A fast output rectifier diode should be selected, e.g. a SBD (Schottky barrier diode) or a FRD (Fast recovery
diode)
 Reverse Voltage Vdr to diode is given as:
𝑉𝑑𝑟 = 𝑉𝑜𝑢𝑡 +
𝑉 𝑖𝑛𝑚𝑎𝑥
𝑛
= 66.8 𝑉 (I)
 RMS current flowing diode is same as secondary current flowing in each winding ISRMS1
𝐼𝑆𝑅𝑀𝑆1 =
2×𝑃𝑜𝑢𝑡
3×𝑉𝑜𝑢𝑡×𝐷2
×
𝐷2
3
(II)
 Assuming maximum current flowing in each winding is 1.2 times the ISRMS1 we get 0.1435A
 Select diode so that its VRRM (maximum reverse voltage) is at least 30% higher than Vdr and IF (Ave. forward
current) is at least 50% higher than the ISRMS1.

10. Design Steps: Selection of output capacitor
 Output capacitors smooth ripples in the rectified voltage, and also serve to maintain stability during transient
increases in the load current.
 Output capacitor is determined on the basis of peak to peak ripple voltage ∆VO , ESR and RMS current rating
𝐶 𝑂𝑚𝑖𝑛 =
𝐷 𝑚𝑎𝑥×𝐼 𝑜𝑢𝑡
∆𝑉𝑜× 𝑓𝑠
(I) ‘Select capacitor value larger than this’
𝐸𝑆𝑅 𝑚𝑎𝑥 =
∆𝑉𝑜
𝐼 𝑆𝑃𝐾
(II) ‘Select cap with ESR lower than this value’
 Chose ESR value in datasheet at fs
 Minimum RMS current of chosen CO is given as:
𝐼 𝐶𝑂𝑅𝑀𝑆 = 𝐼𝑆𝑅𝑀𝑆
2
− 𝐼 𝑜𝑢𝑡
2
(III)
‘The combined RMS current rating of output cap(s) used should be higher than this value’

11. Nominal Parameters
Parameters Values
Duty cycle 0.3587
Peak Primary Current 2.3 A
Peak Secondary Current (Each secondary) 0.3559 A
Average Output Current (Each secondary) 0.0868 A
Voltage across MOSFET 31.5 V
Voltage across Diode 58 V
Voltage across LP during TON 17 V
Voltage across LP during TOFF -12.5 V
Voltage across LS during TON 34 V
Voltage across LS during TOFF -24 V
Table: DC Operating points for 24 V output at 6.2 W and Vin =17 V (obtained from
calculations)

12. Design Steps: Design of Clamp circuit
Fig : Current flow when switch is off
IP
Problem: Drain voltage with 3% leakage
Solution 1: Zener Clamp
Solution 2: RCD Clamp across MOSFET
Solution 3: RCD Clamp across Inductor
𝑉𝑙𝑘𝑔 = 𝑉𝑖𝑛 + 𝑉𝑂𝑅 + 𝐼 𝑃𝑃𝐾
𝐿𝑙𝑘𝑔
𝐶 𝑑𝑠
1. Zener Clamp:
 Effectively clips the voltage spice until leakage energy is dissipated in
Zener diode
 Only clamps when combine VOR and Vspike is greater than its
breakdown voltage; no power dissipation at light load
 Dissipate more power at full load
 Doesn’t damp ringing; may be difficult to pass EMI compliances
2. RCD clamp:
 Cheaper than Solution 1
 Dissipates power even under no load conditions as there is at least
VOR voltage across Rclamp at all time
 Effective at even light load at the cost of efficiency
 Not only clamps but also slows down MOSFET dV/dt, easier to meet
EMI compliances
 Solution 2 needs to clamp voltage higher than VOR+Vin
 Solution 3 needs to clamp voltage higher than VOR only
 Dissipation of Rclamp in solution 2 for same amount of current will be
higher
3. Other solutions: active clamp, TVS, Zener across MOSFET

13. Design Steps: Design of RCD Clamp
 Decide the clamp voltage Vclamp
 The higher we select clamp voltage, the lower the overall dissipation
 A typical design uses Vspike equal to ½ of VOR.
 For this design Vspike equal to VOR has been selected
 A value lower than Rclamp will cause less spike but more losses, a higher value will
cause more spike
Vclamp
Vspike
VOR
Fig : Drain voltage after adding clamp
Fig. Effectiveness of adding clamp

14. Design Step: Loop compensation
Fig : Simulation Results: Loop compensation using
pole/zero cancellation
Fig : Type II compensator

15. LTspice Simulation Circuit

16. Simulation Results
Fig : DC operating points obtained from simulation

17. Simulation Results
Fig : Gate Voltage, ILP, ILS, Vout at full load (276.5 Ohm ) and one-third (800 Ohm) load at 24 Volt output, Vin is 17 V
1/3rd load

18. Simulation Results
Fig : Output voltage and current for step change in load
from half load to full load, Vin=17 V
Fig : Output voltage for different values of Vin

19. Simulation Results
Fig : Enable/Disable circuit demonstration

20. Important References used for this design
 S. B. Yaakov, G. Ivensky, "Passive lossless snubbers for high frequency PWM converters", IEEE APEC'99, 1999-Mar
 Ray Ridley, “Flyback Converter snubber design”, Switching power magazine, 2005.
 Ben-Yaakov, s. https://www.youtube.com/user/sambenyaakov/videos.
 Claudio Adragna, “Offline flyback converters design methodology with the l6590 family” Application Note AN1262, [online] Available: https://www.st.com.
 Sanjay Pithadia, N. Navaneeth Kumar, “Analysis of Power Supply Topologies for IGBT Gate Drivers in Industrial Drives” Application Report SLAA672, [online]
Available: http://www.ti.com/lit/ug/tidu411/tidu411.pdf.
 Allan A. Saliva, “Design Guide for Off-line Fixed Frequency DCM Flyback Converter” Design Note DN 2013-01, [online] Available:
https://www.mouser.com/pdfdocs/DN_201301.pdf

21. Thank You!
Contact: Kunwar.aditya1@gmail.com for the simulation file