This document presents a fault tolerant embedded RAM architecture using BISR (Built In Self Repair) technique. The architecture uses normal words in the RAM as redundancy instead of adding extra rows and columns, which reduces area. It consists of BIST (Built In Self Test), MUX, and BISD (Built In Self Diagnosis) modules. The BIST module tests the memory using the MarchC- algorithm and detects faults. The BISD module stores fault addresses and replaces them with redundant addresses. The architecture can repair faults in normal locations as well as redundant locations. It was implemented on a Spartan3E FPGA and able to successfully detect and repair stuck-at faults.