Hao-Hsiang Ma is seeking a position in ASIC/VLSI/FPGA hardware design or verification. He has a Master's degree in Electrical and Computer Engineering from Rice University and previous degrees from National Cheng Kung University and Tamkang University in Taiwan. He has skills in Verilog, SystemVerilog, C/C++, and FPGA tools. His work experience includes internships at MediaTek doing verification and as a software engineer at FINDREAM. He has also completed projects involving linear equation solvers on FPGA boards, noise filtering, and cache coherence protocols.

1. Hao-Hsiang (Eliot) Ma
469-803-0281 | 18331 Roehampton Dr. Apt A535, Dallas, TX75252 | hm8@alumni.rice.edu| http://hm8426.wix.com/mycv
OBJECTIVE: Seeking a position in ASIC/VLSI/FPGA hardware digital design or verification
EDUCATION
Rice University, Houston, TX, USA Jan2014 - May 2015
Master of Electrical and Computer Engineering (Overall GPA: 3.8)
Coursework: Advanced VLSI, Advanced Digital Hardware Design, Analog Circuit Design, Algorithms,
High Performance Computer Architecture, Computer Network, Vector Space and DSP.
National Cheng Kung University (NCKU), Tainan, Taiwan Sep 2010 - Jul 2012
Master of Microelectronic Engineering (Overall GPA: 3.6)
Tamkang University, Taipei, Taiwan Sep 2006 - Jul 2010
Bachelor of Electrical Engineering (Major GPA: 3.6)
SKILLS
Language: Verilog, SystemVerilog (UVM), Perl, C/C++, Python, Matlab, Swift, VHDL, Native Speaker in Chinese.
Tools: ISE, Simulink, Xilinx FPGA tools (Sysgen, Vivado+HLS), VCS, Perforce, PCB build, 8051 microcontroller.
WORK EXPERIENCE
Chip Design Verification Intern in MediaTek Inc., Taiwan – Perl, SystemVerilog (UVM) Jun 2015 - Sep 2015
n Designed 3 automatic report tools to scan the data from Excel and created algorithms to filter the coverage report.
n The tools were applied on MT7668, MT7622 and MT6632 with MVsim, pinmux, line and toggle coverage report.
n Built a UVM test bench, it consist master agents to drive constraint randomization stimulus to DUT (APB 3.0).
n Implemented slave agent to observe the stimulus driven by DUT and informed slave sequence to control memory.
n Built a scoreboard to cover the feature in simulation and used virtual sequencer to drive master agents.
Software Engineer in FINDREAM, Mountain Veiw, CA – Perl Nov 2015 - Present
n Designed an employ pressure index system to record employee’s pressure, meeting hours, performance…etc.
n Built a database for employee to login with password, automatically record data and sort report.
Research Assistant & Lab Manager in National Cheng Kung University, Taiwan – Matlab Oct 2010 - Jul 2012
n Designed a simulator to calculate repetition rate, pulse duration, peak power and pulse energy of pulse laser.
n Built a CW-pumped passively pulsed all-fiber SAQS laser and maximized the pulse repetition rate (2.5k->300kHz).
PROJECT EXPERIENCE
SOC integration: Linear Equations Solver on Zedboard – C, Xilinx Sysgen, Vivado, Simulink Dec 2014
n Designed a 4x4 Linear System Solver, which took 6µs to execute (4 times faster than stand-alone C code version).
n Applied Triangular Systolic-Array for Givens QR Decomposition and Systolic-Array for Matrix-Multiplication.
n Devised self-made Cordic without multiplier, and optimized by interface FIFO and Pipeline.
Noise filter system on FPGA – Verilog, ISE, Matlab Dec 2014
n Designed a 16-point Fast Fourier Transform (FFT) using Cooley-Tukey algorithm and verified with lsim.
n Used only one 32bit floating point adder and one 32bit floating point multiplier on FFT to minimize the design area.
n Implemented a Chebyshev IIR filter to reduce the environment noise while human voice is unaffected.
Cache coherence protocol, MSI, MOESI – C, Yacsim Mar 2015
n Implemented snoop-based MSI and MOESI protocol for a multi-core simulator in C language.
n Designed the front-end controller for communication between each core and its cache.
n Designed the back-end controller for cache-memory and cache-cache communication through bus broadcast.
Microprocessor Game Design: Nokia Snake Game – VHDL, Maxplus2 Jun 2010
n Designed and implemented on Altera CPLD/FPGA broad LP-2900, output on an 8 X 8 LED dot matrix display.
n Created pseudorandom pattern to generate the food at random location for snake to eat and grow longer.
HONOR & VOLUNTEER
Instructor, SPYCD Ballroom Dance Performance and Competition Team Oct 2015 - Present
Best Poster Paper Award, First Author: International Photonics Conference 2011 Dec 2011
Ministry of Education Scholarship: Electrical engineering graduate school, NCKU Oct 2010 - Jun 2012