Jovin Miranda is a computer engineer seeking opportunities in ASIC design and verification. He has a Master's in Computer Engineering from NC State University and a Bachelor's in Electronics and Telecommunication Engineering from University of Mumbai. His technical skills include Verilog, SystemVerilog, C++, Python, and tools like Modelsim, Synopsys, and Cadence. He has experience in RTL design, verification, computer architecture, and currently works as a research assistant designing hardware accelerators. His projects include verifying a pipelined microcontroller and designing a hardware accelerator for matrix inversion.

1. Jovin Miranda
1043 Wood Duck AVE, Santa Clara, CA | (919)-931-4507| | jmirand@ncsu.edu | https://www.linkedin.com/in/jovin-miranda/
PROFILE:
Skilled Computer Engineer seeking fulltime opportunities in the domain of Digital ASIC Design, ASIC Verification and
CPU Verification.
ACADEMICS:
Masters of Science - Computer Engineering Major GPA: 3.5/4.0
North Carolina State University, Raleigh, NC Aug ’15 – May’17
Bachelor of Engineering - Electronics and Telecommunication Engineering GPA: 3.5/4.0
University of Mumbai, Mumbai, India Aug’08 – July’12
TECHNICAL SKILLS:
Languages: Verilog, System Verilog, C++, Python, Bash Scripting, TCL
Tools: Modelsim, Synopsys Design Compiler, Cadence Virtuoso, GitHub, VIM
Operating Systems: Linux, Windows
Design: RTL Design, Synthesis, Logic Design, Clock Domain Crossing, Asynchronous FIFO, Timing, Finite State
machines (FSM), Low Power Design
Verification: Functional Verification, Test Bench Design, Assertions, Coverage, Interfaces, Threads, Events
Computer Architecture: Multilevel Cache, Pipelining, Branch Prediction, Instruction Level Parallelism, Out of order
Superscalar pipeline, Cache Coherency, Cache Coherency Protocols, Virtual Memory
WORK EXPERIENCE:
Research Assistant, North Carolina State University [Remote] Aug’17 – Present
➢ Working under Dr. Paul Franzon to design and implement Hardware Accelerator to implement Bellman Ford Algorithm.
➢ Simultaneously working to design and implement Hardware which is a simplified version of a Convolutional Neural
Network.
PROJECTS:
Functional Verification of a Pipelined LC3 Micro-Controller (Language: System Verilog, Tools: ModelSim)
➢ Implemented a layered test bench to verify the functionality of data and control paths of LC3 Microcontroller. Designed
Driver and Generator to drive legal pseudo random instructions into the DUT. Designed Checker functions and Golden
reference model for all 6 stages of the LC3 controller to verify functionality. Used System Verilog Assertions.
Hardware Accelerator to compute inversion of a 10X10 Tri-Diagonal Matrix (Language: Verilog, Tools: ModelSim,
Synopsys Design Compiler)
➢ Implemented a synthesizable hardware accelerator and incorporated 32bit IEEE floating point units from Designware
Design focus was on reducing delay and area. Full operational functionality achieved at 14ns with a total of 172 clock
cycles and 33713 um2 die area.
Multilevel Cache Hierarchy Simulator (Language: C++)
➢ Developed a simulator for two-level (L1 and L2) cache hierarchy with parameterized geometry. Replacement policies
implemented: LRU, FIFO, Pseudo LRU. Inclusion policy implemented: inclusive, exclusive, non-inclusive.
Superscalar Out of Order Processor Simulator with Dynamic Instruction Scheduling (Language: C++)
➢ Designed a 9-stage micro-architecture simulator for an “Out of Order” Super Scalar Processor that fetches and issues N
instructions per cycle assuming perfect caches and perfect branch predictors.
➢ Processor's performance was evaluated with the parameter "Instructions Per Cycle" obtained by varying Re-Order
Buffer (ROB) size and Issue queue size.
Branch Predictor Simulator (Language: C++)
➢ Designed a parametric simulator for Bimodal, G-share, Hybrid and Yeh-Patt branch predictors with an optional branch
target buffer. Analyzed the performance of the predictors by running the simulator with different configurations
against standard bench marks.
OTHER EXPERIENCE:
Sr. Engineer, New Ray Engineering Dec’12 – June’15
➢ Supervised over a team of engineers and handled multiple projects; also in charge in dealing with clients. PLC
Programming and designing the GUI as per customer requirement on SCADA systems; Site commissioning.