Half bridge converter simulation.pdf

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Design Project: Switch Mode Power Supply
Date: December 06th
, 2007

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Table of Contents
Abstract................................................................................................................................ 4
Introduction .......................................................................................................................... 4
Converter Topology Selection .......................................................................................... 5
The Isolated Half-Bridge SMPS........................................................................................ 7
Converter Analysis ............................................................................................................... 9
Large Signal Analysis ....................................................................................................... 9
Mode 1: 0 ≤ t < t1 ................................................................................................... 9
Mode 2: t1 ≤ t < t2................................................................................................. 10
Mode 3: t2 ≤ t < t3................................................................................................. 11
Mode 4: t3 ≤ t < t4................................................................................................. 12
Volt-Second Balance of Inductors:.............................................................................. 13
Charge-Balance of Capacitors: ................................................................................... 14
Source:........................................................................................................................ 14
Turns Ratio Selection.................................................................................................. 14
Small Signal Analysis ..................................................................................................... 15
Component Selection.................................................................................................. 21
Controller Design ............................................................................................................... 22
Sensor Gain.................................................................................................................... 22
Line-to-Output................................................................................................................. 23
Control-to-Output............................................................................................................ 25
Uncompensated Loop Gain............................................................................................ 27
Compensator Loop Gain................................................................................................. 28
Closed Loop Performance.............................................................................................. 29
Simulation Validation.......................................................................................................... 32
Conclusions........................................................................................................................ 44
References......................................................................................................................... 45
Appendix A......................................................................................................................... 46
Matlab ‘M-file’ ................................................................................................................. 46

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List of Figures
Figure 1: Half-Bridge SMPS Diagram................................................................................... 7
Figure 2: Timing Diagram..................................................................................................... 7
Figure 3: Mode 1 Diagram.................................................................................................... 9
Figure 4: Mode 2 Diagram.................................................................................................. 10
Figure 7: Output Inductor Differential Equation Modeled.................................................... 19
Figure 8: Output Capacitor Differential Equation Modeled ................................................. 20
Figure 9: Input Current Equation Modeled ......................................................................... 20
Figure 10: Half-Bridge Small Signal Model......................................................................... 21
Figure 11: Half-Bridge Small Signal Model (simplified) ...................................................... 21
Figure 12: Converter & Controller Diagram........................................................................ 22
Figure 13: Half-Bridge Small Signal Model (d = 0) ............................................................. 23
Figure 14: Line-to-Output Circuit Model (d = 0).................................................................. 23
Figure 15: Bode Plot of Gvi(s)............................................................................................. 24
Figure 16: Control-to-Output Circuit Model (vi = 0)............................................................. 25
Figure 17: Bode Plot of Gvd(s) ............................................................................................ 26
Figure 18: Uncompensated Loop Bode Plot – Tu(s)........................................................... 27
Figure 19: Compensator Loop Bode Plot – Gc(s)............................................................... 29
Figure 20: Closed Loop Bode Plot – T(s) ........................................................................... 30
Figure 21: Simulink – Converter......................................................................................... 32
Figure 22: Simulink – Pulse Width Modulation................................................................... 33
Figure 23: Simulink – Steady-state Operation.................................................................... 33
Figure 24: Simulink – Output Voltage Ripple, Vin = 425V.................................................. 34
Figure 25: Simulink – Load Max to Min, Vin = 425V........................................................... 35
Figure 26: Simulink – Load Min to Max, Vin = 425V........................................................... 36
Figure 27: Input Voltage Variation...................................................................................... 37
Figure 28: Simulink – Input Variation Rejection at Output.................................................. 38
Figure 29: Simulink – Output Voltage Ripple at Vin=425V and 15Vac Variation................ 39
Figure 30: Simulink – Vin = 200V....................................................................................... 40
Figure 31: Simulink – Output Voltage Ripple at Vin=200V................................................. 41
Figure 32: Simulink – Vin = 650V....................................................................................... 42
Figure 33: Simulink – Output Voltage Ripple at Vin=650V................................................. 43
List of Tables
Table 1: Converter Specification .......................................................................................... 4
Table 2: Comparison of SMPS Topologies .......................................................................... 5

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Abstract
This report outlines the design and analysis of a switch mode power supply. The
constraints are given by a set of customer’s specification, which could be described as a
wide input, high voltage, step-down power supply of mid range power. The topology
selected to support the requirements is a half-bridge DC-DC converter which includes an
isolating step-down transformer. For the purpose of this report, the transformer is
considered as an ideal component and is not analyzed in detail other than to define the
turns ratio. The analysis includes the derivation of the converter transfer function, large
signal ripple analysis (and component selection), a small signal model and development of
a voltage mode controller. The final design of the converter is simulated using
Matlab/Simulink to validate the circuit’s ability to achieve the customer’s specification.
Simulation results indicate a steady-state output voltage ripple of less than 100mV, and
stable control in the presence of significant load or line disturbances.
Introduction
Switch mode power supplies (SMPS) are used for DC-DC converters where a
simple linear regulator is not practical. The essential feature of a SMPS is a power switch,
typically a MOSFET or IGBT, which transitions between fully conducting to open circuit at a
very high rate. The pulsed waveform created from this high frequency switching is then
averaged across the output low pass filter network such that the desired output voltage is
achieved. In this manor a high efficiency, smaller volume and less heat generated can be
constructed. Due to the stringent converter specification, shown in table 1, it will be
necessary to take advantage of the SMPS features to meet the design goals.
Voltage input 200-650 VDC
Voltage output 28VDC, regulated
Full load power 300W
Minimums load 20% of full load
Ripple voltage ≤100mV at full load
Control loop bandwidth ≥5kHz (full load)
Control loop phase margin ≥45º (full load)
Table 1: Converter Specification

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For this converter, the high peak input voltage and wide input voltage range are items that
will be challenging to meet. Typical component reverse blocking ratings for MOSFETs, for
example, are 600V with some limited availability at 1200V. Clearly any component on the
front end will have to be adequately suited for high voltage application. Since the converter
has only one main control variable, duty-cycle, then in order to maintain a constant output
voltage in the presence of a wide input voltage range, the duty-cycle will also have a wide
operating range. However, it is important to keep in mind that the duty-cycle control range,
for practical reasons, should leave a 10% margin at the extreme ends to account for
converter variability due to component tolerance and operating temperature effects, etc. As
will be seen in the following sections, careful selection of the component rating and
converter topology will address these concerns.
Converter Topology Selection
The various arrangements of the components, and their operation, will dictate the
converter characteristics which give rise to many different SMPS topologies, such as buck,
isolated Flyback and bridge converters. It is the strategic placing of the components that
will expose them to certain electrical and thermal stress which translates to volume, weight
and cost of the overall system. In an effort to minimize the key drivers of volume weight
and cost, the designer is forced to find a balance between converter performance and
customer satisfaction. Some selected topologies and their inherit capabilities are listed in
the table below.
Table 2: Comparison of SMPS Topologies
The major factors that determine the optimum choice of topology are:
1. Is transformer isolation needed from input to output?
2. What is the peak current through the power switches?
3. What is the maximum operating voltage across the power switches?
Justification of an isolation transformer for this design is given for two reasons,
safety and step-down capability. Although the output voltage of 28V is in the “safe range”

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the input voltage is well beyond anything that you would want to come in contact with.
Therefore, galvanic isolation provided by a transformer would be appreciated. Additionally,
the transformer allows one to set a turns-ratio to assist with large difference between input
and output voltages, as is the case in this design.
With the full load power of 300W and a minimum input voltage of 200V, an estimated
peak switch current is, roughly, 2A. Considering current ripple and component derating
practices the selection of device rating should be between 5A to 10A at 75°C.
The peak input voltage of 650V is another matter. For reliability purposes it is
common practice to de-rate power switch devices by as much as 50% when the input
voltage is high. The standard value greater than 650V that meets the required safety
margin would be a device with 1200V blocking capability. As a special note, the designer
has elected to maintain this practice even if such voltage splitting topologies as the half-
bridge is adopted (the switch voltage stress being ½*Vin in this case). The reason given is
to avoid catastrophic destruction of the device and power supply in the event of (hopefully)
rare failure modes.
Referring to the given converter specifications in table 1, the information provided in
table 2 and the current discussion, one can see that the optimal solution is narrowed down
to the half-bridge or push-pull topology. Further reading on the subject of SMPS reveals
that the push-pull topology can by “tricky” due to transformer flux balance requirements and
other issues. Although it was assumed from the outset that the transformer is considered
to be ideal, it is nevertheless good practice to avoid unnecessary complication wherever
possible.
Therefore, the final DC-DC converter topology selected for this design is the isolated Half-
Bridge SMPS.

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The Isolated Half-Bridge SMPS
The electrical block diagram from the converter is given in the figure below.
Figure 1: Half-Bridge SMPS Diagram
Figure 2: Timing Diagram
The timing diagram for a half-bridge converter is split over one period because this
topology has two switches. Therefore, it is often convenient to discuss the operation of the
converter only in terms of ton, so D’ must be rewritten as follows:

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*note:
2
' (1 ) 1 1 2
2
on on
t Ts t
D D D
Ts Ts
−
= − = − = = −
⎛ ⎞
⎜ ⎟
⎝ ⎠
Due to the inherent symmetry between the turn ON/OFF times of the switch it is not always
necessary to evaluate the circuit over the entire switching period, but rather just half.
Finally, it should be noted that this converter topology will limit the maximum possible duty
cycle to 50%. As can be seen in the timing diagram, if the duty-cycle were to exceed 50%
there would be a period of overlap between and thus both switching devices would be
turned-ON simultaneously. This would cause a “shoot-through” condition for the bridge
which appears as a short circuit to the DC input bus, and should be strictly avoided.
Therefore, the maximum limit of the duty-cycle must be limited to 45% (rather than the
theoretical 50%) to accommodate any circuit variation.

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Converter Analysis
Large Signal Analysis
Assumptions:
- Capacitor Cb is very large such that Vcb = 0V
- All components, including the transformer, are considered ideal
Mode 1: 0 ≤ t < t1
Q1 is ON Q2 is OFF D3 is ON D4 is OFF
In this mode energy is being transferred from the supply to the load, iLO↑
Figure 3: Mode 1 Diagram

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( )
( )
( ) ( )*
( ) ( ) ( )
1
( ) ( * * ( )) ( )
2
( )
( ) ( )
( ) ( )
p
s
s p
Lo o oi
Lo i o
o
Co Lo
i i
v t Np
v t Ns
Ns
v t v t
Np
v t v t v t
Ns
v t v t v t
Np
v t
i t i t
R
i t i t
=
=
= − +
= −
= −
=
Note: @ Q1=ON,
( )
( )
2
( )
( ) ( ) *
2
i
p
i
oi s
v t
v t
v t Ns
v t v t
Np
=
= =
By small ripple approximation
Equation 1 1
( ) ( * * ( ) ) ( )
2
Lo i TS o TS
Ns
v t v t v t
Np
= 〈 〉 − 〈 〉
Equation 2 ( )
( ) ( ) o TS
Co Lo TS
v t
i t i t
R
〈 〉
= 〈 〉 −
Equation 3 ( ) ( )
i i TS
i t i t
= 〈 〉
Mode 2: t1 ≤ t < t2
Q1 is OFF Q2 is OFF D3 is ON D4 is ON
The spike voltage is clamped by D2.

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( ) 0
( ) 0
( )
( ) ( )
( )
( ) ( )
( ) 0
p
s
Lo
Lo o
o
Co Lo
i
v t
v t
i t
v t v t
v t
i t i t
R
i t
=
=
∴ ↓
= −
= −
=
Inductor current is decreasing
Equation 4 ( ) ( )
Lo o TS
v t v t
= −〈 〉
Equation 5 ( )
( ) ( ) o TS
Co Lo TS
v t
i t i t
R
〈 〉
= 〈 〉 −
Equation 6 ( ) 0
i
i t =
Mode 3: t2 ≤ t < t3
Q1 is OFF Q2 is ON D3 is OFF D4 is ON
In this mode energy is being transferred from the supply to the load, iLO↑

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( ) ( )*
( ) ( ) ( )
1
( ) ( * * ( )) ( )
2
( )
( ) ( )
( ) ( )
s p
Lo o oi
Lo i o
o
Co Lo
i i
Ns
v t v t
Np
v t v t v t
Ns
v t v t v t
Np
v t
i t i t
R
i t i t
= −
= − +
= −
= −
=
Note: @ Q1=ON,
1
( ) ( )
2
p i
v t v t
= −
And due to rectification
( )
( ) ( ) *
2
i
oi s
v t Ns
v t v t
Np
= = +
Equation 7 1
( ) ( * * ( ) ) ( )
2
Lo i TS o TS
Ns
v t v t v t
Np
= 〈 〉 − 〈 〉
Equation 8 ( )
( ) ( ) o TS
Co Lo TS
v t
i t i t
R
〈 〉
= 〈 〉 −
Equation 9 ( ) ( )
i i TS
i t i t
= 〈 〉
Mode 4: t3 ≤ t < t4
Q1 is OFF Q2 is OFF D3 is ON D4 is ON
The spike voltage is clamped by D1.

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( ) 0
( ) 0
( )
( ) ( )
( )
( ) ( )
( ) 0
p
s
Lo
Lo o
o
Co Lo
i
v t
v t
i t
v t v t
v t
i t i t
R
i t
=
=
∴ ↓
= −
= −
=
Inductor current is decreasing
Equation 10 ( ) ( )
Lo o TS
v t v t
= −〈 〉
Equation 11 ( )
( ) ( ) o TS
Co Lo TS
v t
i t i t
R
〈 〉
= 〈 〉 −
Equation 12 ( ) 0
i
i t =
Volt-Second Balance of Inductors:
o
L
〈 〉
( )
[ ]
1 2
( ) * * ( ) ( ) ( )
2
2
( )
( )
on on
Lo TS i TS o TS o TS
Lo TS
Lo TS o
Ns t Ts t
v t v t v t v t
Ts
Np Ts
d i t
v t L
dt
⎛ ⎞
⎡ ⎤ −
⎛ ⎞
⎜ ⎟
〈 〉 = 〈 〉 − 〈 〉 + −〈 〉 ⎜ ⎟
⎢ ⎥⎜ ⎟ ⎝ ⎠
⎣ ⎦
⎝ ⎠
〈 〉
〈 〉 =
Q
Equation 13
( ) [ ]( )
( ) 1
* * ( ) ( ) 2 ( ) ( ) 1 2 ( )
2
Lo TS
o i TS o TS o TS
d i t Ns
L v t v t d t v t d t
dt Np
⎡ ⎤
〈 〉
∴ = 〈 〉 − 〈 〉 + −〈 〉 −
⎢ ⎥
⎣ ⎦
( )
0
Lo TS
o
d i t
L
dt
〈 〉
= For large signal analysis
( ) [ ]( )
( ) [ ]( )
( ) ( )
1
0 * * ( ) ( ) 2 ( ) ( ) 1 2 ( )
2
1
* * ( ) ( ) 2 ( ) ( ) 1 2 ( )
2
1
* * ( ) * 2 ( ) ( ) * 2 ( ) ( ) ( ) *2 ( )
2
1
* * ( ) * 2 (
2
i TS o TS o TS
i TS o TS o TS
i TS o TS o TS o TS
i TS
Ns
v t v t d t v t d t
Np
Ns
v t v t d t v t d t
Np
Ns
v t d t v t d t v t v t d t
Np
Ns
v t d
Np
⎡ ⎤
∴ = 〈 〉 − 〈 〉 + −〈 〉 −
⎢ ⎥
⎣ ⎦
⎡ ⎤
〈 〉 − 〈 〉 = 〈 〉 −
⎢ ⎥
⎣ ⎦
〈 〉 − 〈 〉 = 〈 〉 − 〈 〉
〈 〉 ( )
) ( )
o TS
t v t
= 〈 〉
Equation 14
( ) ( ) * ( )
o TS i TS
Ns
v t v t d t
Np
∴〈 〉 = 〈 〉
Voltage
Transfer function for converter

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Charge-Balance of Capacitors:
o
C
〈 〉
( )
( ) ( ) 2
( ) ( ) ( )
2
( )
( )
o TS on o TS on
Co TS Lo TS Lo TS
Co TS
Co TS o
v t t v t Ts t
i t i t i t
Ts
R R Ts
d v t
i t C
dt
⎛ ⎞
〈 〉 〈 〉 −
⎡ ⎤ ⎡ ⎤⎛ ⎞
⎜ ⎟
〈 〉 = 〈 〉 − + 〈 〉 − ⎜ ⎟
⎢ ⎥ ⎢ ⎥
⎜ ⎟
⎣ ⎦ ⎣ ⎦⎝ ⎠
⎝ ⎠
〈 〉
〈 〉 =
Q
Equation 15
( ) ( )
( ) ( ) ( )
( ) 2 ( ) ( ) 1 2 ( )
Co TS o TS o TS
o Lo TS Lo TS
d v t v t v t
C i t d t i t d t
dt R R
〈 〉 〈 〉 〈 〉
⎡ ⎤ ⎡ ⎤
∴ = 〈 〉 − + 〈 〉 − −
⎢ ⎥ ⎢ ⎥
⎣ ⎦ ⎣ ⎦
( )
0
Co TS
o
d v t
C
dt
〈 〉
= For large signal analysis
( ) ( )
( ) ( ) ( )
( ) ( )
0 ( ) 2 ( ) ( ) 1 2 ( )
( ) ( )
( ) * 2 ( ) * 2 ( ) ( ) 1 2 ( )
( )
( ) * *
( )
2 ( ) 2 ( ) ( )
o TS o TS
Lo TS Lo TS
o TS o TS
Lo TS Lo TS
o TS
Lo TS
o TS
Lo TS Lo
v t v t
i t d t i t d t
R R
v t v t
i t d t d t i t d t
R R
v t
i t
R
v t
d t d t i t i
R
〈 〉 〈 〉
∴ = 〈 〉 − + 〈 〉 − −
〈 〉 〈 〉
〈 〉 − = − 〈 〉 − −
〈 〉
〈 〉 −
⎡ ⎤ ⎡ ⎤
⎢ ⎥ ⎢ ⎥
⎣ ⎦ ⎣ ⎦
⎡ ⎤
⎢ ⎥
⎣ ⎦
〈 〉
= −〈 〉 + + 〈
( )
( ) *2 ( ) *2 ( )
( )
0 ( )
o TS
TS
o TS
Lo TS
v t
t d t d t
R
v t
i t
R
〈 〉
〉 −
〈 〉
= −〈 〉 +
Equation 16 ( )
( ) o TS
Lo TS
v t
i t
R
〈 〉
∴〈 〉 =
Average output current
Source:
i
i
〈 〉
[ ]
( )
[ ]
2
( ) ( ) 0
2
on on
i TS i TS
t Ts t
i t i t
Ts Ts
⎛ ⎞
−
⎛ ⎞
⎜ ⎟
〈 〉 = 〈 〉 − ⎜ ⎟
⎜ ⎟ ⎝ ⎠
⎝ ⎠
Equation 17 [ ]( )
( ) ( ) 2 ( )
i TS i TS
i t i t d t
∴〈 〉 = 〈 〉
Note that the input current, and thus the current being conducted by the power switch, is
two times the average value. This is because the voltage applied across the device is half
as previously discussed.
Turns Ratio Selection
The turns ratio is determined by assuming that the nominal voltage for this converter is
exactly in the middle of the input voltage range, 425V. Then the duty-cycle, being limited to
45% is chosen to be exactly in the middle of its range or 22.5%. In this manor, the duty-

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cycle can be adjusted higher or lower in equal quantities to accommodate the input voltage
range of 200V to 650V.
Since the output of our converter is 28V, and given the voltage transfer function derived in
Equation 14, we can now select the appropriate turns-ratio as follows.
425
* 0.225* 3.415
28
@ 200 47.81%
i
o
i
V
Np
D
Ns V
check
V V D
= = =
= → =
But Dmax ≤ 45%
3.0 *
@ 200 42.00%
@ 650 12.92%
3 28
19.76%
1 425
i
o
i
i
nom
V
D
V
check
V V D
and
V V D
Np Vo
D
Ns Vi
=
= → =
= → =
= = =
set Np/Ns = 3.0 instead
Passed check!
Now,
Solve for nominal duty-cycle
With the transformer turns-ratio set to 3.0, it will be acting as a step-down transformer and
according to the converter specification, will require a very large but manageable duty-cycle
range.
Small Signal Analysis
The “Perturb and Linearize” method of small signal modeling will be used to construct the
equivalent circuit. To do this, a quiescent operating condition is assumed. Thus the
converter input voltage and duty-cycle can be expressed in their quiescent values plus the
small ac variation as follows.
ˆ
( ) ( )
ˆ
( ) ( )
ˆ
'( ) ' ( )
i TS i i
v t V v t
d t D d t
d t D d t
〈 〉 = +
= +
= −
Note:
ˆ
'( ) 1 ( )
ˆ
1 ( ( ))
ˆ
' ( )
d t d t
D d t
D d t
= −
= − +
= −
In response to the input and after all transients have decayed, the average converter
waveforms can also be expressed as quiescent values plus ac variations:

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ˆ
( ) ( )
ˆ
( ) ( )
ˆ
( ) ( )
o TS o o
Lo TS Lo Lo
i TS i i
v t V v t
i t I i t
i t I i t
〈 〉 = +
〈 〉 = +
〈 〉 = +
With these substitutions the large signal averaged equations become:
From Equation 13:
( )
( ) ( ) ( )
( ) ( )
[ ] ( )
( )
( ) ( )
ˆ ( ) 1 ˆ ˆ
ˆ ˆ ˆ
* * ( ) ( ) 2 ( ) ( ) 1 2 ( )
2
ˆ ( )
1
2 2 2
2
1 1
ˆ ˆ ˆ
ˆ ˆ ˆ
( )2 ( )2 2 ( ) 2 ( ) ( ) 2 (
2 2
Lo Lo
o i i o o o o
Lo
Lo
o o
i o o o
i o o i o o
d I i t Ns
L V v t V v t D d t V v t D d t
dt Np
d i t
d I
L L
dt dt
Ns
V D V D V V D DC terms
Np
Ns Ns
v t D v t D V d t V d t v t V d
Np Np
+
= + − + + + − + − +
⎡ ⎤
⎢ ⎥
⎣ ⎦
+ =
⎡ ⎤
− − + + ↔
⎢ ⎥
⎣ ⎦
− − + − + ˆ
) ( )2 1
1 ˆ ˆ ˆ
ˆ ˆ ˆ
( )2 ( ) ( )2 ( ) ( )2 ( ) 2
2
st
o
nd
i o o
t v t D order te
Ns
v t d t v t d t v t d t order terms
Np
⎡ ⎤
+ + ↔
⎢ ⎥
⎣ ⎦
⎡ ⎤
− + ↔
⎢ ⎥
⎣ ⎦
which simplifies to:

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Collecting DC terms
Equation 18
( )
( )
1
2 2 2
2
Lo
o
Lo
o
i o o o
i o
d I
L
dt
d I
L
dt
Ns
V D V D V V D
Np
Ns
V D V
Np
⎡ ⎤
= − − +
⎢ ⎥
⎣ ⎦
= −
o i
Ns
V V D
Np
∴ = note this is the same as Equation 14
Collecting 1st
order terms
Equation 19
( )
( )
ˆ ( ) 1 1
ˆ ˆ ˆ
ˆ ˆ ˆ ˆ
( )2 ( )2 2 ( ) 2 ( ) ( ) 2 ( ) ( )2
2 2
ˆ ( )
ˆ
ˆ ˆ
( ) ( ) ( )
Lo
o i o o i o o o
Lo
o i i o
d i t Ns Ns
L v t D v t D V d t V d t v t V d t v t D
dt Np Np
d i t Ns Ns
L v t D V d t v t
dt Np Np
= − − + − + +
= + −
⎡ ⎤
⎢ ⎥
⎣ ⎦
Collecting 2nd
order terms
Equation 20
1 ˆ ˆ ˆ
ˆ ˆ ˆ
( )2 ( ) ( )2 ( ) ( )2 ( )
2
ˆ
ˆ ( ) ( )
i o o
i
Ns
v t d t v t d t v t d t
Np
Ns
v t d t
Np
⎡ ⎤
− +
⎢ ⎥
⎣ ⎦
∴
and from Equation 15
( )
( )
( )
( )
( ) ( )
( )
( )
( )
( ) ( )
ˆ ˆ ˆ
( ) ( ) ( )
ˆ ˆ
ˆ ˆ
( ) 2 ( ) ( ) 1 2 ( )
ˆ ( )
2
ˆ ˆ
ˆ ˆ
2 ( ) 2 ( ) ( )
2 2 2
ˆ ( )
2 2
o o o o o o
o Lo Lo Lo Lo
o o
o o
Lo Lo Lo
Lo Lo Lo
o o o
o o
d V v t V v t V v t
C I i t D d t I i t D d t
dt R R
d V d v t
C C
dt dt
DI I I DC terms
Di t D d t I d t i
V V V
D D D
R R R
v t V
R R
+ + +
= + − + + + − − +
+ ↔
−
⎡ ⎤ ⎡ ⎤
⎢ ⎥ ⎢ ⎥
⎣ ⎦ ⎣ ⎦
+ =
⎡ ⎤
− + − − +
⎢ ⎥
⎣ ⎦
+ − + ˆ
( ) ( )
1
ˆ ˆ
2 ( ) ( )
ˆ ˆ ˆ ˆ
ˆ ˆ
( ) ( ) ( ) ( ) ( ) ( ) 2
ˆ ( )
2
ˆ ( )
2 2
ˆ ˆ
( ) ( )
2 2 2 2
Lo
st
Lo
nd
Lo Lo
o
o o
o o
t i t
order terms
D d t I d t
d t i t d t d t i t d t order terms
v t
D
R
v t V
R R
v t v t
R R
− +
+ ↔
+
− + ↔
⎡ ⎤
−
⎢ ⎥
⎢ ⎥
⎢ ⎥
− +
⎣ ⎦
⎡ ⎤
−
⎢ ⎥
⎣ ⎦

of 48
Collecting DC terms
Equation 21
( )
( )
2 2 2 2
o o o o
o Lo Lo Lo
o o
o Lo
d V V V V
C DI D I DI D
dt R R R
d V V
C I
dt R
⎡ ⎤
= − + − − +
⎢ ⎥
⎣ ⎦
= + −
o
Lo
V
I
R
Collecting 1st
order terms
Equation 22
( )
( )
ˆ ˆ
( ) ( )
ˆ ˆ
ˆ ˆ ˆ
2 ( ) 2 2 ( ) 2 ( ) ( ) 2 ( )
ˆ ( )
ˆ ( ) ˆ ˆ
2 2 ( ) 2 ( )
ˆ ( ) ˆ ( )
ˆ ( )
o o o
Lo Lo Lo Lo
o
o
o o
Lo
o o
o Lo
v t V v t
Di t D d t I d t i t Di t
d v t R R R
C
v t V
dt
D d t I d t
R R
d v t v t
C i t
dt R
⎡ ⎤
− + − + − − +
⎢ ⎥
= ⎢ ⎥
⎢ ⎥
+ − +
⎢ ⎥
⎣ ⎦
⎡ ⎤
= −
⎢ ⎥
⎣ ⎦
Collecting 2nd
order terms
Equation 23
ˆ ˆ ˆ ˆ
ˆ ˆ
( ) ( ) ( ) ( ) ( ) ( )
ˆ ˆ
( ) ( )
2 2 2 2
0
Lo Lo
o o
d t i t d t d t i t d t
v t v t
R R
− +
⎡ ⎤
−
⎢ ⎥
⎣ ⎦
∴
and from Equation 17
( ) ( ) ( )
[ ]
ˆ
ˆ ˆ
( ) ( ) 2 ( )
ˆ( )
2
ˆ
ˆ
2 ( ) 2 ( ) 1
ˆ
ˆ( ) ( ) 2
i i i i
i i
i
st
i i
nd
i
I i t I i t D d t
I i t
I D DC terms
Di t d t I order terms
i t d t order terms
+ = + +
+ =
+ ↔
⎡ ⎤
+ + ↔
⎣ ⎦
⎡ ⎤ ↔
⎣ ⎦

of 48
Collecting DC terms
Equation 24 [ ]
2
i i
I I D
=
2
i i
I I D
Collecting 1st
order terms
Equation 25
ˆ
ˆ ˆ
( ) 2 ( ) 2 ( )
ˆ( ) ˆ
ˆ( ) ( )
2
i i i
i
i i
i t Di t d t I
i t
Di t d t I
⎡ ⎤
= +
⎣ ⎦
= +
Collecting 2nd
order terms
Equation 26
ˆ
ˆ( ) ( )
ˆ
ˆ( ) ( )
i
i
i t d t
i t d t
⎡ ⎤
⎣ ⎦
∴
In order to formulate the equivalent circuits the following simplifying statements are made:
• The DC terms contain no time varying quantities
• The 1st
order ac terms are linear functions of the ac variation
• The 2nd
order ac terms are functions of the product of the ac variation and are
therefore very small (recall small ripple assumption)
The inductor ac variation small signal model is derived from the 1st
order ac terms of
Equation 19, and repeated here for convenience.
( )
ˆ ( )
ˆ
ˆ ˆ
( ) ( ) ( )
Lo
o i i o
d i t Ns Ns
L v t D V d t v t
dt Np Np
= + −
Low frequency
ac voltage
across inductor
Driven by duty-
cycle variation
and modeled as
an independent
source
Dependent
source
Variation in
output voltage
This equation is modeled as:
Figure 7: Output Inductor Differential Equation Modeled
The capacitor ac variation small signal model is derived from the 1st
order ac terms of

of 48
( )
ˆ ( ) ˆ ( )
ˆ ( )
o o
o Lo
d v t v t
C i t
dt R
= −
Low frequency ac
current in capacitor
Variation
in current
Ac component
of output
current,
modeled as a
resistor
Figure 8: Output Capacitor Differential Equation Modeled
The input current ac variation small signal model is derived from the 1st
order ac terms of
ˆ( ) ˆ
ˆ( ) ( )
2
i
i i
i t
Di t d t I
= +
Small ac
current
variation,
modeled
as a
voltage
source
Dependent
source
Driven by
duty-cycle
variation,
modeled as
an
independent
source
Note that ½ Vin would produce twice the current for same power
Figure 9: Input Current Equation Modeled
Now the three small signal models can be combined into one circuit.

of 48
Figure 10: Half-Bridge Small Signal Model
Since the dependent sources can be modeled as an ideal transformer; then the small
signal equivalent model of the half-bridge converter in CCM is:
Figure 11: Half-Bridge Small Signal Model (simplified)
Component Selection
The output inductor and capacitor values were originally calculated by study of the
large signal ripple analysis. Under maximum input voltage condition, the minimum inductor
Lo value was determined to maintain constant current mode. Similarly for the output
capacitor, a worse case was assumed and the output capacitor value was calculated to
maintain the specification ∆Vo ≤ 100mV.
It was found however, that the best method of choosing the output filter components
was to get “ball park” numbers from the method outlined above and then fine tune the
values in the simulation. The reason for this approach was that it was simply much faster
and provided more confidence, especially when there are many conditions to check, such
as minimum input voltage with AC ripple on the input etc etc.
The final selection for the output filter components was determined to be:
100
220
o
o
L uH
and
C uH
=
=
Note that the inductor must be current rated for the application (approx. 20Amps would be
sufficient) and the capacitor must be voltage rated for the application (approx. 100V rated
part).

of 48
Controller Design
To control the Half-bridge converter a voltage mode feedback regulator was chosen,
primarily for its ease of implementation, stable performance and ability to meet the
specification. A diagram of the half-bridge converter including the feedback controller is
shown in the following figure.
Figure 12: Converter & Controller Diagram
The object of the feedback controller is to maintain a constant 28V output over the input
voltage range and load change (20% minimum). For this project, the reference signal, Vref,
is 5V and Vm is 4.
Sensor Gain
If we assume a really good controller, then Vo = 28v with no error.
5
e ref
ref
v v H
H v v
= −
∴ = =

of 48
So we should chose:
5
0.17857
28
ref
o
v
H
v
= = =
Line-to-Output
The line-to-output transfer function in normalized form for a converter operating in CCM is:
2
ˆ ( ) 1
( )
ˆ
ˆ ( ) ( ) 0
1
o
vi io
i
o o
v s
G s G
v s d s s s
Qω ω
= =
= ⎛ ⎞
+ + ⎜ ⎟
⎝ ⎠
Now solve for the variables. From the small signal model, with ˆ( ) 0
d s =
Figure 13: Half-Bridge Small Signal Model (d = 0)
To simplify the analysis the source is reflected to the load side, the elements are
transformed into the Laplace form and the circuit becomes:
Figure 14: Line-to-Output Circuit Model (d = 0)
By steady-state analysis, the circuit transfer function can be determined.

of 48
2
2 1
2
*
1
1
ˆ ( )
* *
ˆ
ˆ ( ) 1
0
1
ˆ ( ) 1
*
ˆ
ˆ ( ) 0 1
o
o o
i
o o
o o
o
o
i
o o
from
z
Vo Vi
z z
then
R
R
sRC
v s Ns Ns
sC
D D
v s Np Np
R
d
R sL sL
sC sRC
v s Ns
D
L
v s Np
d s s L C
R
=
+
⎛ ⎞
⎜ ⎟
+
⎝ ⎠
→ =
⎛ ⎞ ⎛ ⎞
=
+ +
⎜ ⎟ ⎜ ⎟
+
⎝ ⎠ ⎝ ⎠
∴ →
= + +
Now match this with the line-to-output transfer function in normalized form.
6 6
6
6
8 2 5
1
0.1976 0.06587
3
1 1
6.742 / 1.073
100 220
220
2.61 =3.871
100
0.06587
( )
2.2 3.827 1
io
o o
o o
o
o
vi
Ns
G D
Np
krad s or f kHz
L C e e
C e
Q R
L e
G s
e s e s
ω − −
−
−
− −
= = =
= = = =
= =
∴ =
+ +
The bode plot of Gvi(s) is shown below.
-80
-70
-60
-50
-40
-30
-20
-10
Magnitude
(dB)
10
2
10
3
10
4
10
5
-180
-135
-90
-45
0
Phase
(deg)
Gvi(s)
Frequency (rad/sec)
Figure 15: Bode Plot of Gvi(s)

of 48
Control-to-Output
The control-to-output transfer function in normalized form for a converter operating in CCM
is:
2
1
ˆ ( )
( )
ˆ ˆ ( ) 0
( )
1
z
o
vi do
i
o o
s
v s
G s G
v s
d s s s
Q
ω
ω ω
⎛ ⎞
−
⎜ ⎟
⎝ ⎠
= =
= ⎛ ⎞
+ + ⎜ ⎟
⎝ ⎠
Now solve for the variables. From the small signal model, with ˆ ( ) 0
i
v s =
To simplify the analysis the source is reflected to the load side, the elements are
transformed into the Laplace form and the circuit becomes:
Figure 16: Control-to-Output Circuit Model (vi = 0)
By steady-state analysis, the circuit transfer function can be determined.
2
2 1
*
1
ˆ ( )
*
ˆ ˆ ( ) 0
( )
1
1
ˆ ( )
*
ˆ ˆ ( ) 0
( )
1
o
o o
i
o
o
o
o o
i
o
o
from
z
Vo Vi
z z
then
R
sRC
v s V
v s D
d s R
sL
sRC
R
sRC
v s V
v s D
d s R
sL
sRC
=
+
⎛ ⎞
⎜ ⎟
+
⎝ ⎠
→
= ⎛ ⎞
+
⎜ ⎟
+
⎝ ⎠
⎛ ⎞
⎜ ⎟
+
⎝ ⎠
∴ →
= ⎛ ⎞
+
⎜ ⎟
+
⎝ ⎠
Now match this with the line-to-output transfer function in normalized form.

of 48
6 6
6
6
8 2 5
28
141.700
0.1976
1 1
6.742 / 1.073
100 220
220
2.61 =3.871
100
141.7
( )
2.2 3.827 1
o
do
o o
o o
o
o
vd
V
G
D
krad s or f kHz
L C e e
C e
Q R
L e
G s
e s e s
ω − −
−
−
− −
= = =
= = = =
= =
∴ =
+ +
The bode plot of Gvd(s) is shown below.
-10
0
10
20
30
40
50
60
Magnitude
(dB)
10
2
10
3
10
4
10
5
-180
-135
-90
-45
0
Phase
(deg)
Gvd(s)
Frequency (rad/sec)
Figure 17: Bode Plot of Gvd(s)

of 48
Uncompensated Loop Gain
Now we are ready to take a look at the transfer function of our system to see how it would
respond if we "did nothing".
0 2
0
0
( ) ( ) ( ) 1
( ) *
1
1 1
1* * * 1 *141.7*0.1786 6.3259
4
20log(6.3259) 16.0225
c vd
u u
M
o o
u do
M
u dB
G s G s H s
T s T
V s s
Q
where
T G H
V
T dB
ω ω
= =
⎛ ⎞ ⎛ ⎞
+ +
⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠
= = =
= =
The compensator gain is set to
unity, i.e. Gc(s) = 1
The uncompensated loop gain can now be bode plotted.
-40
-30
-20
-10
0
10
20
30
Magnitude
(dB)
10
2
10
3
10
4
10
5
-180
-135
-90
-45
0
Phase
(deg)
Tu(s)
Frequency (rad/sec)
Figure 18: Uncompensated Loop Bode Plot – Tu(s)
A couple of general statements that could be made of this transfer function are that the
cross-over frequency of ~20kHz exceeds the specification but is not too high, unfortunately
the phase margin is rather poor at this frequency. Hence the need for a compensating
function which will be explored in the following section.

of 48
Compensator Loop Gain
In order to modify the uncompensated transfer function such that its overall characteristics
are somewhat more desirable, the author has elected to use a PID approach. The PID
compensator is a combination of a lead and lag network which takes advantage of an
improved phase margin (PD) and to reject low frequency disturbances while minimizing the
steady-state error (PI). An inverted ZERO is added to the loop gain at frequency fL. If ‘fL’ is
sufficiently lower than the loop cross-over frequency fc, then the phase margin is
unchanged.
( )
( )
( )
( )
( )
( )
( )
( )
0
0.1 500
1 sin 52
3.7393
1 sin 52
1 sin 52
10.860
1 sin 52
0.5868 4.6303
L c
o
z c
o
o
p c
o
z
c
p
f f Hz
f f kHz
f f kHz
f
G or dB
f
= =
⎛ ⎞
−
⎜ ⎟
= =
⎜ ⎟
+
⎜ ⎟
⎝ ⎠
⎛ ⎞
+
⎜ ⎟
= =
⎜ ⎟
−
⎜ ⎟
⎝ ⎠
= = −
Inverted zero frequency
Compensator zero frequency
Compensator pole frequency
Low frequency compensator gain
To obtain a compensator gain such that Tu0 = 0dB at the desired cut-off frequency fc, then
the midband frequency compensation gain must be:
2
0
0
1
( ) c
cm c
o u
f
G s G
f T
⎛ ⎞
= ⎜ ⎟
⎝ ⎠
Now the compensator transfer function can be written in full.
1 1
( ) ( )
1
L
z
c cm
p
s
s
G s G s
s
ω
ω
ω
⎛ ⎞⎛ ⎞
+ +
⎜ ⎟
⎜ ⎟
⎝ ⎠
⎝ ⎠
=
⎛ ⎞
+
⎜ ⎟
⎜ ⎟
⎝ ⎠
For a PID type Compensation

of 48
The bode plot for the compensator transfer function is given below.
5
10
15
20
25
30
35
40
Magnitude
(dB)
10
2
10
3
10
4
10
5
10
6
-90
-45
0
45
Phase
(deg)
Gc(s)
Frequency (rad/sec)
Figure 19: Compensator Loop Bode Plot – Gc(s)
Closed Loop Performance
The compensator operates on the loop transfer function Tu(s) to generate an overall closed
loop transfer function T(s).
2 4
13 4 8 3 5 2
1
( ) ( ) ( )
0.0005423 14.44 4.003
( )
3.224 2.256 5.292
c vd
M
T s G s G s H
V
s s e
T s
e s e s e s s
− − −
⎛ ⎞
= ⎜ ⎟
⎝ ⎠
+ +
=
+ + +
And since this transfer function is pretty much gibberish, it is again bode plotted to make
more sense.

of 48
-60
-40
-20
0
20
40
60
Magnitude
(dB)
10
2
10
3
10
4
10
5
10
6
-180
-135
-90
-45
0
Phase
(deg)
T(s)
Frequency (rad/sec)
Figure 20: Closed Loop Bode Plot – T(s)

of 48
It is also usfull to plot the transfer functions showing the effects of feedback for
1
1 ( )
T s
+
-60
-50
-40
-30
-20
-10
0
10
Magnitude
(dB)
10
2
10
3
10
4
10
5
10
6
0
45
90
135
180
Phase
(deg)
1/(1+T(s))
Frequency (rad/sec)
( )
1 ( )
T s
T s
+ -60
-50
-40
-30
-20
-10
0
10
Magnitude
(dB)
10
3
10
4
10
5
10
6
-180
-135
-90
-45
0
Phase
(deg)
Ts/(1+Ts)
Frequency (rad/sec)

of 48
Simulation Validation
The models derived in the previous sections were simulated using Simulink; the circuit
diagram is shown below.
Figure 21: Simulink – Converter
The controller details are provided here. Note that the intention of this circuit is to produce
a modulated gating pattern that matches Figure 2: Timing Diagram.

of 48
Figure 22: Simulink – Pulse Width Modulation
To take a measure of the operation of this converter and feedback controller several screen
captures of the simulated results are provided.
The steady-state operation with two load transitions is shown here.
Vin = 425V, Rated load.
Figure 23: Simulink – Steady-state Operation

of 48
Zoom in on the output voltage ripple:
Figure 24: Simulink – Output Voltage Ripple, Vin = 425V

of 48
Figure 25: Simulink – Load Max to Min, Vin = 425V
During a load change from maximum to minimum (100% to 20%) with Vin = 425V.
The overshoot is approximately: 9%
The settling time is approximately: 2ms

of 48
Figure 26: Simulink – Load Min to Max, Vin = 425V
During a load change from minimum to maximum (20% to 100%) with Vin = 425V.
The undershoot is approximately: 7.5%
The settling time is approximately: 2ms

of 48
To evaluate the converters effectiveness at rejecting input variation, the converter was
simulated with an AC source connected in series with the input supply. The parameters of
the AC source was set to 15Vac_pp, 180Hz to represent rather large amount of variation
due to 3-phase rectification supply.
The input voltage variation and input current is shown in the following figure, along with the
transformer primary and secondary voltage.
Figure 27: Input Voltage Variation

of 48
Figure 28: Simulink – Input Variation Rejection at Output
The output regulation is maintained at 28V with an output voltage ripple of ≤100mV as
shown in the figure below.

of 48
Figure 29: Simulink – Output Voltage Ripple at Vin=425V and 15Vac Variation

of 48
Finally, the performance of the converter was established at minimum input voltage.
Vin = 200V.
Figure 30: Simulink – Vin = 200V

of 48
The output voltage ripple is maintain within the converter specification of 100mV.
Figure 31: Simulink – Output Voltage Ripple at Vin=200V

of 48
And at maximum input voltage.
Vin = 650V.
Figure 32: Simulink – Vin = 650V

of 48
The output voltage ripple is maintain within the converter specification of 100mV.
Figure 33: Simulink – Output Voltage Ripple at Vin=650V

of 48
Conclusions
The contents of this report outlined the detailed analysis of a Half-bridge DC/DC
switch mode power supply for the purpose of meeting the given specification (Table 1:
Converter Specification). In order to show this, the average steady-state conditions were
first. Next, the small signal model was developed which provided a means to understand
the operation of the circuit when exposed to circuit variation. From this knowledge, several
open and closed loop transfer functions were developed to demonstrate the suitability of
the chosen circuit parameters. Finally, the SMPS circuit and its closed loop controller were
both simulated using Simulink to provide evidence of meeting the specification. The
converter was also stressed by significant variation, such as a sudden load change, input
voltage variation and AC ripple on the input voltage. In all conditions it was shown that the
converter remained stable and regulated the output voltage to 28V.
This being said, there remains opportunity to improve. For example, if bandwidth of
this controller were reduced to 7kHz (for example) it may be possible to improve the
stability (phase margin) even further. Or the switching frequency and other items of the
design could be modified to try to better optimize the size and cost of the output filter
components.
The results of this converter design were simulated using Simulink. Many waveform
screen captures were presented in this document. For example, it was shown that the
output voltage ripple maintained the converter specification of being less than 100mV over
the entire range of input voltage and also at nominal input voltage but with a 15VACpp
180Hz variation (Figure 24, Figure 29, Figure 31, Figure 33).
The step change in load, from maximum to minimum and vice-versa was
demonstrated (for example, Figure 25 & Figure 26) over the entire voltage range. In all
cases, the overshoot/undershoot remained 10% or better and the settling time was
approximately 2ms.
In any engineering project there are countless different ways to meet the
specification and optimize the cost/weight/volume. The details of this report show a ‘first
pass’ effort which, although may not be the very best solution imaginable, is considered by
the author to be reasonable given the available schedule. It remains to be seen how this
converter actually performs on the bench, but the evidence provided in this report should
give the customer every confidence that it would ultimately be a successful product.

of 48
References
Brown, Marty; Power Supply Cookbook, 2ed., Newnes 2001
Brown, Marty; Practical Switching Power Supply Design, Academic Press, 1990.
Erickson, Robert and Maksimovic, Dragan; Fundamentals of Power Electroncis, 2ed,
Kluwer Academic Publishers
Xu, David; Course Notes for EE8408 Switch Mode Power Supplies, Ryerson University,
2007.
http://en.wikipedia.org/wiki/Switched-mode_power_supply

of 48
Appendix A
Matlab ‘M-file’
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% %
% Half Bridge Controller Design Project %
% By Sonny Lloyd %
% Copyright 2007 %
% %
% Method derived from text: "Fundamentals of Power Electronics 2nd ed" %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
clear all;
close all;
Vi=425; % VARIABLE: 200 <= Vi <= 650
Vo=28; % GIVEN: output voltage
fc=5e3; % GIVEN: cut-off frequency of controller
Po=300; % GIVEN: output power
phi=52; % target phase margin, 52 degrees
fsw=100e3; % switching frequency (Hz) set to 20 * fc
% From DC analysis of circuit
R=Vo^2/Po; % for 300W at 28V, R = 2.61
Ns=1; % step down transformer
Np=3; % step down transformer
D=0.1976 % for Vo = 28V at quiescent conditions
% and for informational purposes..
D_tf=Vo/Vi*Np/Ns; % Duty cycle value to maintain 28V output
Vo_tf=D_tf*Vi*(Ns/Np); % value should always work out to 28V
% From large ripple analysis
Lo=100e-6; % set greater than Lo_min to maintain CCM
Co=220e-6; % set greater than Co_min for Vo ripple voltage < 100mV
% From small signal analysis
Gi0=D*(Ns/Np); % Line-to-Output gain at DC
Gd0=Vo/D; % Control-to-Output gain at DC
wo=1/sqrt(Lo*Co);
fo=wo/(2*pi);
Q=R*sqrt(Co/Lo);
% s = TF('s') specifies the transfer function H(s) = s (Laplace variable)
s = tf('s'); % a useful function
% Begin constructing feedback controller system
Vref=5; % reference voltage
H=Vref/Vo; % sensor gain function
Vm=4; % modulation factor
Vc=D*Vm*(2); % quiescent value of the control voltage Vc
figure
Gvi=tf([Gi0],[1/(wo^2) 1/(Q*wo) 1]); % Line-to-Output transfer function
% computesthe gain margin Gm, the phase margin Pm, and the associated
% frequencies Wcg and Wcp, for the SISO open-loop model SYS
% (continuous or discrete)
[Gm,Pm,Wcg,Wcp]=margin(Gvi);
margin(Gvi) % Bode plot of function with phase & gain margins identified
title('Gvi(s)')
grid;
figure
Gvd=tf([Gd0],[1/(wo^2) 1/(Q*wo) 1]); % Control-to-Output transfer function
% computesthe gain margin Gm, the phase margin Pm, and the associated

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% frequencies Wcg and Wcp, for the SISO open-loop model SYS
[Gm,Pm,Wcg,Wcp]=margin(Gvd);
margin(Gvd) % Bode plot of function with phase & gain margins identified
title('Gvd(s)')
grid;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Now we are ready to take a look at the transfer function of our system
% to see how it would respond if we "did nothing". To do this we
% plot the "uncompensated" transfer function Tu(s).
%
% set compensator gain to unity, i.e. Gc(s) = 1
Tu0=(1)*(1/Vm)*Gd0*H
figure
% uncompensated loop transfer function
Tu=tf([Tu0],[1/(wo^2) 1/(Q*wo) 1]);
%
% computes the gain margin Gm, the phase margin Pm, and the associated
% frequencies Wcg and Wcp, for the SISO open-loop model SYS (continuous or
% discrete)
[Gm,Pm,Wcg,Wcp]=margin(Tu);
margin(Tu); %Bode plot of function with phase & gain margins identified
title('Tu(s)')
grid;
% at fc = 5kHz, the uncompensated loop gain is:
Tu=Tu0*(fo/fc)^2; % this is the value that we are trying to compensate for
% Now look at the transfer function and deside which compensation type
% controller is best suited to achieve goal of crossover at fc,
% with 52deg phase margine, and Tu0 = 0db. What type of compensator would
% do this?
% PD? PI? PID? Also must look at the phase margine to check for
% stability at this location. Each compensator method has its own
% characteristics that will define HOW it operates on the feedback signal.
%
% To enable a certain type of compensator, simply remove the "%" character
% from the line with the equations. Three controller choices given below.
%%%%%%%%%%%%% PD (lead compensator) %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% find the compensator pole/zero frequencies %
% convert degrees to radian: phi * pi / 180 %
% The zero at frequency fz adds phase lead in the vicinity of the crossover
% frequency.
%fz=fc*(sqrt((1-sin(phi*(pi/180))/(1+sin(phi*(pi/180)))))); %
%wz = 2*pi*fz; %
%fp=fc*(sqrt((1+sin(phi*(pi/180))/(1-sin(phi*(pi/180)))))); %
%wp = 2*pi*fp; %
% %
% to obatin a compensator gain such that Tu0 = 0dB at fc, the low %
% frequency compensator gain Gc0(s) must be: %
%Gc0=sqrt(fz/fp); % low frequency compensator gain %
%Gc=Gc0*(1+s/wz)/(1+s/wp) % Compensator transfer function for PD %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%% PI (lag compensator) %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% This type of compensator is used to increase the %
% low-frequency loop gain, such that the output is better regulated at %
% DC and at frequencies well below the loop crossover frequency. %
% %
% An inverted ZERO is added to the loop gain, at requency fL. If fL is %
% sufficiently lower than the lopp crossover frequency fc, %
% then the phase margin is unchanged. %
%fL=0.1*fc; %
%wL=2*pi*fL; %
%Gc0=fc/(Tu0*fo) % low frequency compensator gain %
%Gc=Gc0*(1+wL/s) % Compensator transfer function for PD %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%% PID (lead-lag compensator)%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% %

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% A combination of the PI and PD methods given above. %
% An inverted ZERO is added to the loop gain, at frequency fL. If fL is %
% sufficiently lower than the loop crossover frequency fc, %
% then the phase margin is unchanged. %
fL=0.1*fc; %
wL=2*pi*fL; %
%Gc0=fc/(Tu0*fo) % low frequency compensator gain %
% %
% find the compensator pole/zero frequencies %
% convert degrees to radian: phi * pi / 180 %
fz=fc*(sqrt((1-sin(phi*(pi/180))/(1+sin(phi*(pi/180)))))); %
wz = 2*pi*fz; %
fp=fc*(sqrt((1+sin(phi*(pi/180))/(1-sin(phi*(pi/180)))))); %
wp = 2*pi*fp; %
Gc0=sqrt(fz/fp); % low frequency compensator gain
% %
% to obatin a compensator gain such that Tu0 = 0dB at fc, the low %
% frequency compensator gain Gc0(s) must be: %
Gcm=Gc0*(fc/fo)^2*1/Tu0 % midband gain %
Gc=Gcm*(1+s/wz)*(1+wL/s)/(1+s/wp) %PID Compensator
figure
[Gm,Pm,Wcg,Wcp]=margin(Gc); % computes the gain margin Gm, the phase margin Pm,
% and the associated frequencies Wcg and Wcp,
% for the SISO open-loop model SYS
margin(Gc) % Bode plot of function with phase & gain margins identified
title('Gc(s)')
grid;
% The compensated close loop transfer function (eq. 9.53 from text)
T=Gc*(1/Vm)*Gvd*H;
figure
[Gm,Pm,Wcg,Wcp]=margin(T); % computes the gain margin Gm, the phase margin Pm,
margin(T) % Bode plot of function with phase & gain margins identified
title('T(s)')
grid;
%%%%%%%%%%%%%%%%%%%%%%
figure
[Gm,Pm,Wcg,Wcp]=margin(T/(1+T)); % computes the gain margin Gm, the phase margin Pm,
margin(T/(1+T)) % Bode plot of function with phase & gain margins identified
title('Ts/(1+Ts)')
grid;
figure
[Gm,Pm,Wcg,Wcp]=margin(1/(1+T)); % computes the gain margin Gm, the phase margin Pm,
margin(1/(1+T)) % Bode plot of function with phase & gain margins identified
title('1/(1+T(s))');
grid;

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