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GENERAL PRINCIPLES OF
PIPELINING
BY AWAB HUMAYUN
WASIQ ALI IRFAN
M.JUNAID SULTAN
Q: What’s actually Pipelining?
 Pipelining is a technique where multiple
instructions are overlapped during execution.
Pipeline is divided into stages and these stages
are connected with one another to form a pipe like
structure. Instructions enter from one end and exit
from another end. Pipelining increases the overall
instruction throughput.
Stages of PIPELINING:-
 Fetch loads an instruction from memory.
 Decode identifies the instruction to be executed.
 Execute processes the instruction and writes the
result back to a register.
 COMPUTATIONAL PIPELINING:
 It consists of some logic that performs a computation, followed by a register to hold
the results of this computation.
. On each 320 ps cycle, the system spends
300 ps evaluating a combinational logic
function and 20 ps storing the results in
an output register.
GENERAL PRINCIPLES OF PIPELINING.pptx
 DETAIL STUDY OF PIPELINE OPERATION:
 Three-stage pipeline timing.
The rising edge of the clock signal controls the movement of instructions from
one pipeline stage to the next.
 Nonuniform Partitioning:
 Limitations of pipelining due to nonuniform stage delays. The
system throughput is limited by the speed of the slowest stage.
GENERAL PRINCIPLES OF PIPELINING.pptx
THANKS FOR YOUR PATIENCE
;))

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GENERAL PRINCIPLES OF PIPELINING.pptx

  • 1. GENERAL PRINCIPLES OF PIPELINING BY AWAB HUMAYUN WASIQ ALI IRFAN M.JUNAID SULTAN
  • 2. Q: What’s actually Pipelining?  Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from one end and exit from another end. Pipelining increases the overall instruction throughput.
  • 3. Stages of PIPELINING:-  Fetch loads an instruction from memory.  Decode identifies the instruction to be executed.  Execute processes the instruction and writes the result back to a register.
  • 4.  COMPUTATIONAL PIPELINING:  It consists of some logic that performs a computation, followed by a register to hold the results of this computation. . On each 320 ps cycle, the system spends 300 ps evaluating a combinational logic function and 20 ps storing the results in an output register.
  • 6.  DETAIL STUDY OF PIPELINE OPERATION:  Three-stage pipeline timing. The rising edge of the clock signal controls the movement of instructions from one pipeline stage to the next.
  • 7.  Nonuniform Partitioning:  Limitations of pipelining due to nonuniform stage delays. The system throughput is limited by the speed of the slowest stage.
  • 9. THANKS FOR YOUR PATIENCE ;))