IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
Implementation and Performance Analysis of Kaiser and Hamming Window Techniqu...IJERA Editor
Considering the importance of real time filtering, a comparison was done between two prominent window
techniques known for digital filtering. A 16 tap digital band pass FIR filter is designed for each design technique
(Kaiser and Hamming) and implemented over FPGA. The Simulink model of the filter confirms the correctness
and other properties of the digital filter. Further a hardware descriptive code (VHDL) is generated for the
designed filter which then will be loaded on to the FPGA. The VHDL code is speed optimized. The VHDL code
is simulated and synthesized in Xilinx ISE. Further the performance analysis is done on FPGA to determine the
applicability of the filter.
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
An Extensive Literature Review on Reversible Arithmetic and Logical UnitIRJET Journal
This document provides a literature review on reversible arithmetic and logical units (ALUs). It discusses how reversible logic can be used to reduce power dissipation, one of the main requirements in low power digital design. Reversible logic gates like the Feynman gate, Fredkin gate, Toffoli gate, and HNG gate are described. Previous work on designing reversible ALUs is summarized, including designs using these reversible logic gates that achieve lower power consumption, quantum cost, and area. The document concludes by stating that novel programmable reversible logic gates have been used to design an 8-bit reversible ALU with low power consumption.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
Implementation and Performance Analysis of Kaiser and Hamming Window Techniqu...IJERA Editor
Considering the importance of real time filtering, a comparison was done between two prominent window
techniques known for digital filtering. A 16 tap digital band pass FIR filter is designed for each design technique
(Kaiser and Hamming) and implemented over FPGA. The Simulink model of the filter confirms the correctness
and other properties of the digital filter. Further a hardware descriptive code (VHDL) is generated for the
designed filter which then will be loaded on to the FPGA. The VHDL code is speed optimized. The VHDL code
is simulated and synthesized in Xilinx ISE. Further the performance analysis is done on FPGA to determine the
applicability of the filter.
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
An Extensive Literature Review on Reversible Arithmetic and Logical UnitIRJET Journal
This document provides a literature review on reversible arithmetic and logical units (ALUs). It discusses how reversible logic can be used to reduce power dissipation, one of the main requirements in low power digital design. Reversible logic gates like the Feynman gate, Fredkin gate, Toffoli gate, and HNG gate are described. Previous work on designing reversible ALUs is summarized, including designs using these reversible logic gates that achieve lower power consumption, quantum cost, and area. The document concludes by stating that novel programmable reversible logic gates have been used to design an 8-bit reversible ALU with low power consumption.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
This document summarizes an academic paper presented at the International Conference on Emerging Trends in Engineering and Management in 2014. The paper proposes a design and implementation of an elliptic curve scalar multiplier on a field programmable gate array (FPGA) using the Karatsuba algorithm. It aims to reduce hardware complexity by using a polynomial basis representation of finite fields and projective coordinate representation of elliptic curves. Key mathematical concepts like finite fields, point addition, and point doubling that are important to elliptic curve cryptography are also discussed at a high level.
Low complexity digit serial fir filter by multiple constant multiplication al...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
COUPLED FPGA/ASIC IMPLEMENTATION OF ELLIPTIC CURVE CRYPTO-PROCESSORIJNSA Journal
In this paper, we propose an elliptic curve key generation processor over GF(2163) scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the high efficiently of this implementation design.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A verilog based implementation of transcendental function calculator using co...eSAT Journals
Abstract The CORDIC (COordinate Rotation DIgital Computer) algorithm is an iterative algorithm developed by Volder [1] in 1959. It rotates the vector, iteratively and in finite steps to calculate Sine and Cosine of a given angle. Additional work has been done by Walther [2] in 1971. The main principle of CORDIC are calculations based on shift−registers and adders instead of multiplications, which makes use of limited reconfigurable CLB’s in FPGA efficiently saving hardware resources. All trigonometric functions can be computed using vector rotation. CORDIC is also used for polar to rectangular and rectangular to polar conversions, calculation of vector magnitude, and also for transforms like discrete Fourier transform (DFT)/FFT on reconfigurable platform. This paper presents the CORDIC Algorithm for calculation of elementary functions Sine and Cosine in IEEE-754 Format and Q-Format. The paper analyses the feasibility of CORDIC algorithm for implementing the elementary angle computation in FPGA .The CORDIC algorithm is implemented using Verilog language and results are obtained from Xilinx ISE simulation. Keywords: CORDIC, Elementary angle, FPGA, SDR, VHDL
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...IRJET Journal
This document describes the implementation of an effective self-timed multiplier for single precision floating point values using a carry-look ahead adder. It begins by introducing floating point representation and the need for floating point arithmetic in applications requiring a large dynamic range. It then discusses the IEEE 754 standard for single precision floating point format and the steps to multiply two floating point values. The key aspects of the proposed self-timed multiplier are that it uses a carry-look ahead adder to add the exponents, making the operation faster than a traditional ripple carry adder. VHDL is used to design and simulate the self-timed multiplier, which is shown to correctly perform multiplications under normal, overflow, and underflow conditions.
Low Power VLSI Design of Modified Booth Multiplieridescitation
Low power VLSI circuits became very vital criteria
for designing the energy efficient electronic designs for prime
performance and compact devices. Multipliers play a very
important role for planning energy economical processors that
decides the potency of the processor. To scale back the facility
consumption of multiplier factor booth coding methodology
is being employed to rearrange the input bits. The operation
of the booth decoder is to rearrange the given booth equivalent.
Booth decoder can increase the range of zeros in variety. Hence
the switching activity are going to be reduced that further
reduces the power consumption of the design. The input bit
constant determines the switching activity part that’s once
the input constant is zero corresponding rows or column of
the adder ought to be deactivated. When multiplicand contains
a lot of number of zeros the higher power reduction will takes
place. therefore in booth multiplier factor high power
reductions are going to be achieved.
This document summarizes a research paper about centralized PID control of a nonlinear boiler-turbine unit. The researchers applied a control by decoupling methodology to design a multivariable PID controller for the 3x3 boiler-turbine process, which has strong interactions and input constraints. They obtained the PID controller by approximating an ideal decoupler that includes integral action. Additional gains were tuned to improve performance. An anti-windup strategy was incorporated to handle input constraints and achieve better response. Simulation results showed good decoupled response and tracking, comparable or better than other controllers.
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
This document describes a novel design for a 32-bit unsigned multiplier using a modified carry select adder (MCSLA). It begins with background on adders and multipliers in VLSI design. It then describes the conventional carry select adder (CSLA) and proposes a modified CSLA (MCSLA) that uses common boolean logic to reduce area and power. The document presents the design and VHDL simulation results of a 32-bit unsigned multiplier using both CSLA and the proposed MCSLA. The results show the MCSLA based multiplier achieves a 45% reduction in power-area-delay product compared to the CSLA based multiplier.
Hardware Implementation of Two’s Compliment Multiplier with Partial Product b...IJERA Editor
With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, the multiplication is an essential arithmetic operation for common DSP applications, such as filtering, convolution, fast Fourier Transform (FFT) etc. To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. This paper presents an approach to reduce power consumption of 2’s compliment multiplier design, in which switching activities are reduced through dynamic by passing of partial products.
FPGA Implementation of SubByte & Inverse SubByte for AES Algorithmijsrd.com
Advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In traditional look up table (LUT) approaches, the unbreakable delay is longer than the total delay of the rest of operations in each round. LUT approach consumes a large area. It is more efficient to apply composite field arithmetic in the SubBytes transformation of the AES algorithm. It not only reduces the complexity but also enables deep sub pipelining such that higher speed can be achieved. Isomorphic mapping can be employed to convert GF(28) to GF(22)2)2) ,so that multiplicative inverse can be easily obtained. SubBytes and InvSubBytes transformations are merged using composite field arithmetic. It is most important responsible for the implementation of low cost and high throughput AES architecture. As compared to the typical ROM based lookup table, the presented implementation is both capable of higher speeds since it can be pipelined and small in terms of area occupancy (137/1290 slices on a Spartan III XCS200-5FPGA).
Performance Analysis of Reversible 16 Bit ALU based on Novel Programmable Rev...IRJET Journal
This document describes the design of a reversible 16-bit Arithmetic Logic Unit (ALU) using novel reversible logic gate structures to reduce power consumption. It presents the design of 1-bit arithmetic and logic units that are then extended to 16-bits. The arithmetic unit uses a Hagparast Navi gate as a reversible full adder along with Feynman and Fredkin gates. The logic unit uses Toffoli gates to perform logic operations. A reversible multiplexer combines the units. Simulation results show the reversible ALU reduces total power consumption by 5.12% compared to an irreversible design due to lower dynamic power, particularly in logic power which is reduced by 53.3%.
An Extended Approach for Online Testing of Reversible CircuitsIOSR Journals
: Reversible computing has tremendous benefits in terms of power consumption, less heat dissipation
and packaging density. Because its applications are found in diverse fields including quantum computing,
nanotechnology, low power CMOS designs and cryptography, Reversible computing has gained attraction of
many researchers recently. In order to incorporate fault testing capability in reversible circuits, a number of
offline and online approaches have been proposed. In order to extend online testability of reversible circuits, an
analysis followed by a Peres gate substitution is presented here. The proposed extension has identified online
testing capabilities of MCF gates and has made all available libraries including MCT+MCF, MCT+P online
testable. Furthermore a conversion for parity-preserving reversible circuits is presented. Finally the paper is
concluded by proposing a generic online testable substitution of n*n reversible gate
Robust PID Controller Design for Non-Minimum Phase Systems using Magnitude Op...IRJET Journal
This document discusses two approaches for designing a controller for non-minimum phase systems: 1) the magnitude optimum and multiple integration method, and 2) a numerical optimization approach. The magnitude optimum method uses areas calculated from the process step response to determine the PID controller parameters, eliminating the need to estimate process parameters directly. The numerical optimization approach formulates the controller design as an optimization problem to minimize sensitivity functions in the closed-loop system. Both approaches are presented as ways to design robust controllers for non-minimum phase systems.
A CORDIC based QR Decomposition Technique for MIMO Detection IJECEIAES
CORDIC based improved real and complex QR Decomposition (QRD) for channel pre-processing operations in (Multiple-Input Multiple-Output) MIMO detectors are presented in this paper. The proposed design utilizes pipelining and parallel processing techniques and reduces the latency and hardware complexity of the module respectively. Computational complexity analysis report shows the superiority of our module by 16% compared to literature. The implementation results reveal that the proposed QRD takes shorter lat ency compared to literature. The power consumption of 2x2 real channel matrix and 2x2 complex channel matrix was found to be 12mW and 44mW respectively on the state-of-the-art Xilinx Virtex 5 FPGA.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
Performance Study of BCH Error Correcting Codes Using the Bit Error Rate Term...IJERA Editor
The quality of a digital transmission is mainly dependent on the amount of errors introduced into the transmission channel. The codes BCH (Bose-Chaudhuri-Hocquenghem) are widely used in communication systems and storage systems. In this paper a Performance study of BCH error correcting codes is proposed. This paper presents a comparative study of performance between the Bose-Chaudhuri-Hocquenghem codes BCH (15, 7, 2) and BCH (255, 231, 3) using the bit error rate term (BER). The channel and the modulation type are respectively AWGN and PSK where the order of modulation is equal to 2. First, we generated and simulated the error correcting codes BCH (15, 7, 2) and BCH (255, 231, 3) using Math lab simulator. Second, we compare the two codes using the bit error rate term (BER), finally we conclude the coding gain for a BER = 10-4.
We looked at the data. Here’s a breakdown of some key statistics about the nation’s incoming presidents’ addresses, how long they spoke, how well, and more.
The document discusses how startup entrepreneurs think and operate. It notes that startups like Airbnb and Uber were started due to identifying shortages or problems. It emphasizes that startups focus on providing customer benefit, eliminating waste, and creating value. It also highlights that startups operate with speed, embracing failure fast and pivoting quickly, with transparency and by breaking rules. Startups succeed by moving rapidly, with minimal processes and instead prioritizing speed above all else.
This document discusses how emojis, emoticons, and text speak can be used to teach students. It provides background on the origins of emoticons in 1982 as ways to convey tone and feelings in text communications. It then suggests that with text speak and emojis, students can translate, decode, summarize, play with language, and add emotion to language. A number of websites and apps that can be used for emoji-related activities, lessons, and discussions are also listed.
Layout Design Analysis of CMOS Comparator using 180nm TechnologyIJEEE
Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
This document summarizes an academic paper presented at the International Conference on Emerging Trends in Engineering and Management in 2014. The paper proposes a design and implementation of an elliptic curve scalar multiplier on a field programmable gate array (FPGA) using the Karatsuba algorithm. It aims to reduce hardware complexity by using a polynomial basis representation of finite fields and projective coordinate representation of elliptic curves. Key mathematical concepts like finite fields, point addition, and point doubling that are important to elliptic curve cryptography are also discussed at a high level.
Low complexity digit serial fir filter by multiple constant multiplication al...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
COUPLED FPGA/ASIC IMPLEMENTATION OF ELLIPTIC CURVE CRYPTO-PROCESSORIJNSA Journal
In this paper, we propose an elliptic curve key generation processor over GF(2163) scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the high efficiently of this implementation design.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A verilog based implementation of transcendental function calculator using co...eSAT Journals
Abstract The CORDIC (COordinate Rotation DIgital Computer) algorithm is an iterative algorithm developed by Volder [1] in 1959. It rotates the vector, iteratively and in finite steps to calculate Sine and Cosine of a given angle. Additional work has been done by Walther [2] in 1971. The main principle of CORDIC are calculations based on shift−registers and adders instead of multiplications, which makes use of limited reconfigurable CLB’s in FPGA efficiently saving hardware resources. All trigonometric functions can be computed using vector rotation. CORDIC is also used for polar to rectangular and rectangular to polar conversions, calculation of vector magnitude, and also for transforms like discrete Fourier transform (DFT)/FFT on reconfigurable platform. This paper presents the CORDIC Algorithm for calculation of elementary functions Sine and Cosine in IEEE-754 Format and Q-Format. The paper analyses the feasibility of CORDIC algorithm for implementing the elementary angle computation in FPGA .The CORDIC algorithm is implemented using Verilog language and results are obtained from Xilinx ISE simulation. Keywords: CORDIC, Elementary angle, FPGA, SDR, VHDL
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...IRJET Journal
This document describes the implementation of an effective self-timed multiplier for single precision floating point values using a carry-look ahead adder. It begins by introducing floating point representation and the need for floating point arithmetic in applications requiring a large dynamic range. It then discusses the IEEE 754 standard for single precision floating point format and the steps to multiply two floating point values. The key aspects of the proposed self-timed multiplier are that it uses a carry-look ahead adder to add the exponents, making the operation faster than a traditional ripple carry adder. VHDL is used to design and simulate the self-timed multiplier, which is shown to correctly perform multiplications under normal, overflow, and underflow conditions.
Low Power VLSI Design of Modified Booth Multiplieridescitation
Low power VLSI circuits became very vital criteria
for designing the energy efficient electronic designs for prime
performance and compact devices. Multipliers play a very
important role for planning energy economical processors that
decides the potency of the processor. To scale back the facility
consumption of multiplier factor booth coding methodology
is being employed to rearrange the input bits. The operation
of the booth decoder is to rearrange the given booth equivalent.
Booth decoder can increase the range of zeros in variety. Hence
the switching activity are going to be reduced that further
reduces the power consumption of the design. The input bit
constant determines the switching activity part that’s once
the input constant is zero corresponding rows or column of
the adder ought to be deactivated. When multiplicand contains
a lot of number of zeros the higher power reduction will takes
place. therefore in booth multiplier factor high power
reductions are going to be achieved.
This document summarizes a research paper about centralized PID control of a nonlinear boiler-turbine unit. The researchers applied a control by decoupling methodology to design a multivariable PID controller for the 3x3 boiler-turbine process, which has strong interactions and input constraints. They obtained the PID controller by approximating an ideal decoupler that includes integral action. Additional gains were tuned to improve performance. An anti-windup strategy was incorporated to handle input constraints and achieve better response. Simulation results showed good decoupled response and tracking, comparable or better than other controllers.
A High Throughput CFA AES S-Box with Error Correction CapabilityIOSR Journals
The document describes a proposed method for implementing a fault tolerant Advanced Encryption Standard (AES) using a Hamming error correction code. AES operates by performing rounds of transformations on blocks of data, with the most complex step being the SubBytes transformation which involves calculating multiplicative inverses in GF(28). The proposed method uses composite field arithmetic to more efficiently calculate these inverses. It also applies a (12,8) Hamming error correction code to each byte before and after processing to detect and correct single bit errors caused by radiation events, improving reliability for satellite communications. The parity check bits for the Hamming code are precalculated and stored for the AES S-box lookup tables.
This document describes a novel design for a 32-bit unsigned multiplier using a modified carry select adder (MCSLA). It begins with background on adders and multipliers in VLSI design. It then describes the conventional carry select adder (CSLA) and proposes a modified CSLA (MCSLA) that uses common boolean logic to reduce area and power. The document presents the design and VHDL simulation results of a 32-bit unsigned multiplier using both CSLA and the proposed MCSLA. The results show the MCSLA based multiplier achieves a 45% reduction in power-area-delay product compared to the CSLA based multiplier.
Hardware Implementation of Two’s Compliment Multiplier with Partial Product b...IJERA Editor
With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, the multiplication is an essential arithmetic operation for common DSP applications, such as filtering, convolution, fast Fourier Transform (FFT) etc. To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. This paper presents an approach to reduce power consumption of 2’s compliment multiplier design, in which switching activities are reduced through dynamic by passing of partial products.
FPGA Implementation of SubByte & Inverse SubByte for AES Algorithmijsrd.com
Advanced encryption standard was accepted as a Federal Information Processing Standard (FIPS) standard. In traditional look up table (LUT) approaches, the unbreakable delay is longer than the total delay of the rest of operations in each round. LUT approach consumes a large area. It is more efficient to apply composite field arithmetic in the SubBytes transformation of the AES algorithm. It not only reduces the complexity but also enables deep sub pipelining such that higher speed can be achieved. Isomorphic mapping can be employed to convert GF(28) to GF(22)2)2) ,so that multiplicative inverse can be easily obtained. SubBytes and InvSubBytes transformations are merged using composite field arithmetic. It is most important responsible for the implementation of low cost and high throughput AES architecture. As compared to the typical ROM based lookup table, the presented implementation is both capable of higher speeds since it can be pipelined and small in terms of area occupancy (137/1290 slices on a Spartan III XCS200-5FPGA).
Performance Analysis of Reversible 16 Bit ALU based on Novel Programmable Rev...IRJET Journal
This document describes the design of a reversible 16-bit Arithmetic Logic Unit (ALU) using novel reversible logic gate structures to reduce power consumption. It presents the design of 1-bit arithmetic and logic units that are then extended to 16-bits. The arithmetic unit uses a Hagparast Navi gate as a reversible full adder along with Feynman and Fredkin gates. The logic unit uses Toffoli gates to perform logic operations. A reversible multiplexer combines the units. Simulation results show the reversible ALU reduces total power consumption by 5.12% compared to an irreversible design due to lower dynamic power, particularly in logic power which is reduced by 53.3%.
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1. Ganesh L K M, LopamudraPattanayak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.957-960
957 | P a g e
VLSI Testing Technique for BIST:Using Priority Based
Algorithm
Ganesh L K M*, LopamudraPattanayak**
(*AsstProfessor,,School of Electronics Engineering,KIIT University, Bhubaneswar,Odisha, INDIA)
(**M. Tech. VLSI Design and Embedded System ,,School of Electronics Engineering,KIIT University,
Bhubaneswar,Odisha, INDIA)
ABSTRACT
The paper presents a low test time BIST
based on Priority Algorithm (PA) is applied for
the 32-bit Carry Look-Ahead Adder. This
method assigns priority to the test patterns based
on faulty coverage and independent faulty
detecting test patterns. Experiment conducted on
Cadences’ RTL Compiler Tool and Cadences’
Encounter Tool demonstrate that proposed
scheme gives better performance with large
reduction in test time and power dissipation
during testing.
Keywords- BIST, LFSR, Priority Test Patterns,
Test Time
I. INTRODUCTION
Built-In Self-test (BIST) is the ability of an
integrated circuit (IC) to examine its own functional
health, in order to detect and report faults that may
jeopardize the reliability of the application wherein
it is deployed. The test time of a chip depends on the
types of tests conducted [1]. These may include
parametric tests (leakage, contact, voltage levels,
etc.) applied at a slow speed, and vector tests (also
called “functional tests” in the ATE environment)
applied at high speed. The time of parametric tests is
proportional to the number of pins since these tests
must be applied to all active pins of the chip. The
vector test time depends on the number of vectors
and the clock rate. The total test time for digital
chips ranges between 3 to 8 seconds. The vectors
may not cover all possible functions and data
patterns but must have a high coverage of modeled
faults. The main driver is cost, since every device
must be tested. Test time (and therefore cost) must
be absolutely minimized. During Test mode, power
consumption will double than normal mode [2].
This Priority Test Pattern method saves significant
test time and power consumption by shortening the
pattern sequence.
II. BIST STRUCTURE
Block Diagram of BIST is shown in
figure.1. BI is enable pin for BIST operation and BO
is output of BIST operation, based on BO only can
say whether given CUT is working properly are
not.When BI = 0, Test Pattern Generator and Ideal
Response Block are in OFF state. MUX will accept
Input and applied to CUT and outputs are taken at
Output pin. When BI = 1, Test Pattern Generator and
Ideal Response Block are in ON state. MUX will
accept Test Pattern Generator output and applied to
CUT and outputs are taken at BO pin. When BO is
1,indicates IC is working properly otherwise
malfunction is there in IC.
Fig 1.Block Diagram of BIST
III. PRIORITY ALGORITHM
If “n” is number of input present in digital
circuit and “M = 2n”
input vector is present. For n
input digital circuit, “F” is number of fault.
TABLE 1. LIST OF FAULT COVERED
Sl.No Input Vector
No of
Fault Covered
1 1st
Input Vector X1
2 2nd
Input Vector X2
.. …….. ………
M M Input Vector XM
Priorities are assigning as follows
1st
Priority Y1 = max (X1, X2, X3,……..XM )
2nd
Priority Y2 must select such that Y2
must cover maximum remaining fault (F – Y1). For
example, 100 faults are present in digital circuits and
first input pattern is covering maximum of 42 faults.
Second input patterns must select such that it must
cover maximum remaining fault (100 – 42 = 58).
3rd
Priority Y2 must select such that Y2 must
cover maximum remaining fault (F – Y1 – Y2) and
soon.
2. Ganesh L K M, LopamudraPattanayak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.957-960
958 | P a g e
Fig 2. Flow chart of Priority Algorithm
For example CLA is taken as CUT
• CLA is used in most ALU designs.
• It is faster compared to ripple carry logic
adders or full adders especially when adding a large
number of bits.
• The Carry Look Ahead Adder is able to
generate carries before the sum is produced using the
propagate and generate logic to make addition much
faster.
When BI is 1 and it will represented in a verilog
code with test timing insertion and after that it will
be simulated in Xilinx 9.2 version and the RTL
diagram of 32 bit CLA is show in figure
Fig 3. Test bench of 32 bit CLA
Fig 4.RTL diagram of 32 bit CLA
Four test patterns are sending to CLA (CUT) which
is independent to each other for fault detecting.
Total no of faults is 258(64*2+33*2+32*2)
1. No of fault coverage =66/258=25%
(Input A=8’h00000000, Input B=8’hFFFFFFFF
and Input Cin= 1’b0) stuck_at_1 at port A and port
Cin can be detected
2. No of fault coverage =66/258=25%
(Input A=8’hFFFFFFFF, Input B=8’h00000000
and Input Cin= 1’b0) stuck_at_1 at port B and port
Cin can be detected
3. No of fault coverage =66/258=25%
(Input A=8’h00000000, Input B= 8’hFFFFFFFF
and Input Cin = 1’b1)
stuck_at_0 at port B and port Cin can be detected
4. No of fault coverage =66/258=25%
(Input A=8’hFFFFFFFF, Input B= 8’h00000000
and Input Cin=1’b1)
stuck_at_0 at port A and port Cin can be detected.
Fig 5. Test bench of 32bit CLA using BIST
IV. SIMULATION RESULTS
Verilog codes were used to simulate the
test generation process performed using Cadences’
RTL complier Tool and Layout analysis is
performed using Cadences’ Encounter Tool.
1. Leakage power, dynamic power and total
power calculations in nW for 32-bit CLA, LSFR-
BIST and PA-BIST are shown in figure 6,7 and 8
respectively.
3. Ganesh L K M, LopamudraPattanayak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.957-960
959 | P a g e
Fig 6.Power Calculation of 32-bit CLA
Fig 7.Power Calculation of LSFR-BIST
Fig 8.Power Calculation of PA-BIST
2. No of Gates used to design of 32-bit CLA,
LSFR-BIST and PA-BIST are calculated and shown
in figure 9, 10 and 11 respectively.
Fig 9.Gates Calculation of 32-bit CLA
Fig 10. Gates Calculation of LFSR-BIST
Fig11.Gates Calculation of PA-BIST
3. Area of 32-bit CLA, LSFR-BIST and PA-
BIST are calculated and shown in figure12,13 and
14 respectively.
Fig 12. Area Calculation of 32-bit CLA
Fig 13.Area Calculation of LFSR-BIST
Fig 14.Area Calculation of PA-BIST
4. Layouts of LFSR-BIST and PA-BIST
without negative slacks are shown in figure 15 and
16 respectively.
4. Ganesh L K M, LopamudraPattanayak / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.957-960
960 | P a g e
Fig 15.Layout of LFSR-BIST
Fig16.Layout of PA-BIST
LFSR-BIST and PA-BIST with all parameters are
compared in Table-II
Table 2. Comparison of LSFR-BIST and PA-BIST
Param
eters
CLA
Using
LFS
R
Perc
enta
ge
Using
PA-
BIST
Percenta
ge
AREA
(in µm)
8831
18295
.2
51%
14390.0
06
38%
Power
(in
nW)
11916
32
24219
82
50%
182440
6
34%
No of
Gates
241 521 53% 325 34%
V. CONCLUSION
As showed in table 2, PA-BIST can highly
reduce the test time, during BIST application, that
is, all the total power, area and the no of gates
are highly reduced. Experimental results based on
Cadences’ RTL Complier tool and Encounter tool
for BIST applications show that about 51% to 38%
reduction in area, 50% to 34% reduction in the
power and 53% to 34% reduction in no of gates used
and BIST achieved without losing the stuck-at fault
coverage.
A comparison of reduction of power
consumption between LFSR-BIST and PA-BIST
was reported, to demonstrate that PA-BIST is much
more efficient in the reduction of peak power
consumption when the pattern is applied to 32-
bit Carry Look Ahead Adder.
REFERENCE
1. Michael L. Bushnell,Vishwani D. Agrawal
“Essentials of ElectronicTesting fordigital,
memory and mixed-signal vlsi
circuits”Kluwer Academic Publishers,
pp.11-12.
2. Y Zorian, “A Distributed BIST control
scheme for Complex VLSIdevices.”. IEEE
PZSITeslSymp. 1993, pp.4-9.
3. Michael L. Bushnell,Vishwani D. Agrawal
“Essentials of ElectronicTesting fordigital,
memory and mixed-signal vlsi
circuits”Kluwer Academic Publishers,
pp.496-498.