This document outlines a proposed superconducting proton linac design for the ESS-Bilbao accelerator. Key points include:
- The design proposes using existing superconducting spoke and elliptical cavities to accelerate a proton beam to 1400 MeV, requiring fewer sections and frequency jumps than the baseline ESS design.
- The superconducting section would extend down to 30 MeV, taking advantage of mature superconducting technology.
- Design goals include minimizing length and cost while achieving high accelerating gradients up to 30 MV/m.
- Key research and development issues include controlling higher-order modes and wakefield effects at high beam currents up to 150 mA.
- Collaboration
Use of MIKE 21/3 in the Hydraulic Analysis for the Dublin Port ABR Project - ...Stephen Flood
2015 DHI UK & Ireland Symposium
KEYNOTE: Use of MIKE 21/3 in the Hydraulic Analysis for the Dublin Port ABR Project
Adrian Bell (RPS),
Tuesday 21 April 2015 at 10:30 - 11:00
This project essentially looked at the stability of a deepened approach channel and examined the impact of the dredging and disposal for the scheme in support of a public planning hearing. The modelling used coupled MIKE 21 FM HD-SW-ST models as well as well as MIKE 21 and MIKE 3 FM HD and MT models.
Undertaking Modelling of Flooding due to Wave Overtopping using the MIKE by D...Stephen Flood
Undertaking Modelling of Flooding due to Wave Overtopping using the MIKE by DHI Software Suite - Dr Suzie Clarke (DHI)
This presentation outlines the basis for one of the methodologies that can be followed in order to simulate the flooding of coastal areas due to overtopping of coastal defences by extreme or storm wave conditions. It is not expected that the slides are exhaustive in detail, nor present the only approach, but are provided to give basic guidance for all experience levels. Care is advised when following this methodology and all results should be subjected to reasonable checking.
Read the full Executive Summary here - http://s3.amazonaws.com/dhiuk_blog_storage/UGM_2014/Overtopping-with-BW-Guidance-Executive-Summary.pdf
Shellfisheries Waters Compliance Assessments at Pegwell BayStephen Flood
Shellfisheries Waters Compliance Assessments at Pegwell Bay in Kent. MIKE by DHI modelling (FM Series) formed a large part of the study, and Jonathan presents some interesting experiences in the use of the Software (Jonathan Short - URS).
MIKE by DHI 15th UK User Group Meeting - Tuesday 19 March 2013
Use of MIKE 21/3 in the Hydraulic Analysis for the Dublin Port ABR Project - ...Stephen Flood
2015 DHI UK & Ireland Symposium
KEYNOTE: Use of MIKE 21/3 in the Hydraulic Analysis for the Dublin Port ABR Project
Adrian Bell (RPS),
Tuesday 21 April 2015 at 10:30 - 11:00
This project essentially looked at the stability of a deepened approach channel and examined the impact of the dredging and disposal for the scheme in support of a public planning hearing. The modelling used coupled MIKE 21 FM HD-SW-ST models as well as well as MIKE 21 and MIKE 3 FM HD and MT models.
Undertaking Modelling of Flooding due to Wave Overtopping using the MIKE by D...Stephen Flood
Undertaking Modelling of Flooding due to Wave Overtopping using the MIKE by DHI Software Suite - Dr Suzie Clarke (DHI)
This presentation outlines the basis for one of the methodologies that can be followed in order to simulate the flooding of coastal areas due to overtopping of coastal defences by extreme or storm wave conditions. It is not expected that the slides are exhaustive in detail, nor present the only approach, but are provided to give basic guidance for all experience levels. Care is advised when following this methodology and all results should be subjected to reasonable checking.
Read the full Executive Summary here - http://s3.amazonaws.com/dhiuk_blog_storage/UGM_2014/Overtopping-with-BW-Guidance-Executive-Summary.pdf
Shellfisheries Waters Compliance Assessments at Pegwell BayStephen Flood
Shellfisheries Waters Compliance Assessments at Pegwell Bay in Kent. MIKE by DHI modelling (FM Series) formed a large part of the study, and Jonathan presents some interesting experiences in the use of the Software (Jonathan Short - URS).
MIKE by DHI 15th UK User Group Meeting - Tuesday 19 March 2013
Here is a prelim presentation I will make at the SMM Coatings Conference in Hamburg, Sept. 2010. Contact me for the .ppt after the conference. Sorry but many of the fonts converted automatically as a part of the upload process.
The SpaceDrive Project - First Results on EMDrive and Mach-Effect ThrustersSérgio Sacani
Propellantless propulsion is believed to be the best option for interstellar travel. However, photon rockets or solar sails have thrusts so low that maybe only nano-scaled spacecraft may reach the next star within our lifetime using very high-power laser beams. Following into the footsteps of earlier breakthrough propulsion programs, we are investigating different concepts based on non-classical/revolutionary propulsion ideas that claim to be at least an order of magnitude more efficient in producing thrust compared to photon rockets. Our intention is to develop an excellent research infrastructure to test new ideas and measure thrusts and/or artefacts with high confidence to determine if a concept works and if it does how to scale it up. At present, we are focusing on two possible revolutionary concepts: The EMDrive and the Mach-Effect Thruster. The first concept uses microwaves in a truncated cone-shaped cavity that is claimed to produce thrust. Although it is not clear on which theoretical basis this can work, several experimental tests have been reported in the literature, which warrants a closer examination. The second concept is believed to generate mass fluctuations in a piezo-crystal stack that creates non-zero time-averaged thrusts. Here we are reporting first results of our improved thrust balance as well as EMDrive and Mach-Effect thruster models. Special attention is given to the investigation and identification of error sources that cause false thrust signals. Our results show that the magnetic interaction from not sufficiently shielded cables or thrusters are a major factor that needs to be taken into account for proper μN thrust measurements for these type of devices.
An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wi...IJECEIAES
Amplifiers are widely used in signal receiving circuits, such as antennas, medical imaging, wireless devices and many other applications. However, one of the most challenging problems when building an amplifier circuit is the noise, since it affects the quality of the intended received signal in most wireless applications. Therefore, a preamplifier is usually placed close to the main sensor to reduce the effects of interferences and to amplify the received signal without degrading the signal-to-noise ratio. Although different designs have been optimized and tested in the literature, all of them are using larger than 100 nm technologies which have led to a modest performance in terms of equivalent noise charge (ENC), gain, power consumption, and response time. In contrast, we consider in this paper a new amplifier design technology trend and move towards sub 100 nm to enhance its performance. In this work, we use a pre-well-known design of a preamplifier circuit and rebuild it using 45 nm CMOS technology, which is made for the first time in such circuits. Performance evaluation shows that our proposed scaling technology, compared with other scaling technology, extremely reduces ENC of the circuit by more than 95%. The noise spectral density and time resolution are also reduced by 25% and 95% respectively. In addition, power consumption is decreased due to the reduced channel length by 90%. As a result, all of those enhancements make our proposed circuit more suitable for medical and wireless devices.
Area Efficient Pulsed Clocks & Pulsed Latches on Shift Register TannerIJMTST Journal
This paper introduced a design and implementation of shift register using pulsed latches and flip-flops. As
flip-flop based shift registers requires a clock signal to operate. Multistage flip-flop processes with high clock
switching activity and then increases time latency. Flip-flops also engages fifty percent power out of total
circuit power in clocking. To reduce such power consumptions and to achieve area optimization flip-flops are
replaced by pulsed latches. The design is implemented with 250nm technology in Tanner EDA Tool. With
Vdd=1.8V, Freq=100MHz. Average power of total circuit is 0.465uW and delay of 0.312 us.
In this deck from the HPC User Forum in Detroit, Muhsin Ameen from Argonne National Laboratory presents: Towards Exascale Engine Simulations with NEK5000.
"High-order methods have the potential to overcome the current limitations of standard CFD solvers. For this reason, we have been developing and improving the spectral element code NEK5000 for more than 30 years now. It features state-of-the-art, scalable algorithms that are fast and efficient on platforms ranging from laptops to the world’s fastest computers. Applications span a wide range of fields, including fluid flow, thermal convection, combustion and magnetohydrodynamics. Our user community includes over 400+ scientists and engineers in academia, laboratories and industry."
Watch the video: https://wp.me/p3RLHQ-j7R
Learn more: https://nek5000.mcs.anl.gov/
and
http://hpcuserforum.com
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Modelling of next zen memory cell using low power consuming high speed nano d...eSAT Journals
Abstract Hybrid SET-CMOS circuits which syndicate the assets of both the SET [Single Electron Transistor] and CMOS depicts highest possibilities to be incorporated in practical implementation for future low power VLSI/ULSI configurations. The proposed work is an attempt based on SET-CMOS hybrid circuit to realize the next gen simple Memory Cell. The authors adhered to MIB model for SET and BSIM4 model for CMOS in realizing the complex cell. The maneuver of the proposed circuit is verified subsequently in standard environment. The outcomes are in good trade off with the conventional statistics of existing memory cell. Keywords: SET, SED, Hybrid CMOS-SET, MIB and Memory Cell
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Here is a prelim presentation I will make at the SMM Coatings Conference in Hamburg, Sept. 2010. Contact me for the .ppt after the conference. Sorry but many of the fonts converted automatically as a part of the upload process.
The SpaceDrive Project - First Results on EMDrive and Mach-Effect ThrustersSérgio Sacani
Propellantless propulsion is believed to be the best option for interstellar travel. However, photon rockets or solar sails have thrusts so low that maybe only nano-scaled spacecraft may reach the next star within our lifetime using very high-power laser beams. Following into the footsteps of earlier breakthrough propulsion programs, we are investigating different concepts based on non-classical/revolutionary propulsion ideas that claim to be at least an order of magnitude more efficient in producing thrust compared to photon rockets. Our intention is to develop an excellent research infrastructure to test new ideas and measure thrusts and/or artefacts with high confidence to determine if a concept works and if it does how to scale it up. At present, we are focusing on two possible revolutionary concepts: The EMDrive and the Mach-Effect Thruster. The first concept uses microwaves in a truncated cone-shaped cavity that is claimed to produce thrust. Although it is not clear on which theoretical basis this can work, several experimental tests have been reported in the literature, which warrants a closer examination. The second concept is believed to generate mass fluctuations in a piezo-crystal stack that creates non-zero time-averaged thrusts. Here we are reporting first results of our improved thrust balance as well as EMDrive and Mach-Effect thruster models. Special attention is given to the investigation and identification of error sources that cause false thrust signals. Our results show that the magnetic interaction from not sufficiently shielded cables or thrusters are a major factor that needs to be taken into account for proper μN thrust measurements for these type of devices.
An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wi...IJECEIAES
Amplifiers are widely used in signal receiving circuits, such as antennas, medical imaging, wireless devices and many other applications. However, one of the most challenging problems when building an amplifier circuit is the noise, since it affects the quality of the intended received signal in most wireless applications. Therefore, a preamplifier is usually placed close to the main sensor to reduce the effects of interferences and to amplify the received signal without degrading the signal-to-noise ratio. Although different designs have been optimized and tested in the literature, all of them are using larger than 100 nm technologies which have led to a modest performance in terms of equivalent noise charge (ENC), gain, power consumption, and response time. In contrast, we consider in this paper a new amplifier design technology trend and move towards sub 100 nm to enhance its performance. In this work, we use a pre-well-known design of a preamplifier circuit and rebuild it using 45 nm CMOS technology, which is made for the first time in such circuits. Performance evaluation shows that our proposed scaling technology, compared with other scaling technology, extremely reduces ENC of the circuit by more than 95%. The noise spectral density and time resolution are also reduced by 25% and 95% respectively. In addition, power consumption is decreased due to the reduced channel length by 90%. As a result, all of those enhancements make our proposed circuit more suitable for medical and wireless devices.
Area Efficient Pulsed Clocks & Pulsed Latches on Shift Register TannerIJMTST Journal
This paper introduced a design and implementation of shift register using pulsed latches and flip-flops. As
flip-flop based shift registers requires a clock signal to operate. Multistage flip-flop processes with high clock
switching activity and then increases time latency. Flip-flops also engages fifty percent power out of total
circuit power in clocking. To reduce such power consumptions and to achieve area optimization flip-flops are
replaced by pulsed latches. The design is implemented with 250nm technology in Tanner EDA Tool. With
Vdd=1.8V, Freq=100MHz. Average power of total circuit is 0.465uW and delay of 0.312 us.
In this deck from the HPC User Forum in Detroit, Muhsin Ameen from Argonne National Laboratory presents: Towards Exascale Engine Simulations with NEK5000.
"High-order methods have the potential to overcome the current limitations of standard CFD solvers. For this reason, we have been developing and improving the spectral element code NEK5000 for more than 30 years now. It features state-of-the-art, scalable algorithms that are fast and efficient on platforms ranging from laptops to the world’s fastest computers. Applications span a wide range of fields, including fluid flow, thermal convection, combustion and magnetohydrodynamics. Our user community includes over 400+ scientists and engineers in academia, laboratories and industry."
Watch the video: https://wp.me/p3RLHQ-j7R
Learn more: https://nek5000.mcs.anl.gov/
and
http://hpcuserforum.com
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Modelling of next zen memory cell using low power consuming high speed nano d...eSAT Journals
Abstract Hybrid SET-CMOS circuits which syndicate the assets of both the SET [Single Electron Transistor] and CMOS depicts highest possibilities to be incorporated in practical implementation for future low power VLSI/ULSI configurations. The proposed work is an attempt based on SET-CMOS hybrid circuit to realize the next gen simple Memory Cell. The authors adhered to MIB model for SET and BSIM4 model for CMOS in realizing the complex cell. The maneuver of the proposed circuit is verified subsequently in standard environment. The outcomes are in good trade off with the conventional statistics of existing memory cell. Keywords: SET, SED, Hybrid CMOS-SET, MIB and Memory Cell
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
CNTFET Based Analog and Digital Circuit Designing: A ReviewIJMERJOURNAL
ABSTRACT: Silicon has been a material of choice for the last many decades and more than 95% of electronics devices are from silicon. However, silicon has reached to its saturation level and extracting more and more performance is difficult and costly now. A new material which has a potential to replace Si and can extend the scalability of devices below 22 nm is the carbon nanotube (CNT). CNT is a wonderful material possesses unique properties that make it a promising future material. CNT based field effect transistor (Cntfet) is a promising basic building block to complement the existing silicon based MOSFET and can result in the extension of the validity of Moore's law further. CNTFT has been used extensively in realizing electronics circuits. This paper presents the state of the art literature related to carbon nanotubes, carbon nanotube field effect transistors and CNTFET based circuit designing. A review of Cntfet based analog and digital circuits has been presented. It has been observed that the use of CNTFET has improved the performance of both analog and digital circuits. The work will be very useful to the people working in the field of CNT based analog and digital circuit designing.
Overview of the FlexPlan project. Focus on EU regulatory analysis and TSO-DSO...Leonardo ENERGY
Webinar recording at https://youtu.be/4s2GGlu-ylc
The FlexPlan project (https://flexplan-project.eu/) aims at establishing a new grid planning methodology making use of storage and flexible loads as an alternative to the build-up of new grid elements. After introducing the project, the webinar will focus on pan-European grid planning regulation and present practices of TSOs and DSOs.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
ESS-Bilbao Initiative Workshop. Beam Dynamics Codes: Availability, Sophistica...ESS BILBAO
Beam Dynamics Codes: Availability, Sophistication, Limitations. P.N. Ostroumov and B. Mustapha Argonne National Laboratory, J.-P. Carneiro Fermi National Accelerator Laboratory
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
ESS Bilbao Initiative Workshop Talk. Javier Bermejo
1. A Superconducting Proton
Linac for the ESS-Bilbao
Accelerator
ILC-GDE / MICINN - FPA Mtg.
Madrid, Jan. 20 2009
F.J. Bermejo,
CSIC & Dept. Electricity & Electronics, Univ. Basque Country
ZTF/FCT Leioa, Biscay
2. Outline
A Brief Account of the ESS Accel. Concept
Pending issues with the ESS Baseline
Schematics for the ESS-B Accelerator
Designs
ESS-B R&D Activities
Wrap up & Conclusion
4. The European Spallation Source saga :A prom along a long, winding path
Late 80´s - Early 90´s : Setting up of a study group at EU headquarters (Brussels DG XII) to envisage
•
how to maintain european leadership in neutron scattering (i.e. Post I.L.L. Scenario)
1996 - First complete design spec finished. ESS Central project team moved to KFZ Juelich,
•
2002-2003 - Revised accelerator spec., mostly as a result of ISIS -CEA collaboration. KFZ-J to play the
•
host role for the installation. Mid-2003, Central Project Team disbanded after a poor review by the
Deutche Wissenschaftrat,
2003-2004 - A team of survivors (ESS-Initiative) settles at the Institut Laue Langevin (Grenoble) to keep
•
the project minimally alive,
2008 - ESS included within the list of EU Large Infrastructures. Three countries remain interested in
•
hosting the installation : Hungary (Debrecen), Spain (Bilbao) and Sweden (Lund). The three bidding places
have been recently scrutinized by an international panel,
2008 - … ESS will not be financed thru EU channels but rather, as a result of multilateral agreements.
•
4
12. Matters arising the ESS 2003/2008 Baseline :
It has been taken as a basis for construction and operation costs,
Has been used to determine the site requirements,
Sets the spec for energy, power and time structure,
A number of pending issues requiring a significant R&D effort still
remain, particularly those concerning the front end,
Dual mode, short/long pulses operation needs to be proven feasible,
SC technology is now a proven thing. This may have implications on
whether or not a long, warm LINAC is still needed.
13. A revision of the accelerator design is highly advisable
The 2008 ESS baseline has potential show-stoppers: i.e. the funnel
section may be far more difficult to build than previously thought,
can we do without ?
SC cavities are nowadays the choice for accelerating devices for
energies well below the 400 MeV mark given in the ESS baseline,
The current 2008 baseline considers three frequency jumps which
may perhaps be reduced to two (cheaper and safer),
Accelerating gradients are limited to 10.2 MV/m (far too modest),
As it stands, synergies with other existing projects are difficult to
envisage.
15. A few constraints to the design,
use existing acceleration devices whenever possible
minimize the number of sections/lattice transitions
minimize the number of bunch frequencies
maximize accelerating fields while keeping peak surface fieldsbelow safe values (70 mT for
Bpeak and gradients below 30 MV/m)
minimize the Linac length (cost of present-day linacs : 1 M€/m)
keep beam losses below 1 W/m,
select those operating frequencies to match those: a) used by the low-energy front-ends
within current-day projects where synergies are expected; b) employed by cavities and couplers
already developed; c) provided by klystrons commercially available and a smaller number of cavities
to be employed,
choose those accelerating structures which show more potential reliability-wise (highly modular
with some degree of redundancy)
15
19. Some remarks on the proposed design
Technology is now mature to push the accelerator superconducting section
down to a few tens of MeV (EURISOL - 1.5 MeV/u, HINS/Project X - 10 MeV,
EUROTRANS - 20 MeV)
Super-conducting cavities show additional advantages such as : a) Beam
apertures of a few cm , b) Mechanically more stable than warm components; c)
Allow fast dynamic compensation of tuning failures leading to far enhanced
reliable operation; d) enable a far more eficient use of the RF power,
SC LINACs are , by force, significantly shorter in length! Expenditure in
cryogenics plants will most certainly be compensated by savings in rising
electricity costs,
There are pending feasibily issues concerning the liquid metal target. Rotating
solid-metal considered as a safe, backdrop option.
20. Which spoke cavities do we want ?
Energy range - 30 -MeV -- 150 MeV
Beam Current - 100 mA
Rep. Rate - 30 Hz
Pulse Length- 1 ms
Duty Factor- 3.%
Frequency - 352.2 MHz
Transv. Emittance (input)- 0.2π mm mr (rms norm.)
Long. Emittance (input)- 0.2π deg MeV
Beam aperture - 6 cm
Eacc - 8-9 MV/m (optimally)
Q- 7 x 10^8
β- 0.35
Acceleration 1.8 MeV/m
Peak.surf.mag. field. 90 mT
Oper.Temp. 4K
26. The ESS-B Accelerator Concept,
A single proton source may do the job, SILHI has reached 140
mA. Operation with the switch magnet enables RF
preconditioning of a new source providing enhanced reliable
operation
A RFQ and DTL very close in design to that of Linac4 suffices
to reach some 30 MeV,
SC cavities (spokes) are proven to provide acceleration up to
150 MeV,
Two sets of elliptical SC cavities required to reach 1400 MeV,
A considerable degree of built-in redundancy is planned to
allow tuning by means of dynamic compensation schemes
Operating frequencies to match those of Linac4,
27. RD issues to address
Need to attenuate higher-order-modes. HOMs drive longitudinal
and transverse coupled bunch instabilities, which need to be
controlled using active feedback systems,
The deleterious effects of wake fields at the high beam currents
we are aiming at need to be quantified in terms of the emittance
growth,
Need to assess the best method to deal with frequency jump
(Duperrier PRST-AB 10, 084201 2007)
A whole new set of diagnostic tools needs to be thought.
29. Our view of target development
Preparatory work is being carried out along two parallel lines
on liquid-metal and solid targets to minimize project risks :
-The thermal hydraulic and thermal shock performance due to deposition
of 300 kJ on millisecond scales needs to be characterized in much more
detail than previously done.
Work on cavitation mitigation technologies (helium bubbles and gas
protective layers) is being carried out in collaboration with SNS.
Rod disposition
Detailed numerical simulations of the pressure and thermal waves are being
developed. Particular attention is being paid to the study of effects of
thermal cycling aiming to select candidate materials for the vessel able to
stand the heat loads.
The engineering design of a rotary solid 5 MW target is being developed.
It considers options such as:
Embodiment and location of the drive unit
Target material, possible cladding and disposition (solid block, plates, rods)
Cooling loop.
A prototype mockup will be built and tested.
29
30. Our Activities : Current Plausible
Development of a conceptual accelerator design in full parametric
form (SNS, IPNO CEA),
Adaptation and prototyping a triple b= 0.35 spoke cavity for high
current / pulsed operation (IPNO),
Participation in Linac4 (CERN) injector (LEBT DTL) as well as in
engineering development for SPL (HVC Modulators, adaptation of ILC/
TESLA Cryomodules),
Ongoing partnership in the development of ISIS-FETS,
Prototyping of a MW-grade rotating solid-metal target (SNS),
Development of thermal-hydraulics studies on target materials to
stand heat loads of 300 kJ at high duty factors (3 %) (SNS),
Neutron instruments developments currently under way at ISIS, ILL
(Lagrange) and PNPI-Gatchina,
30
31. Our view on instrument development
ESS-B considers the timing too
premature to define an instrument suite
at this stage of early planning
The users will have full power to specify
the instrument suite. ESS-Bilbao will set
up the adequate user forums to evaluate
proposals for new instruments as the
source develops
Care is being taken of to ensure that
Prototypes being developed at present
new instruments with particularly
at LCMI (Grenoble) and SNS
important power and spatial demands
Instrumentation requiring rather
such as 35 T magnets, or extreme-
special needs (12 MW, demanding
cooling conditions, instrument to be conditions machines, can be designed
built within a separate building and built
Magnet systems to adapt to a variety of
instruments (diraction, spectroscopy,
ESS-Bilbao will be looking for
SANS,Reflectometry)
collaboration with other sources for
doing prototypes and testing
31
32. Collaboration ESS-Bilbao- ISIS Pulsed Neutron Source
Magnetic LEBT
Low-level RF controls for the RFQ
RFQ Tuning system
Engineering design for the fast (MEBT) chopper
Beam Dump
RFQ RF couplers RF splitting/distribution system
MEBT Rebuncher,
MEBT high resolution timing/sync. system
35. Current Activities : In-house developments
Development of a versatile Ion Source Test Stand,
aiming at the development of our own injector able
to test low beta cavities.
Assembly of a (mostly local) project team on beam
dynamics, RF controls, neutronics fluid mech. issues
Help to nucleate an industrial base for accelerator
components. A base for neutron instrumentation
already exists.
39. References
A.P. Letchford et al. PAC’07, Alburquerque, NM 2007, Code TUPAN111
R. Enparantza et al. EPAC’08, Genoa, Italy, Code WEPP080
A.P. Letchford et al. EPAC’08, Genoa, Italy, Code THPP029
A.P. Letchford et al. LINAC’08, Victoria, BC, 2008 : “Status of the RAL
Front End Test Stand”
I.Bustinduy et al. HB2008, Nashville, TN, 2008, : “A superconducting
proton accelerator for thr ESS-B linac
R. Enparantza et al. NIBS, Aix-en-Provence 2008: “ An Ion Source Test
Stand for Ultimate Reliability
39
40. Wrap up / Conclusions
ESS- Bilbao is now in a position to start baselining an
up to date accelerator able to deliver a minimum of
100 mA current using already existing technology,
Reaching the 150 mA current as written in the spec.
will require a modest RD effort, mostly geared
towards finding available options for compensation of
space-charge effects at the front-end,
42. References
A.P. Letchford et al. PAC’07, Alburquerque, NM 2007, Code
TUPAN111
R. Enparantza et al. EPAC’08, Genoa, Italy, Code WEPP080
A.P. Letchford et al. EPAC’08, Genoa, Italy, Code THPP029
A.P. Letchford et al. LINAC’08, Victoria, BC, 2008 : “Status
of the RAL Front End Test Stand”
R. Enparantza et al. NIBS, Aix-en-Provence 2008: “ An Ion
Source Test Stand for Ultimate Reliability”