This document discusses finite state machines (FSM) and algorithmic state machine (ASM) charts. It provides examples of Moore and Mealy FSM implementations in VHDL, including ASM charts and VHDL code. It also provides an example of an arbiter control unit design using an ASM chart and VHDL code. Recommended reading materials on FSMs and ASM charts in VHDL are listed.

1. George Mason University
Algorithmic State Machine (ASM) Charts:
VHDL Code & Timing Diagrams
ECE 448
Lecture 7

2. 2
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 5, FSM

3. 3
Recommended reading
• S. Brown and Z. Vranesic,
Fundamentals of Digital Logic with VHDL Design
Chapter 8, Synchronous Sequential Circuits
Sections 8.1-8.5
Section 8.10, Algorithmic State Machine (ASM)
Charts

4. 4
Finite State Machines
in VHDL

5. 5
Recommended FSM Coding Style
Based on RTL Hardware Design by P. Chu
Process(clk, reset)
Process(Present State, Input)
Next State
Present State

6. 6
ASM Chart of Moore Machine
S0
reset
input
S1
S2
input
input
0
1
0
1
1 0
output

7. 7
Moore FSM in VHDL (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY FSM_Moore IS
PORT ( clk : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
input : IN STD_LOGIC ;
output : OUT STD_LOGIC) ;
END FSM_Moore ;

8. 8
Moore FSM in VHDL (1)
ARCHITECTURE behavioral of FSM_Moore IS
TYPE state IS (S0, S1, S2);
SIGNAL Present_State, Next_State: state;
BEGIN
U_Moore: PROCESS (clk, reset)
BEGIN
IF(reset = '1') THEN
Present_State <= S0;
ELSIF rising_edge(clk) THEN
Present_State <= Next_State;
END IF;
END PROCESS;

9. 9
Moore FSM in VHDL (2)
Next_State_Output:
PROCESS (Present_State, input)
BEGIN
Next_State <= Present_State;
output <= '0';
CASE Present_State IS
WHEN S0 =>
IF input = '1' THEN
Next_State <= S1;
ELSE
Next_State <= S0;
END IF;

10. 10
Moore FSM in VHDL (3)
WHEN S1 =>
IF input = '0' THEN
Next_State <= S2;
ELSE
Next_State <= S1;
END IF;
WHEN S2 =>
output <= '1' ;
IF input = '1' THEN
Next_State <= S1;
ELSE
Next_State <= S0;
END IF;
END CASE;
END PROCESS;
END behavioral;

11. 11
ASM Chart of Mealy Machine
S0
S1
reset
input
input
output
0
1
1 0

12. 12
Mealy FSM in VHDL (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY FSM_Mealy IS
PORT ( clk : IN STD_LOGIC ;
reset : IN STD_LOGIC ;
input : IN STD_LOGIC ;
output : OUT STD_LOGIC) ;
END FSM_Mealy ;

13. 13
Mealy FSM in VHDL (1)
ARCHITECTURE behavioral of FSM_Mealy IS
TYPE state IS (S0, S1);
SIGNAL Present_State, Next_State: state;
BEGIN
U_Mealy: PROCESS(clk, reset)
BEGIN
IF(reset = '1') THEN
Present_State <= S0;
ELSIF rising_edge(clk) THEN
Present_State <= Next_State;
END IF;
END PROCESS;

14. 14
Mealy FSM in VHDL (2)
Next_State_Output:
PROCESS (Present_State, input)
BEGIN
Next_State <= Present_State;
output <= '0';
CASE Present_State IS
WHEN S0 =>
IF input = '1' THEN
Next_State <= S1;
ELSE
Next_State <= S0;
END IF;

15. 15
Mealy FSM in VHDL (3)
WHEN S1 =>
IF input = '0' THEN
Next_State <= S0;
Output <= '1' ;
ELSE
Next_State <= S1;
END IF;
END CASE;
END PROCESS;
END behavioral;

16. 16
Control Unit Example: Arbiter (1)
Arbiter
reset
r1
r2
r3
g1
g2
g3
clock

17. 17
ASM Chart for Control Unit - Example 4
r1
r3
0 1
1
Id
le
R
e
s
e
t
r2
r1
r3
r2
g
n
t1
g
n
t2
g
n
t3
1
1
1
0
0
0
g
1
g
2
g
3
0
0
1
r1
r3
0 1
1
Id
le
R
e
s
e
t
r2
r1
r3
r2
g
n
t1
g
n
t2
g
n
t3
1
1
1
0
0
0
g
1
g
2
g
3
0
0
1

18. 18
VHDL code of arbiter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY arbiter IS
PORT ( Clk, Reset : IN STD_LOGIC ;
r : IN STD_LOGIC_VECTOR(1 TO 3) ;
g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;
END arbiter ;
ARCHITECTURE Behavior OF arbiter IS
TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;
SIGNAL y, y_next : State_type ;

19. 19
VHDL code of arbiter – Style 2 (2)
BEGIN
PROCESS ( Reset, Clk )
BEGIN
IF Reset = '1' THEN
y <= Idle ;
ELSIF rising_edge(Clk) THEN
y <= y_next;
END IF;
END PROCESS;

20. 20
VHDL code of arbiter
PROCESS ( y, r )
BEGIN
y_next <= y;
g <= "000";
CASE y IS
WHEN Idle =>
IF r(1) = '1' THEN y_next <= gnt1 ;
ELSIF r(2) = '1' THEN y_next <= gnt2 ;
ELSIF r(3) = '1' THEN y_next <= gnt3 ;
ELSE y_next <= Idle ;
END IF ;
WHEN gnt1 =>
g(1) <= '1' ;
IF r(1) = '0' THEN y_next <= Idle ;
ELSE y_next <= gnt1 ;
END IF ;

21. 21
WHEN gnt2 =>
g(2) <= '1' ;
IF r(2) = '0' THEN y_next <= Idle ;
ELSE y_next <= gnt2 ;
END IF ;
WHEN gnt3 =>
g(2) <= '1' ;
IF r(3) = '0' THEN y_next <= Idle ;
ELSE y_next <= gnt3 ;
END IF ;
END CASE ;
END PROCESS ;
END Behavior ;
VHDL code of arbiter

22. Problem 1
Assuming ASM chart given on the next slide,
supplement timing waveforms given in the answer
sheet with the correct values of signals
State, g1, g2, g3, in the interval from 0 to 575 ns.

23. 23
ASM Chart
r1
r3
0 1
1
Id
le
R
e
s
e
t
r2
r1
r3
r2
g
n
t1
g
n
t2
g
n
t3
1
1
1
0
0
0
g
1
g
2
g
3
0
0
1
r1
r3
0 1
1
Id
le
R
e
s
e
t
r2
r1
r3
r2
g
n
t1
g
n
t2
g
n
t3
1
1
1
0
0
0
g
1
g
2
g
3
0
0
1

24. Clk
r1
r2
State
Reset
r3
g1
g2
g3
0 ns 100 ns 200 ns 300 ns 400 ns 500 ns

25. Problem 2
Assuming state diagram given on the next slide,
supplement timing waveforms given in the answer sheet
with the correct values of signals
State and c, in the interval from 0 to 575 ns.

26. X
Reset
a
Y
Z
b
1
0
0
1
0 1
c
b
c
c

27. Clk
a
b
State
c
Reset
0 ns 100 ns 200 ns 300 ns 400 ns 500 ns

28. 28
FSM Coding Style
Process(clk, reset)
Process(Present State,Inputs)

29. RTL Hardware Design
by P. Chu
Chapter 10 29
oe<=1
oe<=1
oe<=1
oe<=1
Memory
Controller

30. 30

31. 31

32. 32