Designmethodology1

Design methodology-Part1
K.Meenakshi
Professor
ECE,GRIET

Design methodology
• Digital design at three basic levels of abstraction
a) Gate level abstraction (large detailed description)
b) Register level of abstraction(Intermediate detail)
c) Processor level of abstraction(low detail)

Digital design
• A digital design can be represented at various levels in three different
angles.
1) Behavioral description
2) Structural description
3) Physical representation.

What is behavioural,structural and physical
implementation of computer
Behavioral
CPU
M1 M2 IO
structural
chip1
chip3 chip4
chip2
Physical

System design
A computer is an example of a system, which is defined informally as a collection—
often a large and complex one—of objects called components, that are connected to
form a coherent entity with a specific function or purpose.
The function of the system is determined by the functions of its components and
how the components are connected.

System representation
• A useful way of modeling a system is a graph.
• A (directed) graph consists of a set of objects V = {v1,v2,v3..vn} called
nodes or vertices and a set of edges E whose members are (ordered)
pairs of nodes taken from the set {(v1,v2),(v2,v3),…(vn-1,vn)} of all such
pairs. The edge e = (vi,vj) joins or connects node vi to vj.
• A graph is often defined by a diagram in which nodes are represented
by circles, dots, or other symbols and edges are represented by lines:
this diagram is synonymous with the graph. The ordering implied by
the notation (vi,vj) may be indicated in the diagram by an arrowhead
pointing from vi to vj.

System
• The system comprises two classes of objects:
I. A set of information processing components C
II. A set of lines that carry information S
In modeling the system by a graph G, we associate C with the nodes of
G and S with the edges of G; the resulting graph is often called a block
diagram. This name comes from the fact that it is convenient to draw
each node (component) as a block or box in which its name and/or its
function can be written.

Structure Versus behavior
• Two central properties of any system are its structure and behaviour.
Structural description
• We define the structure of a system as the abstract graph consisting
of its block diagram with no functional information.
• A structural description merely names components and defines their
interconnection.

Xor gate functional representation

Behavior description
A behavioral description, on the other hand, enables one to determine for
any given input signal a to the system, the corresponding output f(a). We
define the function f to be the behavior of the system.
The behavior/may be represented in many different ways. Truth table
shows one kind of behavioral description for the logic circuit of EX-OR gate.
This tabulation of all possible combinations of input-output values is called
a truth table. Another description of the same EXCLUSIVE-OR behavior can
be written in terms of mathematical equations as

Block diagram
• In general, a block diagram conveys structure rather than behavior.
For example, some of the blocks of computer as being arithmetic-
logic units or memory circuits. Such functional descriptions do not
completely describe the behavior of the components in question;
therefore, we cannot deduce the behavior of the system as a whole
from the block diagram. If we need a more precise description of
system behavior, we generally supply a separate narrative text, or a
more formal description such as a truth table or a list of equations.

Hardware description languages
• we can fully describe a system's structure and behavior by means of a
a hardware description language (HDL), a format that resembles (and
is usually derived from) a high-level programming language such as
Ada or C.

Hardware description languages
• VHDL
• Verilog

Advantages of HDL
• They can provide precise, technology-independent descriptions of
digital circuits at various levels of abstraction, primarily the gate and
register levels. Consequently, they are widely used for documentation
purposes.
• Like programming languages, HDLs can be processed by computers
and so are suitable for use with computer-aided design (CAD)
programs which plays an important role in the design process.

VHDL description
It contains two parts
1. Entity declaration
2. Architectural body

Entity declaration
It describes the system's interface, but says nothing about the
system's behavior or its internal structure.
In this example the entity statement gives the half adder's formal
name half_adder and the names assigned to its input-output (IO)
signals; I0 signals are referred to in VHDL by their connection
terminals or ports.
Inputs and outputs are distinguished by the keywords in and out,
respectively.
The size of each 10 port, meaning the number of signals associated
with it, is specified here as 1 bit by the key- word bit. Thus we can
conclude from the entity part that half_adder System has two inputs,
named x and y, and two 1-bit outputs, named sum and carry .

Architectural body
The architecture part of a VHDL description specifies behavior and/or internal
structure.
The functions of the half adder's two outputs sum and carry are specified by two
Boolean functions xor and and, which are built into VHDL; that is, they are
predefined functions. In VHDL xor stands for the EXCLUSIVE-OR
function.
The AND function denoted by and is another basic logic function, which may be
defined as follows: AND(x,y) = 1 if and only if x = 1 and y = 1.

There are three models in VHDL
I. Behavior Model
II. Structural Model
III. Dataflow Model

Half-adder in behavioral model

Design process
Given a system's structure, the task of determining its
function or behavior is termed analysis. The converse
problem of determining a system structure that exhibits a
given behavior is design or synthesis.
Design problem. We can now state in broad terms the problem facing the
computer designer or, indeed, any system designer. Given a desired range
of behavior and a set of available components, determine a structure
(design) formed from these components that achieves the desired behavior
with acceptable cost and performance by the cost of manufacture and is
measured by the speed of operation.

Performance constraints
Performance and cost constraints are
1. high reliability
2. low power consumption
3. High speed
4. Minimization of area
5. Compatibility with existing systems

Iterative design process
New system often fails to meet the design
objective.
The failure is due to
a) Incomplete specification
b) Errors made by humans or CAD tools
c) Unanticipated interactions between
structure, performance, and cost.

Reducing complexity in computer design
The complexity of computer systems is such that the design problem
must be broken down into smaller, easier tasks involving various
classes of components.
These smaller problems can then be solved independently by different
designers or design teams. Each major design step is often implemented
via the multistep or iterative process depicted by a flowchart.
An initial design is created, perhaps in ad hoc fashion, by adapting
an existing design of a similar system. The result is then evaluated
to see if it meets the relevant design objectives. If not, the design
is revised and the result reevaluated.
Many iterations through the redesign and evaluation steps of Figure
2.6 may be necessary to obtain a satisfactory design.

Computer Aided design
The emergence of powerful and inexpensive desktop computers with good
graphics interfaces provides designers with a range of programs to
support their design tasks.
CAD tools contribute in three important
to the overall design process.
CAD editors or translators convert design data into forms such as HDL descriptions or
schematic diagrams, which humans, computers, or both can efficiently process.
• Simulators create computer models of a new design, which can mimic the design's
behavior and help designers determine how well the design meets various performance
and cost goals.
• Synthesizers automate the design process itself by deriving structures that implement
all or part of some design step.

Computer Aided design
Editing is the easiest of these three tasks, and synthesis the
most difficult.
Many synthesis approaches are therefore based on trial-and error
methods and experience with earlier designs. These
computationally efficient but inexact methods are called heuristics
and form the basis of most practical CAD tools.

Design levels
The design of a complex system such as a computer is carried out at several levels of
abstraction. Three such levels are generally recognized in computer design, although
they are referred to by various different names in the literature:
• The processor level, also called the architecture, behavior, or system level.
• The register level, also called the register-transfer level (RTL).
• The gate level, also called the logic level
The processor level corresponds to a user's or manager's view of a computer. The register level is approximately
the level of detail seen by a programmer. The gate level is primarily the concern of the hardware designer. These
three design levels also correspond roughly to the major subdivisions of integrated-circuit technology into VLSI,
MSI, and SSI components.

The major computer design levels

Differences between different layers of
abstraction based on complexity
Another important difference lies in the time required for an elementary operation;
successive levels can differ by several orders of magnitude in this parameter. At the gate
level the time required to switch the output of a gate between and 1 (the gate delay)
serves as the time unit and typically is a nanosecond (ns) or less. A clock cycle of, say, 10
ns, is a commonly used unit of time at the register level. The time unit at the processor
level might be a program's execution time, a quantity that can vary widely.
Levels of abstraction Manipulated data
Low level of abstraction individual bits (Os and Is)
Mid level abstraction Multibit words or vectors
High level abstraction Blocks of words, A program or dataset

System hierarchy
It is customary to refer to a design level as high or low; the more complex the components, the higher the level.
A component in any level Li, is equivalent to a (sub) system of components taken
from the level Li-1, beneath it.

Design process
1.Specify the processor-level structure of the system.
2. Specify the register-level structure of each component type identified in step 1.
3. Specify the gate-level structure of each component type identified in step 2.

The Gate level
Gate-level (logic) design is concerned with processing binary variables whose
possible values are restricted to the bits (binary digits) and 1 . The design
components are logic gates, which are simple, memoryless processing elements,
and flip-flops, which are bit-storage devices.
A combinational function, also referred to as a logic, or a Boolean function, is a
mapping from the set of 2" input combinations of n binary variables onto the
output values 0 and 1 . Such a function is denoted by Z(x1,x2……………xn) or simply
by Z, which specified for every input combination of Z(x1,x2……………xn).

Gates
A set G of gate types is said to be (functionally) complete if any logic function can be
realized by a circuit that contains gates from G only. Examples of complete sets of gates
are {AND, OR, NOT}, {AND, NOT}, {NAND}, and {NOR}.
NANDs and NORs are particularly important in logic design because they are easily
manufactured using most IC technologies and are the only standard gate types that are
functionally complete by themselves.
SOP
POS

Number of Logic levels
The number of logic levels is defined by the number
of gates along the circuit's longest i/o path.
Logic levels 2
Logic levels 4

Design trade-offs
The half-adder-based has 1/o paths containing up to four gates and so is considered to
have four levels of logic. If all gates have the same propagation delay, then the two-level
adder (Figure 2.9c) is twice as fast as the four-level design (Figure 2.9b). However, the
two-level adder has more gates and so has a higher hardware cost. A basic task in logic
design is to synthesize a gate level circuit realization of a given set of combinational
functions that achieves a satisfactory balance between hardware cost as measured by the
number of gates, and operating speed as measured by the number of logic levels used.

Logic synthesis
1. Unoptimized design
a) Specification in the form of truth table
b) A set of logic equations embedded in HDL description language
2. Design constraints
a) Propagation delay
b) Fan out
3. Technology library: Once a good design of a useful function is known, it can be
placed in a library for future use. A full adder, for instance, can be used to build a
multibit, multilevel adder

Flip flops
By adding memory to a combinational circuit in the form of 1-bitstorage elements
called flip-flops, we obtain a sequential logic circuit. Flip-flops rely on an external
clock signal CK to synchronize the times at which they respond to changes on their
input data lines.
Triggering is two types:
1) Edge triggering
2) Level triggering

Edge triggered and level triggered differences

Asynchronous control inputs
When a flip-flop is first switched on. its state y is uncertain unless it is
explicitly brought to a known initial state. It is therefore desirable to be able
to initialize (reset) the flip-flop asynchronously, that is, independently of the
clock signal CK, at the start of operation. To this end, a flip-flop can have one
or two asynchronous control inputs, CLR (clear) and PRE (preset), as shown
in Figure 2.11a. Each is designed to respond to a brief input pulse that forces
y to in the case of CLR or to 1 in the case of PRE.

We can then describe a D flip-flop's next-state
behavior by the following characteristic equation
y(t+l) = D(t)

Sequential circuits
 A sequential circuit consists of a combinational circuit and a set of flip-
flops.
 The combinational logic forms the computational or data processing part
of the circuit.
 The flip-flops store information on the circuit's past behavior; this stored
information defines the circuit's internal state Y.
 If the primary inputs are X and the primary outputs are Z, then Z is a
function of both X and Y, denoted Z(X,Y). It is usual to supply a sequential
circuit with a precisely controlled clock signal that determines the times at
which the flip-flops change state; the resulting circuit is said to be clocked
or synchronous. Each tick (cycle or period) of the clock permits a single
change in the circuit's state Y.

Serial circuit as a sequential circuit

Serial adder
A serial adder, which is intended to add two unsigned binary numbers X, and X2 of
arbitrary length, producing their sum Z = X plus X2 . The numbers are supplied
serially, that is, bit by bit, and the result is also produced serially.
On the other hand, "parallel" adder, which, ignoring its internal-signal propagation
delays, adds all bits of the input numbers simultaneously.
In one clock cycle System Design, Serial adder receives 2 input bits X1(i) and x2(i) and
computes 1 bit z(i) of Z. It also computes a carry signal c(i) that affects the addition in
the next clock cycle.
Thus the output computed in clock cycle i is

Serial adder cont…
where c(i - 1) must be determined from the adder's present state S(i).
S(0 ) means the previous carry signal C(i-1)=0
S(1) means the previous carry signal C(I-1)=1

Serial adder Mealy FSM with state diagram

Problems with register level design
1.The operations performed by some basic register-level components are numerical rather than logical; they
are not easily incorporated into a Boolean framework.
2. Many of the logical operations associated with register-level components are complex and do not have the
properties of the gates—interchangeability of inputs, for example—that simplify gate-level design.
2.Although a system often has a standard word length w based on the width of some important buses or
registers, some buses carry signals with a different number of bits. For example, the outcome of a test on a is
1 bit rather than w. The lack of a uniform word size for all signals makes it difficult to define a useful algebra
to describe operations on these signals.

OR word gate implementing y + X:

Multiplexer
A multiplexer is a device intended to route data from one of several
sources to a common destination; the source is specified by
applying appropriate control (select) signals to the multiplexer. If
the maximum number of data sources is k and each I/O data line
carries m bits, the multiplexer is referred to
as a k-input (or k-way), m-bit multiplexer. It is convenient to make k
= 2 𝑝., so that data source selection is determined by an encoded
pattern or address of p bits.
The 2 𝑝
addresses then cover the range 00...0, 00...1, ..., 11...1 =
2 𝑝 - 1.

Multiplexer operation
• Let 𝑎𝑖=1, when we want to select the m-bit input data bus
𝑋𝑖= 𝑥𝑖,0, 𝑥𝑖,1, … … … … … 𝑥𝑖,𝑚−1 Then 𝑎𝑖=1, when we apply the word
corresponding to the binary number i to the select bus S. The binary
variable, 𝑎𝑖 denotes the selection of input data bus 𝑋𝑖-𝑎𝑖, is not a
physical signal. The data word on X, is then transferred to Z when e =
1.

An eight-input multiplexer constructed from two-input multiplexers.
Several &-input multiplexers can be used to
route more than k data paths by
connecting them in the treelike fashion.
A q-level tree circuit of this type forms
𝑘 𝑞,-input multiplexer.
A distinct select line is associated
with every level of the tree and is connected
to all multiplexers in that level. Thus each
level performs a partial selection of the data
line X, to be connected to the output Z.

Multiplexers as function generators
• Multiplexers have the interesting property that they can compute
any combinational function and so form a type of universal logic
generator.
• Specifically, a 2 𝑛, 2"-input, 1-bit multiplexer MUX can generate any
n-variable function 𝑧 𝑣 𝑜,𝑣1 … … 𝑣 𝑛−1 . Thisis accomplished by
applyingthe n input variables𝑣 𝑜,𝑣1 … … 𝑣 𝑛−1 to n select lines
𝑠 𝑜,𝑠1 … … 𝑠 𝑛−1, and2 𝑛
function-specific constant values (0 or 1) to
MUX's 2 𝑛
input data lines 𝑥 𝑜,𝑥1 … … 𝑥2 𝑛−1. The output of MUX is
then
where again ai, denotes the selection of input data bus xi.

Full adder realization with 4 by 1 MUX

Full adder realization with 8 by 1 MUX

Decoders
• A l-out-of-2 𝑛
is a' combinational circuit with n input lines X and 2 𝑛
output
lines Z such that each of the 2 𝑛
possible input combinations 𝐴𝑖applied to X
activates a corresponding output line 𝑧𝑖. Several 1/2 𝑛
decoders can be
used to decode more than n lines by connecting them in a tree
configuration analogous to the multiplexer tree.
• The main application of decoders is address decoding, where 𝐴𝑖, is
interpreted as an address that selects a specific output line 𝑧𝑖; or some
circuit attached to 𝑧𝑖.
• .

A four-output, 2-bit demultiplexer

Encoders
• An encoder is a circuit intended to generate the address or index of
an active input line; it is therefore the inverse of a decoder. Most
encoders have 2 𝑘
input data lines and k output data lines.
• 𝑥 𝑜,𝑥1,𝑥2…𝑥 𝑛−1 The encoder produces output 𝑧0 𝑧1 𝑧2=110. Moreover,
it is also necessary to assign priorities to the input lines and design
the encoder so that the output address is always that of the active
input line with the highest priority. A circuit of this type is called a
priority encoder

DESIGN OF A 4-BIT MAGNITUDE
COMPARATOR.
• It has eight input lines, implying that its truth table has 28 = 256 rows.
The comparator is quite difficult to design at the gate level.
Furthermore, a two-level (SOP or POS) realization is impractical
because of the many gates involved, as well as their large fan-in.
• We can design a magnitude comparator for two n-bit numbers X and
Y efficiently at the register level by noting that X > Y is equivalent to
X-Y>0

DESIGN OF A 4-BIT MAGNITUDE
COMPARATOR.
• Now Y can be computed by the subtraction step 2 𝑛 − 1 − 𝑌. where
𝑌the bitwise complement of Y and 2 𝑛 − 1is a sequence of n Is. For
example, if n = 4 and Y = 1001(9), then Y = 0110(6), 24 - 1 = 1111 (15),
and Y= 1111 -0110= 1001. Hence inequality can be replaced by X -
2 𝑛 − 1 − 𝑌.> 0, implying
• Suppose X and 𝑌 are added in an adder and if carry out is 1, X +
• Y will exceed the largest n-bit number 2 𝑛 − 1.

Registers
• An m-bit register is an ordered
set of m flip-flops designed to
store an m-bit
word 𝑧 𝑜, 𝑧1, 𝑧2 … . . 𝑧 𝑚 .
• Each bit of the word is stored in a
separate flip-flop, but the flip-
flops have common control lines
(clock, clear, and so on). Registers
can be constructed from various
flip-flop types.

Symbolic representation of a register

Load i/p
• The register Z of reads in the data word X each time it is
clocked.Therefore, to maintain the contents or state of Z at a constant
value, it is necessary to apply that value continuously to Z's input bus.
• Often we want to load a new value of X into Z in a particular clock cycle
and subsequently change X without changing Z. To this end, we
introduce a control line LOAD, which should cause the register to read in
(load) the current value of X when it is clocked and LOAD has been set
to 1 . When LOAD = 0, the state of Z should not change when the
register is clocked; it should retain the last value loaded into it.

Load i/o
• To this end, we introduce a control line LOAD, which should cause the
register to read in (load) the current value of X when it is clocked and
LOAD has been set to 1 . When LOAD = 0, the state of Z should not
change when the register is clocked; it should retain the last value
loaded into it.
• To To add this load feature to register Z, we insert a two-input, 4-bit
multiplexer MUX into its into its input data bus.
• The new control line LOAD is connected MUX's select line s. MUX's
data input lines are connected to X and to the register output Z so
that the circuit behaves as follows in each clock cycle.

Control with Load signal
• If LOAD = 1, then X is loaded into the register from the input bus: that
is. Z := X.
• If LOAD = 0, then the old value of Z is loaded back into the register;
that is, Z := Z.
• These circuits are designed so that external data can be transferred
to or from all its flip-flops simultaneously; this mode of operation is
called parallel input-output.

Shift registers
• In some computer-design situations it is usefulto transfer (shift) the
contents of a register in and out 1 bit at a time. A register
• designed for such operations is a shift register. A right-shift operation
changes the register's state as described by the following register-
transfer statement

Shift register cont..
• In each case a bit of stored data is lost from one end of the shift
register, while a new data bit x is brought in at the other end.
• In its simplest form, an m-bit shift register consists of m flip-flops
each of which is connected to its left or right neighbor.
• Data can be entered 1 bit at a time at one end of the register and can
be removed (read) 1 bit at a time from the other end; this process is
called serial input-output.

Shift register modes
• A right shift is accomplished by activating the SHIFT enable line
connected to the clock input CK of each flip-flop. In addition to the
serial data lines, m input or output lines are often provided to permit
parallel data transfers to or from the shift register. Additional control
lines are required to select the serial or parallel input modes. A
further refinement is to permit both left- and right-shift operations.

Applications of shift registers
• Shift registers are useful design components in a number of
applications.
1. Storage of serial data
2. Serial-to-parallel or parallel-to-serial data conversion.
• They can also be used to perform certain arithmetic operations on
binary
• numbers, because left- (right-) shifting corresponds to multiplication
(division) by two.
The instruction sets of most computers include shift operations.

Counters
• A counter is a sequential circuit designed to cycle through a
predetermined sequence of k distinct states 𝑆0 , 𝑆1, , . . . , 𝑆 𝑘−1 in
response to signals ( 1 -pulses) on an input line. The k states
represent k consecutive numbers, so the state transitions can be
described by the statement

Counters
• Each 1 -input increments the state by one; the circuit can therefore be
viewed as counting the input Is. Counters come in many different
varieties depending on the number codes used, the modulus k, and
the timing mode (synchronous or asynchronous).

UP-DOWN COUNTER
In the up-counting mode (DOWN= 0), the counter's behavior
in the down-counting mode (DOWN = 1), the behavior
becomes

Applications of counters
1. They can store the state of a control unit. Incrementing a counter
provides an efficient means of generating a sequence of control states.
2.Counters can also generate timing signals.
3. Introduce precise delays into a system.

Buses
• A bus is a set of lines (wires) designed to transfer all bits of a word from a specified source to a specified
destination on the same or a different IC; the source and destination are typically registers. A bus can be
unidirectional, that is, capable of transmitting data in one direction only, or it can be bidirectional.
• Although buses perform no logical function, a significant cost is associated with them, since they require
logic circuits to control access to them and, when used over longer distances, signal amplification circuits
(drivers and receivers). The pin requirements and gate density of an IC increase rapidly with the number of
external buses connected to it. If these buses are long, the cost of the wires or cables used must also be
taken into account.

Buses
• They are two types
1) Shared bus
2) Dedicated bus
• Shared bus: A shared bus is one that can connect one of several
sources to one of several destinations. Bus sharing reduces the
number of connecting lines but requires more complex bus-
control mechanisms.
• Dedicated bus: Shared buses are relatively cheap, they do not
permit simultaneous transfers between different pairs of
devices, which is possible with unshared or dedicated buses.

Programmable Logic Devices
A class of components called programmable logic devices or PLDs, a term
applied to ICs containing many gates or other general-purpose cells whose
interconnections can be configured or "programmed" to implement any desired
combinational or sequential function.
PLDs are relatively easy to design and inexpensive to manufacture. They constitute a key
technology for building application-specific integrated circuits (ASICs).

Types of PLDs
There are two types of PLD’s
1.Mask programmable
2.Field programmable

Erasable PLDs
• Some field-programmable PLDs are erasable, implying that the
same IC can be reprogrammed many times. This technology is
especially convenient when developing and debugging a
prototype design for a new product.

Programmable arrays
The connections leading to and from logic elements in a PLD contain transistor
switches that can be programmed to be permanently switched on or switched
off.
These switches are laid out in two-dimensional arrays so that large gates can
be implemented with minimum IC area.
PLD array are represented abstractly, with x denoting a programmable
connection or crosspoint in a gate's input line. The absence of an x means that
the corresponding connection has been programmed to the off (disconnected)
state.

Implementation of function ACD

PLA
• The programmable logic array (PLA is intended to realize a set of
combinational logic functions in minimal SOP form. It consists of an array
of AND gates (the AND plane), which realize a set of product terms
(prime implicants), and a set of OR gates (the OR plane), which form
various logical sums of the product terms.
• The inputs to the AND gates are programmable and include all the input
variables and their complements. Hence it is possible to program any
desired product term into any row of the PLA.

PLA
For example, the top row of the PLA in Figure 2.33 is programmed to
generate the term 𝑥1 𝑥3 𝑥4 𝑦1 𝑦2, which is used in computing the output
D2 the last row is programmed to generate 𝑥1 𝑥2 𝑦1 for output D1. The
inputs to the OR gates are also programmable,
so each output column can include any subset of the product terms
produced by the rows.
The inputs to the OR gates are also programmable,
so each output column can include any subset of the product terms
produced by the rows.

Full adder realization with ROM
In ROM, AND PLANE is fixed
represented by dots and OR plane
is programmable.

Programmable Array logic
• Programmable array logic (PAL) circuits have an AND plane that is
programmable, but an OR plane with fixed connections designed to
link each output line to a fixed set of AND rows, typically about eight
rows. Such a PAL output can realize only a two-level expression
containing at most eight terms. A PAL's advantages are ease of use in
some applications, as well as higher speed because output fan-out is
restricted.

Field-programmable gate arrays.
• A Field-programmable gate array (FPGA) is a two-dimensional array of
general-purpose logic circuits, called cells or logic blocks, whose
functions are programmable; the cells are linked to one another by
programmable buses. The cell types are not restricted to gates. They
are small multifunction circuits capable of realizing all Boolean
functions of a few variables; a cell may also contain one or two flip-
flops.
• Like all field-programmable devices, FPGAs are suitable for
implementing prototype designs and for small-scale manufacture.

FPGA
• FPGAs can store the program that determines the circuit to be implemented in a
RAM or PROM on the FPGA chip. The pattern of the data in this Configuration
memory CM determines the cells' functions and their interconnection wiring. Each
bit of CM controls a transistor switch in the target circuit that can select some cell
function or make (break) some connection.
• By replacing the contents of CM, designers can make design changes or correct
design errors. This type of FPGA can be reprogrammed repeatedly, which
significantly reduces development and manufacturing costs. Some FPGAs employ
fuses or antifuses as switches, which means that each FPGA IC can be
programmed only once. These one-time programmable FPGAs have other
advantages, however, such as higher density, and smaller or more predictable
delays.

Types of Logic cells in FPGA
1. Based on multiplexers
2. Based on PROM table-lookup memories.

Multiplexer based cell array
• This cell is a four-input, 1-bit multiplexer with an AND and OR gate
added.
An ACT FPGA contains a large array (many thousands) of such cells organized in rows
separated by horizontal wiring channels . Vertical wire segments are attached to each cell's
10 terminals. These wires enable onnections to be established between the cells and the
wiring channels by means of one-time-programmable antifuses positioned where the
horizontal and vertical wires cross. In addition, long vertical wires run across the entire
array to carry primary IO signals, power (logical 1), and ground (logical 0).

Multiplexer cell based array as function
generator
Multiplexers as function generators implies that the FPGA cell of can
generate any Boolean function of up to three variables if the inputs are
supplied in both true and complemented form.
This cell can also generate various useful functions of more than three
variables due to the presence of the two extra gates.
The cell's AND and OR gates help to realize four-input AND and OR
functions.
The same combinational cell implements an edge-triggered D flipflop.

4 i/p AND gate, 4 i/p or gate and complement
implementation with mux based cells

FPGA implementation of serial adder

Serial adder
• Here z is the sum bit and c is the carry bit. A single D flip-flop stores
the value of c produced
• in each clock cycle and applies it to C as y in the next clock cycle. We
Here z is the sum bit and c is the carry bit. A single D flip-flop stores the value of c produced
in each clock cycle and applies it to C as y in the next clock cycle.

FPGA implementation of Serial adder
• We will assume that if the complements of any of the input variables x1,
x2 , or y are needed, they must be generated explicitly in the FPGA.
• two cells are required for the D flip-flop, assuming that
• we don't need the complement of y. It's not immediately clear how many
cells are needed to produce the sum and carry. A little experimentation
shows that the carry function does indeed have a one-cell realization;.
which suggests the way we use the Actel cell's AND and OR gates.

FPGA in CAD
FPGAs are very well suited to computer-aided'design and manufacture.
The process of mapping a new design into one or more FPGA chips can be
almost entirely automated.
 It requires first translating or "compiling" the design specification—a
schematic diagram or an HDL description, for example—into a logic (gate
and flip-flop) model. Specialized place-and-route CAD software is then
employedto assign the logic elements to cells, to determine the switch
settings needed to set each cell's function, and to establish the intercell
connections.
Finally, the design is physically transferred to one or more copies of the
FPGA chip via an appropriate programming unit, a process that has been
aptly described as "desktop manufacturing."

Register-Level Design
• A register-level system consists of a set of registers linked by combinational
data transfer and data-processing circuits. A block diagram can define its
structure, and the set of operations it performs on data words can define its
behavior. Each operation is typically implemented by one or more
elementary register- transfer steps of the form
where /is a function to be performed or an instruction to be executed in one clock cycle. Here 𝑋1,𝑋2. ., 𝑋 𝑘 and Z denote
data words or the registers that store them. The prefix cond denotes a control condition that must be satisfied (cond =
1) for the indicated operation to take place. It is read as follows: when
cond holds, compute the (combinational) function/on and assign the Here 𝑋1,𝑋2 . ., 𝑋 𝑘
resulting value to Z.

Data and control.
A multifunction system is
generally partitioned into
a data-processing part,
called a datapath, and a
controlling part, the
control unit, which is
responsible for selecting
and controlling the actions
of the datapath.

Multifunction unit
• It is easy to see that this circuit has the connection paths necessary to
perform the following data-processing operations, as well as many others.
Less obvious operations that can be performed are the simple data transfer Z := B, which is implemented as Z := + B:
the clear operation B := 0, which is implemented as B := B - B; and the negation operation B := - B. A few double
operations can be performed in one clock cycle, for example,

Multifunction unit
Each of the foregoing operations requires CU to send specific control
signals, indicated by dashed lines to various places in the datapath. For
instance, to execute the subtraction Z := A - B, the controller CU must
send select signals to the ALU to select its subtract function; it must
send select signals to the multiplexer that connects register A to the
ALU's left port; and it must send a "load data" control signal to the
output register Z.

Central processing unit
• It is a multifunction unit in computer.
• Its control unit, which is responsible for the interpretation of instructions, is called
the program control unit or I-unit. The CPU's datapath is also called the E-unit.
• Further datapath/control subdivisions are possible in complex systems, yielding a
hierarchy of levels of control.
• In relatively simple machines , the control unit can be a special-purpose hard-wired
sequential circuit designed using standard gate-level techniques. In more complex
cases, both the datapath and control units may have to be treated at the register
level.

Formal language description of an 8-bit
binary multiplier.

8 bit unsigned multipication
• This 8-bit multiplication circuit, named multiplier8, computes the
product Z = Y x X. where the numbers are 8-bit binary fractions in
sign-magnitude form. (The actual design of this multiplier, which
implements a binary version of "long" multiplication based on
repeated addition and shifting.
• Two 8-bit buses INBUS and OUTBUS form multiplier8' s input and
output ports, respectively, and link it to the outside world.
• The circuit contains three 8-bit data registers A, M, and Q, as well as a
• 3-bit control register COUNT that counts the number of add-and-shift
steps to decide when Multiplication is complete.

8 bit multiplication
• The A and Q registers can be merged into a single 16-bit shift register denoted A.Q.
• The operands X (the multiplier) and F (the multiplicand) are initially transferred from
INBUS into the Q and M registers, respectively.
• The product is computed by multiplying F by 1 bit of X at a time and adding the
result to A. After each addition step, the contents of A.Q are shifted 1 bit to the right
so that the next multiplier bit required is always in Q[7] the right-most
• bit in the Q register. After seven iterations to multiply the magnitude parts ofX and F,
the sign of the product is computed and placed in the left-most position of A, that is,
in A[0].

Design techniques
1. Define the desired behavior by a set of sequences of register-transfer operations, such that each operation
can be implemented directly using the available design components. This constitutes an algorithm AL to be
executed.
2. Analyze AL to determine the types of components and the number of each type required for the datapath DP.
3. The Register Level Construct a block diagram for DP using the components identified in step 2.
4. Make the connections between the components so that all data paths implied by AL are present and the given
performance-cost constraints are met.
5. 4. Analyze AL and DP to identify the control signals needed. Introduce into DP the logic or control points
necessary to apply these signals.
6. 5. Design a control unit CU for DP that meets all the requirements of AL.
7. 6. Verify, typically by computer simulation, that the final design operates correctly and meets all performance-
cost goals.

8 bit multiplication
• Fixed-point multiplication is often implemented in computers by a binary
version of the manual multiplication algorithm for decimal numbers based
on repeated addition and shifting.
• Consider the task of multiplying two 8-bit binary fractions X =
𝑥0 𝑥1 𝑥2 𝑥3 𝑥4 𝑥5 𝑥6 𝑥7 and Y=𝑦0 𝑦1 𝑦2 𝑦3 𝑦4 𝑦5 𝑦6 𝑦7 to form the product 𝑍 = 𝑋 ×
𝑌.
• The left-most bit (with subscript 0) of the number denotes its sign: for
positive and 1 for negative. The remaining seven bits represent the number's
magnitude. Note that for fractions, it is convenient to index the numbers
from left to right, so that bit 𝑥𝑖 has a weight of 2−𝑖. Hence when 𝑥0=0, X =
𝑥0 𝑥1 𝑥2 𝑥3 𝑥4 𝑥5 𝑥6 𝑥7denotes the positive number

8 bit unsigned multiplication
The multiplication algorithm first multiplies the magnitude
Parts 𝑋 𝑀 and 𝑌 𝑀 of X and Y
𝑃 𝑀=𝑋 𝑀 × 𝑌 𝑀

Unsigned product PM
• The unsigned product PM is computed in seven add and shift operations.

With these preliminaries, we can now specify the main components needed
for multiplier8. Two 8-bit registers, conventionally denoted Q (for multiplier-
quotient) and M (for multiplicand), are required to store X and Y, respectively.
A double-length, 16- bit register A (for accumulator) stores the P,'s; this
standard length is more convenient than the actual 15-bit maximum size of P.
A 7-bit combinational adder is used for the addition .The adder must have its
output and one input connectedto A, while its other input must be switched
between M and zero. The 1-bit right-shift function can be conveniently
obtained by constructing A from a right shift register with parallel IO.

The addition is controlled by bit 𝑥7−𝑖, which is stored in the Q register. The
multipliers control unit must be able to scan the contents of Q from right to left
in the course of the multiplication. If Q is a right-shift register, then 𝑥7−𝑖, can
always be obtained from Q's right-most flip-flop Q[l] by right-shifting Q
before the next is needed. Consequently, is gradually reduced from 7 to 0 bits
while 𝑃𝑖 is expanding from 7 to 14 bits, also by right-shifting. Hence we can
combine A and Q into a single 16-bit, right-shift register, the left half of which
is A while the right half is Q. The multiplier is completed by the inclusion of
external data buses INBUS and OUTBUS and a control unit, which contains a
3-bit iteration counter named COUNT.

The output-carry signal 𝐶 𝑜𝑢𝑡 of the adder is the most significant bit of an 8-
bit sum and so is connected to the data input of A[0}. The counter COUNT
is incremented and tested at the end of each add-shift step to determine if
the add-shift phase should terminate. When COUNT is found to contain 7,
𝑃𝑖 occupies bits 1:14 of the register-pair A.Q; that is, bits A[1:7].Q[0:6].
The sign bit p is then computed from x and y , which are stored in Q[l] and
M[0], respectively, and p is placed in A[0]. At the same time is written into
Q[l] to expand the final product from
15 to 16 bits. Figure 2.42 shows the complete step-by-step multiplication
process for two sample fractions X = 10110011 and Y = 01010101. The
sign bit x = 1 of X (indicating that it is a negative number) is marked by an
underline. The data in A.Q to the left of .v is the current partial product P.

The processor level
• The processor or system level is the highest in the computer
design hierarchy. It is concerned with the storage and processing
of blocks of information such as programs and data files. The
components at this level are complex, usually sequential, circuits
that are based on VLSI technology.

The processor level components
1. Processors
2. Memories
3. I/O devices
4. Interconnection networks

Processor
• We define a CPU to be a general-purpose, instruction- set processor that has overall
responsibility for program interpretation and execution in a computer system.
• The qualifier general-purpose distinguishes CPUs from other, more specialized
processors, such as IO processors (IOPs), whose functions are restricted. An
instruction-set processor is characterized by the fact that it operates on word-
organized instructions and data, which the processor obtains from an external
memory that also stores results computed by the processor.
• Most contemporary CPUs are microprocessors, implying that their physical
implementation is a single VLSI chip.

CPU
• The CPU contains the logic needed to execute its particular instruction set
and is divided into datapath and control units.
• The control part (the I-unit) generates the addresses of instructions and
data stored in external memory. In this particular system a cache memory is
interposed between the main memory M and the CPU. The cache is a fast
buffer memory designed to hold an active portion of the system's address
space; it is often placed, wholly or in part, on the same IC as the CPU.
• Each memory request generated by the CPU is first directed to the cache. If
the required information is not currently assigned to the cache, the request
is redirected to M and the cache is automatically updated from M. The I-unit
fetches instructions from the cache or M and decodes them to derive the

CPU
• The CPU's datapath (E-unit) has the arithmetic-logic circuits that execute most
instructions; it also has a set of registers for temporary data storage. The CPU
manages a system bus, which is the main communication link among the CPU-
cache subsystem, main memory, and the IO devices.
• The CPU is a synchronous sequential circuit whose clock period is the computer's
• basic unit of time. In one clock cycle the CPU can perform a register-transfer
• operation, such as fetching an instruction word from M via the system bus and
loading it into the instruction register IR. This operation can be expressed
formally by

CPU
• where PC is the program counter the CPU uses to hold the expected
address of the next instruction word. Once in the I-unit, an instruction is
decoded to determine the actions needed for its execution; for example,
perform an arithmetic operation on data words stored in CPU registers. The
I-unit then issues the sequence of control signals that enables execution of
the instruction in question. The entire process of fetching, decoding, and
executing an instruction constitutes the CPU's instruction cycle.

Memories
CPUs and other instruction-set processors operate in conjunction with external memories that store the
programs and data required by the processors.
Numerous memory technologies exist, and they vary greatly in cost and performance. The cost of a memory
device generally increases rapidly with its speed of operation. The memory part of a computer can be divided
into several major subsystems:

Types of memories
• Main memory M, consisting of relatively fast storage ICs connected directly to,
• and controlled by, the CPU.
• 2. Secondary memory, consisting of less expensive devices that have very high
• storage capacity. These devices often involve mechanical motion and so are
• much slower than M. They are generally connected indirectly (via M) to the
• CPU and form part of the computer's 10 system.
• 3. Many computers have a third type of memory called a cache, which is
positioned between the CPU and main memory. The cache is intended to further
• reduce the average time taken by the CPU to access the memory system. Some
• or all of the cache may be integrated on the same IC chip as the CPU itself.

IO Devices
• Input-output devices are the means by which a computer communicates
with the outside world. A primary function of 10 devices is to act as data
transducers, that is, to convert information from one physical
representation to another. Unlike processors, 10 devices do not alter the
information content or meaning of the data on which they act. Since data
is transferred and processed within a computer system in the form of
digital electrical signals, input (output) devices transform other forms of
information to (from) digital electrical signals.

Interconnection networks
• Processor-level components communicate by word-oriented buses. In systems with many
components, communication may be controlled by a subsystem called an interconnection
network; terms such as switching network, communications controller, and bus controller are also
used in this context.
• The function of the interconnection network is to establish dynamic communication paths among
• the components via the buses under its control. For cost reasons, these paths are usually shared.
• Only two communicating devices can access and use a shared bus at any time, so contention
results when several system components request use of the bus.
• The interconnection network resolves such contention by selecting one of the requesting devices
• on some priority basis and connecting it to the bus. The interconnection network may place the
other requestingdevices in a queue.

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