A floating point arithmetic unit designed to perform operations on floating point numbers as well as fixed point numbers. Floating point numbers can support a much wider range of values in comparison to fixed point representation. Floating Point units are mainly used in high speed objects recognition system, high performance computer systems, embedded systems and mobile applications. To represent very small values or very large values, large range is required as the integer representation is no longer appropriate to represent these numbers so these values can be represented by using floating point representation that is based on the IEEE 754 standard. The proposed floating point arithmetic unit is designed using single stage implementation. Due to single stage implementation the complex logic operations which consist of various multiple numbers of stages are converted into single stage implementation. So by using single stage implementation the time requires to reach data from input to output becomes less. The proposed unit is designed in VHDL, simulated in Questa Sim simulator and implemented on vertex 7 FPGA. Naresh Kumar | Onkar Singh | Harjit Singh "Design and Analysis of High Performance Floating Point Arithmetic Unit" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-1 , December 2020, URL: https://www.ijtsrd.com/papers/ijtsrd38049.pdf Paper URL : https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/38049/design-and-analysis-of-high-performance-floating-point-arithmetic-unit/naresh-kumar
IRJET- Implementation of Floating Point FFT Processor with Single Precision f...IRJET Journal
This document describes the implementation of a floating point fast Fourier transform (FFT) processor with single precision to reduce power consumption. It discusses floating point number representation and the steps involved in floating point addition, including de-normalization, mantissa addition, and normalization. The key blocks used in a floating point adder architecture are described, including a comparator, shifters, and an exponent incrementer. Simulation results validating the functionality of these blocks are provided. Finally, the document presents simulation and synthesis results for a single precision floating point adder implemented in a CAD tool, including its RTL view and area and delay reports.
A Fast Floating Point Double Precision Implementation on FpgaIJERA Editor
In the modern day digital systems, floating point units are an important component in many signal and image
processing applications. Many approaches of the floating point units have been proposed and compared with
their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for
floating point operations, single and double. In the proposed architecture double precision floating point unit is
used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high
speed adder, which is shared among other operations and can perform operations independently as a separate
unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing
technique which allows performing the operations with the minimum usage of the resources while computing
the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results
show the 23% improvement in the speed of the designed circuit
SINGLE PRECISION FLOATING POINT MULTIPLIER USING SHIFT AND ADD ALGORITHMAM Publications
Floating-point numbers are widely adopted in many applications due to their dynamic representation
capabilities. Basically floating point numbers are one possible way of representing real numbers in binary format.
Floating-point representation is able to retain its resolution and accuracy compared to fixed-point representations.
Multiplying floating point numbers is also a critical requirement for DSP applications involving large dynamic range.
The IEEE has produced a standard to define floating point representation and arithmetic which is known as IEEE
754 standards and which is the most common representation today for real numbers on computer. The IEEE 754
standard presents two different floating point formats, Binary interchange format and Decimal interchange format.
This paper presents a single precision floating point multiplier based on shift and add algorithm that supports the
IEEE 754 binary interchange format..
IRJET- Cheque Bounce Detection System using Image ProcessingIRJET Journal
This document proposes an automatic cheque processing system using image processing techniques. It aims to extract key information from cheque images like the bank logo, signature, date, and amount in order to quickly detect if a cheque has bounced. The system would first preprocess cheque images through steps like binarization. It would then use optical character recognition, support vector machines, and pattern matching to extract, recognize, and verify the different fields. This would allow the system to notify customers faster than manual processing if a cheque has bounced or needs further processing. The system aims to reduce redundancies and free up employee time compared to traditional manual cheque processing methods.
IRJET - Application of Linear Algebra in Machine LearningIRJET Journal
This document discusses the application of linear algebra concepts in machine learning. It begins with an introduction to linear algebra and key concepts like vectors, matrices, and linear transformations. It then provides an introduction to machine learning, including the different types of machine learning algorithms like supervised, unsupervised, and reinforcement learning. It discusses how machine learning is closely related to statistics and introduces some common statistical concepts. Finally, it discusses how linear algebra is widely used in machine learning algorithms like linear regression and support vector machines. Linear algebra allows machine learning models to represent data and map it to specific feature spaces.
Bangla Optical Digits Recognition using Edge Detection MethodIOSR Journals
Abstract:This paper is based on Bangla Optical Digit Recognition (ODR) by the Edge detection technique. In this method, Bangla digit image converted into gray-scale which distributed by an M by N array form. Here input data are considered off-line printed digit’s image which collected from computer generated image, scanned documents or printed text. After addressing the gray-scale image against a variable in the form of an M by N array, where the value of array pointers are shown 255 for total white space, 0 (zero) for total dark space and value between 255 and 0 for mix of white and dark space of the image. At the next process, four edgestouch points as well as each touch point’s ratio use as parameters to determine each Bangla digit uniquely. Keywords-Edge, image,gray-scale, Matrix,ODR.
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...iosrjce
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end
computationally intense microprocessors capable of handling both fixed and floating- point mathematical
operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking
significant area. Over the years, the VLSI community has developed many floating-point adder algorithms
mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating
point adder with minimum time. Floating point numbers are used in various applications such as medical
imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the
performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL.
This paper discusses in detail the best possible FPGA implementation will act as an important design resource.
The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area,
and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
IRJET - Automatic Licence Plate Detection and RecognitionIRJET Journal
This document describes a system for automatic license plate detection and recognition. The system uses image processing techniques in MATLAB to capture an image of a vehicle license plate, preprocess the image by converting it to grayscale and reducing noise, segment the license plate from the image, and recognize the characters on the plate using optical character recognition. The system is proposed to identify vehicles entering a university campus and check if they are registered in the university's database. The document outlines the methodology, which involves preprocessing, segmentation, character separation, and character recognition steps. It also discusses related work on license plate detection algorithms and presents experimental results demonstrating the system's ability to accurately extract license plate numbers from images.
IRJET- Implementation of Floating Point FFT Processor with Single Precision f...IRJET Journal
This document describes the implementation of a floating point fast Fourier transform (FFT) processor with single precision to reduce power consumption. It discusses floating point number representation and the steps involved in floating point addition, including de-normalization, mantissa addition, and normalization. The key blocks used in a floating point adder architecture are described, including a comparator, shifters, and an exponent incrementer. Simulation results validating the functionality of these blocks are provided. Finally, the document presents simulation and synthesis results for a single precision floating point adder implemented in a CAD tool, including its RTL view and area and delay reports.
A Fast Floating Point Double Precision Implementation on FpgaIJERA Editor
In the modern day digital systems, floating point units are an important component in many signal and image
processing applications. Many approaches of the floating point units have been proposed and compared with
their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for
floating point operations, single and double. In the proposed architecture double precision floating point unit is
used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high
speed adder, which is shared among other operations and can perform operations independently as a separate
unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing
technique which allows performing the operations with the minimum usage of the resources while computing
the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results
show the 23% improvement in the speed of the designed circuit
SINGLE PRECISION FLOATING POINT MULTIPLIER USING SHIFT AND ADD ALGORITHMAM Publications
Floating-point numbers are widely adopted in many applications due to their dynamic representation
capabilities. Basically floating point numbers are one possible way of representing real numbers in binary format.
Floating-point representation is able to retain its resolution and accuracy compared to fixed-point representations.
Multiplying floating point numbers is also a critical requirement for DSP applications involving large dynamic range.
The IEEE has produced a standard to define floating point representation and arithmetic which is known as IEEE
754 standards and which is the most common representation today for real numbers on computer. The IEEE 754
standard presents two different floating point formats, Binary interchange format and Decimal interchange format.
This paper presents a single precision floating point multiplier based on shift and add algorithm that supports the
IEEE 754 binary interchange format..
IRJET- Cheque Bounce Detection System using Image ProcessingIRJET Journal
This document proposes an automatic cheque processing system using image processing techniques. It aims to extract key information from cheque images like the bank logo, signature, date, and amount in order to quickly detect if a cheque has bounced. The system would first preprocess cheque images through steps like binarization. It would then use optical character recognition, support vector machines, and pattern matching to extract, recognize, and verify the different fields. This would allow the system to notify customers faster than manual processing if a cheque has bounced or needs further processing. The system aims to reduce redundancies and free up employee time compared to traditional manual cheque processing methods.
IRJET - Application of Linear Algebra in Machine LearningIRJET Journal
This document discusses the application of linear algebra concepts in machine learning. It begins with an introduction to linear algebra and key concepts like vectors, matrices, and linear transformations. It then provides an introduction to machine learning, including the different types of machine learning algorithms like supervised, unsupervised, and reinforcement learning. It discusses how machine learning is closely related to statistics and introduces some common statistical concepts. Finally, it discusses how linear algebra is widely used in machine learning algorithms like linear regression and support vector machines. Linear algebra allows machine learning models to represent data and map it to specific feature spaces.
Bangla Optical Digits Recognition using Edge Detection MethodIOSR Journals
Abstract:This paper is based on Bangla Optical Digit Recognition (ODR) by the Edge detection technique. In this method, Bangla digit image converted into gray-scale which distributed by an M by N array form. Here input data are considered off-line printed digit’s image which collected from computer generated image, scanned documents or printed text. After addressing the gray-scale image against a variable in the form of an M by N array, where the value of array pointers are shown 255 for total white space, 0 (zero) for total dark space and value between 255 and 0 for mix of white and dark space of the image. At the next process, four edgestouch points as well as each touch point’s ratio use as parameters to determine each Bangla digit uniquely. Keywords-Edge, image,gray-scale, Matrix,ODR.
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...iosrjce
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end
computationally intense microprocessors capable of handling both fixed and floating- point mathematical
operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking
significant area. Over the years, the VLSI community has developed many floating-point adder algorithms
mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating
point adder with minimum time. Floating point numbers are used in various applications such as medical
imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the
performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL.
This paper discusses in detail the best possible FPGA implementation will act as an important design resource.
The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area,
and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
IRJET - Automatic Licence Plate Detection and RecognitionIRJET Journal
This document describes a system for automatic license plate detection and recognition. The system uses image processing techniques in MATLAB to capture an image of a vehicle license plate, preprocess the image by converting it to grayscale and reducing noise, segment the license plate from the image, and recognize the characters on the plate using optical character recognition. The system is proposed to identify vehicles entering a university campus and check if they are registered in the university's database. The document outlines the methodology, which involves preprocessing, segmentation, character separation, and character recognition steps. It also discusses related work on license plate detection algorithms and presents experimental results demonstrating the system's ability to accurately extract license plate numbers from images.
This document describes the design and implementation of a power optimized 32-bit floating point arithmetic logic unit (ALU) using a block enabling technique. It discusses the motivation, introduction, literature survey, objectives, floating point ALU design, block enabling technique, tools used, and plan of action. The document presents the design of floating point addition, subtraction, multiplication, and division modules. It compares the synthesis results and power analysis of the proposed floating point ALU with block enabling to a conventional floating point ALU. The goal is to reduce power consumption by limiting unnecessary switching activities through the block enabling technique.
Design and Implementation of Test Vector Generation using Random Forest Techn...IRJET Journal
This document discusses automatic test pattern generation (ATPG) for digital circuits. It begins by introducing ATPG and some common ATPG algorithms like fault simulation and sensitization-propagation-justification. It then describes the design of a random forest ATPG technique, which generates random test vectors for testing digital circuits. Simulation results are presented to validate the technique on sample combinational and sequential circuits like a multiplexer and D flip-flop. The paper concludes that ATPG is an important part of digital design testing.
IRJET- Advanced Character based Recognition and Phone Handling for Blind ...IRJET Journal
This document describes a system to help blind people by converting text to speech. It uses a Raspberry Pi with a USB camera to scan documents and images. Optical character recognition (OCR) is used to convert the images to digital text. For English text, Tesseract OCR is used, while Tamil text uses segmentation to identify characters. The text is then converted to synthesized speech. Gyroscope sensors also allow blind users to make phone calls by detecting gestures near the sensors. The system aims to make life more independent for blind people.
IRJET- Color Image Compression using Canonic Signed Digit and Block based...IRJET Journal
This document proposes a color image compression technique using canonical signed digit (CSD) and multi-level block truncation coding (BTC). It begins by introducing the need for image compression and discusses existing techniques like discrete wavelet transform (DWT) and BTC. The proposed technique is then described, which uses CSD to implement DWT convolution and multi-level BTC to compress color image channels. Simulation results on different images show improved peak signal-to-noise ratio and computation time compared to other techniques. In conclusion, the CSD and multi-level BTC approach achieves good compression performance for color images.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
IRJET- ROI based Automated Meter Reading System using PythonIRJET Journal
This document describes an automated meter reading system using image processing and Python. Key points:
- The system takes images of a meter panel containing multiple meters. It then extracts the meter reading from each meter using image processing techniques in Python like thresholding, contour detection and digit recognition.
- The extracted meter readings are uploaded to a server (ThingSpeak) for remote access. This avoids the need for a service provider to manually record readings.
- An algorithm was developed to detect the region of interest containing each meter display, identify the segments that make up each digit, and recognize the digits based on segment patterns.
- Tests on sample meter images successfully extracted readings from individual meters as well as a panel with
IRJET - Kirsch Compass Kernel Edge Detection for Vehicle Number Plate Det...IRJET Journal
This document describes a method for vehicle number plate detection using image processing techniques. It involves preprocessing the captured vehicle image by converting it to grayscale and binary, then using Kirsch compass kernel edge detection to locate the number plate region. Morphological operations like dilation and erosion are performed for processing. The number plate is extracted using bounding box technique and characters within are segmented. Individual characters are displayed and can be recognized using template matching. The described method aims to accurately detect vehicle number plates for applications like parking access control.
This slidecast takes an informal approach to image processing using Matlab environment.
Very little math is involved to keep things simple. But the full essence is only felt with the math involved.
IRJET - Comparison of Vedic, Wallac Tree and Array MultipliersIRJET Journal
This document compares three multiplication methods: Vedic, Wallace tree, and array multipliers. It implements 8-bit versions of each multiplier in Xilinx and compares their performance in terms of delay, power utilization, and speed. The results show that the Vedic multiplier has the lowest delay and utilizes less power and area than the other multipliers, making it the fastest and most efficient technique for complex mathematical problems according to this research.
This document summarizes techniques for error detection and correction in data communication systems. It discusses various error correction techniques including forward error correction using block codes, convolutional codes, and hybrid automatic repeat request. It focuses on convolutional codes and the Viterbi algorithm, describing the algorithm's use of branch metric computation, path metric computation, and traceback to decode data with the minimum accumulated error path. The document concludes that convolutional encoding with Viterbi decoding is an effective method for forward error correction in wireless communication systems.
IRJET- Implementation of Radix-16 and Binary 64 Division VLSI Realization...IRJET Journal
This document presents four proposed VLSI realization architectures for implementing a high-speed and low-power 64-bit binary division. The architectures use digit-recurrence division algorithms with radix-16 representations and signed digit number systems to represent partial remainders and quotient digits. This allows carry-free addition for calculating next partial remainders and reduces the number of required division iterations. Two representations - static and semidynamic - are used for generating divisor multiples. Radix-16 signed digit sets between [-9,9] are used to represent quotient digits. Carry save and maximally redundant number systems are explored for representing partial remainders to reduce power dissipation. Simulation results show the proposed methods achieve 26-35% lower power
Fabric design pattern feeding through human machine interface (hmi) for an el...eSAT Journals
Abstract
This work mainly focused on improving performance of a semi-automated weaving loom by replacing conventional cylinder with
solenoid array. A human machine interface (HMI) based system is introduced to ensure design edit on loom without the help of
personal computer (PC). Solenoid arrays are controlled by a HMI and a simple microcontroller instead of PC. The technology
behinds the viewable and editable designs of human machine interface without personal computer are explained. Design patterns
are stored in either SD card or USB memory device in the format of bitmap. All hardware models are simulated and verified
forsemi-automated conventional weaving loom.
Key Words: HMI, Microcontroller, Card, Electronic Jacquard, Solenoid Array, Semi Automated Loom, Fabric Design.
The document discusses digital logic circuits and their components. It begins with an introduction to logic gates, which are the basic building blocks of digital circuits. Common logic gates like AND, OR, NOT, NAND, NOR, XOR and XNOR are described along with their truth tables. Boolean algebra is then introduced as the mathematical system used to analyze and design digital logic circuits. Important concepts in boolean algebra like boolean functions, identities and logic simplification are covered. The document concludes by describing Karnaugh maps, a graphical technique used to simplify boolean functions into their minimum logic gate implementations.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
OCR optimization for vehicle number plate Identification based on Template ma...IJEEE
This document proposes and describes a method for vehicle license plate identification and optical character recognition (OCR) based on image segmentation, filtering, and template matching. The key steps include converting images to black and white, removing noise, labeling connected components, filtering regions of interest based on height, width ratios and centroid positions, and correlating localized characters with predefined templates to recognize characters. The method aims to optimize OCR for vehicle plates under varying illumination conditions and achieved an accuracy of 95.76% on 500 test images.
IRJET- RESULT:Wavelet Transform along with SPIHT Algorithm Used for Image Com...IRJET Journal
This document summarizes a research paper that proposes a new medical image compression algorithm combining lifting wavelet transform with the Set Partitioning in Hierarchical Trees (SPIHT) coding algorithm. The algorithm applies lifting schemes to implement wavelet transforms, which decompose an image into sub-bands. It then uses SPIHT coding to efficiently encode the wavelet coefficients. Experimental results showed the proposed algorithm achieved higher peak signal-to-noise ratios than other compression methods like JPEG, making it superior for compressing medical images like MRI scans in both lossy and lossless formats.
Improved Performance of Fuzzy Logic Algorithm for Lane Detection ImagesIRJET Journal
1) The document proposes improving lane detection algorithms by modifying the Hough transform with fuzzy logic to handle curved lane images better.
2) It compares the performance of the traditional Hough transform method to the proposed fuzzy logic-based method using metrics like recall, accuracy, and error rates.
3) The results show that the proposed technique outperforms existing methods, particularly in the presence of noise, curved lanes, or other challenging image conditions.
Barcode Based Parking Management SystemIRJET Journal
This document summarizes a proposed barcode-based parking management system that uses image processing and barcode scanning. The system uses a camera to capture images of the parking lot and compare them to reference images to identify vacant spaces. Drivers scan a barcode at entry that records the check-in time and date. When a vehicle enters, it is assigned a free parking slot and guided there. The system aims to reduce human interference in parking and lower power consumption compared to existing systems. A prototype was implemented using a Raspberry Pi, and testing identified vacant spaces accurately based on image comparisons.
The document describes the design of a 4-bit magnitude comparator using Simulink. It begins with an introduction to magnitude comparators and their applications. It then presents the methodology, including the comparator's block diagram, truth table, and equations. The Simulink modeling environment is described. The design was implemented in Simulink by splitting it into three stages: input, combination, and output. The results were obtained by simulating the design with different input data sets and verifying it produced the expected outputs in each case. The design of the 4-bit magnitude comparator using Simulink was concluded to be successful.
IRJET - Design and Implementation of Double Precision FPU for Optimised SpeedIRJET Journal
This document describes the design and implementation of a double precision floating point unit (FPU) for optimized speed. It discusses the need for high-speed arithmetic operations in applications such as digital signal processing. It presents the architecture of the proposed FPU, which includes blocks for floating point multiplication and addition. It also discusses the implementation of pipelined 64-bit floating point multiplication and addition units using techniques like carry lookahead addition and hybrid multiplication. Simulation results on a FPGA platform show that the proposed pipelined design achieves higher throughput than existing non-pipelined approaches.
This document presents a VHDL implementation of an IEEE 754 floating point unit using a carry look ahead adder and radix-4 modified Booth encoder multiplier. The floating point unit performs single precision floating point multiplication. It consists of blocks to calculate the sign bit, add the exponents, multiply the significands using the modified Booth encoding technique, normalize the result, detect overflow/underflow, and implement pipelining. VHDL simulation results show that this floating point multiplier design has lower delay and power consumption compared to an array multiplier implementation.
This document describes the design and implementation of a power optimized 32-bit floating point arithmetic logic unit (ALU) using a block enabling technique. It discusses the motivation, introduction, literature survey, objectives, floating point ALU design, block enabling technique, tools used, and plan of action. The document presents the design of floating point addition, subtraction, multiplication, and division modules. It compares the synthesis results and power analysis of the proposed floating point ALU with block enabling to a conventional floating point ALU. The goal is to reduce power consumption by limiting unnecessary switching activities through the block enabling technique.
Design and Implementation of Test Vector Generation using Random Forest Techn...IRJET Journal
This document discusses automatic test pattern generation (ATPG) for digital circuits. It begins by introducing ATPG and some common ATPG algorithms like fault simulation and sensitization-propagation-justification. It then describes the design of a random forest ATPG technique, which generates random test vectors for testing digital circuits. Simulation results are presented to validate the technique on sample combinational and sequential circuits like a multiplexer and D flip-flop. The paper concludes that ATPG is an important part of digital design testing.
IRJET- Advanced Character based Recognition and Phone Handling for Blind ...IRJET Journal
This document describes a system to help blind people by converting text to speech. It uses a Raspberry Pi with a USB camera to scan documents and images. Optical character recognition (OCR) is used to convert the images to digital text. For English text, Tesseract OCR is used, while Tamil text uses segmentation to identify characters. The text is then converted to synthesized speech. Gyroscope sensors also allow blind users to make phone calls by detecting gestures near the sensors. The system aims to make life more independent for blind people.
IRJET- Color Image Compression using Canonic Signed Digit and Block based...IRJET Journal
This document proposes a color image compression technique using canonical signed digit (CSD) and multi-level block truncation coding (BTC). It begins by introducing the need for image compression and discusses existing techniques like discrete wavelet transform (DWT) and BTC. The proposed technique is then described, which uses CSD to implement DWT convolution and multi-level BTC to compress color image channels. Simulation results on different images show improved peak signal-to-noise ratio and computation time compared to other techniques. In conclusion, the CSD and multi-level BTC approach achieves good compression performance for color images.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
IRJET- ROI based Automated Meter Reading System using PythonIRJET Journal
This document describes an automated meter reading system using image processing and Python. Key points:
- The system takes images of a meter panel containing multiple meters. It then extracts the meter reading from each meter using image processing techniques in Python like thresholding, contour detection and digit recognition.
- The extracted meter readings are uploaded to a server (ThingSpeak) for remote access. This avoids the need for a service provider to manually record readings.
- An algorithm was developed to detect the region of interest containing each meter display, identify the segments that make up each digit, and recognize the digits based on segment patterns.
- Tests on sample meter images successfully extracted readings from individual meters as well as a panel with
IRJET - Kirsch Compass Kernel Edge Detection for Vehicle Number Plate Det...IRJET Journal
This document describes a method for vehicle number plate detection using image processing techniques. It involves preprocessing the captured vehicle image by converting it to grayscale and binary, then using Kirsch compass kernel edge detection to locate the number plate region. Morphological operations like dilation and erosion are performed for processing. The number plate is extracted using bounding box technique and characters within are segmented. Individual characters are displayed and can be recognized using template matching. The described method aims to accurately detect vehicle number plates for applications like parking access control.
This slidecast takes an informal approach to image processing using Matlab environment.
Very little math is involved to keep things simple. But the full essence is only felt with the math involved.
IRJET - Comparison of Vedic, Wallac Tree and Array MultipliersIRJET Journal
This document compares three multiplication methods: Vedic, Wallace tree, and array multipliers. It implements 8-bit versions of each multiplier in Xilinx and compares their performance in terms of delay, power utilization, and speed. The results show that the Vedic multiplier has the lowest delay and utilizes less power and area than the other multipliers, making it the fastest and most efficient technique for complex mathematical problems according to this research.
This document summarizes techniques for error detection and correction in data communication systems. It discusses various error correction techniques including forward error correction using block codes, convolutional codes, and hybrid automatic repeat request. It focuses on convolutional codes and the Viterbi algorithm, describing the algorithm's use of branch metric computation, path metric computation, and traceback to decode data with the minimum accumulated error path. The document concludes that convolutional encoding with Viterbi decoding is an effective method for forward error correction in wireless communication systems.
IRJET- Implementation of Radix-16 and Binary 64 Division VLSI Realization...IRJET Journal
This document presents four proposed VLSI realization architectures for implementing a high-speed and low-power 64-bit binary division. The architectures use digit-recurrence division algorithms with radix-16 representations and signed digit number systems to represent partial remainders and quotient digits. This allows carry-free addition for calculating next partial remainders and reduces the number of required division iterations. Two representations - static and semidynamic - are used for generating divisor multiples. Radix-16 signed digit sets between [-9,9] are used to represent quotient digits. Carry save and maximally redundant number systems are explored for representing partial remainders to reduce power dissipation. Simulation results show the proposed methods achieve 26-35% lower power
Fabric design pattern feeding through human machine interface (hmi) for an el...eSAT Journals
Abstract
This work mainly focused on improving performance of a semi-automated weaving loom by replacing conventional cylinder with
solenoid array. A human machine interface (HMI) based system is introduced to ensure design edit on loom without the help of
personal computer (PC). Solenoid arrays are controlled by a HMI and a simple microcontroller instead of PC. The technology
behinds the viewable and editable designs of human machine interface without personal computer are explained. Design patterns
are stored in either SD card or USB memory device in the format of bitmap. All hardware models are simulated and verified
forsemi-automated conventional weaving loom.
Key Words: HMI, Microcontroller, Card, Electronic Jacquard, Solenoid Array, Semi Automated Loom, Fabric Design.
The document discusses digital logic circuits and their components. It begins with an introduction to logic gates, which are the basic building blocks of digital circuits. Common logic gates like AND, OR, NOT, NAND, NOR, XOR and XNOR are described along with their truth tables. Boolean algebra is then introduced as the mathematical system used to analyze and design digital logic circuits. Important concepts in boolean algebra like boolean functions, identities and logic simplification are covered. The document concludes by describing Karnaugh maps, a graphical technique used to simplify boolean functions into their minimum logic gate implementations.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
OCR optimization for vehicle number plate Identification based on Template ma...IJEEE
This document proposes and describes a method for vehicle license plate identification and optical character recognition (OCR) based on image segmentation, filtering, and template matching. The key steps include converting images to black and white, removing noise, labeling connected components, filtering regions of interest based on height, width ratios and centroid positions, and correlating localized characters with predefined templates to recognize characters. The method aims to optimize OCR for vehicle plates under varying illumination conditions and achieved an accuracy of 95.76% on 500 test images.
IRJET- RESULT:Wavelet Transform along with SPIHT Algorithm Used for Image Com...IRJET Journal
This document summarizes a research paper that proposes a new medical image compression algorithm combining lifting wavelet transform with the Set Partitioning in Hierarchical Trees (SPIHT) coding algorithm. The algorithm applies lifting schemes to implement wavelet transforms, which decompose an image into sub-bands. It then uses SPIHT coding to efficiently encode the wavelet coefficients. Experimental results showed the proposed algorithm achieved higher peak signal-to-noise ratios than other compression methods like JPEG, making it superior for compressing medical images like MRI scans in both lossy and lossless formats.
Improved Performance of Fuzzy Logic Algorithm for Lane Detection ImagesIRJET Journal
1) The document proposes improving lane detection algorithms by modifying the Hough transform with fuzzy logic to handle curved lane images better.
2) It compares the performance of the traditional Hough transform method to the proposed fuzzy logic-based method using metrics like recall, accuracy, and error rates.
3) The results show that the proposed technique outperforms existing methods, particularly in the presence of noise, curved lanes, or other challenging image conditions.
Barcode Based Parking Management SystemIRJET Journal
This document summarizes a proposed barcode-based parking management system that uses image processing and barcode scanning. The system uses a camera to capture images of the parking lot and compare them to reference images to identify vacant spaces. Drivers scan a barcode at entry that records the check-in time and date. When a vehicle enters, it is assigned a free parking slot and guided there. The system aims to reduce human interference in parking and lower power consumption compared to existing systems. A prototype was implemented using a Raspberry Pi, and testing identified vacant spaces accurately based on image comparisons.
The document describes the design of a 4-bit magnitude comparator using Simulink. It begins with an introduction to magnitude comparators and their applications. It then presents the methodology, including the comparator's block diagram, truth table, and equations. The Simulink modeling environment is described. The design was implemented in Simulink by splitting it into three stages: input, combination, and output. The results were obtained by simulating the design with different input data sets and verifying it produced the expected outputs in each case. The design of the 4-bit magnitude comparator using Simulink was concluded to be successful.
IRJET - Design and Implementation of Double Precision FPU for Optimised SpeedIRJET Journal
This document describes the design and implementation of a double precision floating point unit (FPU) for optimized speed. It discusses the need for high-speed arithmetic operations in applications such as digital signal processing. It presents the architecture of the proposed FPU, which includes blocks for floating point multiplication and addition. It also discusses the implementation of pipelined 64-bit floating point multiplication and addition units using techniques like carry lookahead addition and hybrid multiplication. Simulation results on a FPGA platform show that the proposed pipelined design achieves higher throughput than existing non-pipelined approaches.
This document presents a VHDL implementation of an IEEE 754 floating point unit using a carry look ahead adder and radix-4 modified Booth encoder multiplier. The floating point unit performs single precision floating point multiplication. It consists of blocks to calculate the sign bit, add the exponents, multiply the significands using the modified Booth encoding technique, normalize the result, detect overflow/underflow, and implement pipelining. VHDL simulation results show that this floating point multiplier design has lower delay and power consumption compared to an array multiplier implementation.
Design of 32-bit Floating Point Unit for Advanced ProcessorsIJERA Editor
Floating Point Unit is one of the integral unit in the Advanced Processors. The arithmetic operations on floating point unit are quite complicated. They are represented in IEEE 754 format in either 32-bit format (single precision) or 64-bit format (double precision). They are extensively used in high end processors for various applications such as mathematical analysis and formulation, signal processing etc. This paper describes the detailed process for the computation of addition, subtraction and multiplication operations on floating point numbers. It has been designed using VHDL. The design has been simulated and synthesized to identify the area occupied and its performance in terms of delay.
The Role Of Software And Hardware As A Common Part Of The...Sheena Crouch
This document discusses the implementation of a software-defined networking (SDN) system using Field Programmable Gate Arrays (FPGAs). It describes an SDN switch core that can modify packet headers based on flow tables and forward packets to different ports. An SDN controller programmed the flow tables and monitored packet flows. Attacker nodes, implemented with a Microblaze processor, transmitted packets to the SDN switch network at programmable rates. The system allowed observation and testing of the SDN switches and network. Hardware and software implementations are discussed to realize the SDN system on FPGAs.
IRJET- A Review on Single Precision Floating Point Arithmetic Unit of 32 Bit ...IRJET Journal
This document reviews a single precision floating point arithmetic unit that performs operations like addition, subtraction, and multiplication on 32-bit operands according to the IEEE 754 standard. It discusses how floating point units are widely used in areas like scientific computing and signal processing. The review covers the IEEE 754 standard specification for single precision floating point numbers, which uses 1 sign bit, 8 exponent bits, and 23 fraction bits. It also summarizes several previous studies that have designed and optimized reversible floating point arithmetic units to reduce costs like quantum cost, garbage outputs, and constant inputs.
Review on 32 bit single precision Floating point unit (FPU) Based on IEEE 754...IRJET Journal
The document reviews a 32-bit single precision floating point unit based on the IEEE 754 standard that is implemented using VHDL. It discusses floating point number representations, the IEEE 754 standard, and prior work on floating point unit design. The proposed FPU performs operations like addition, subtraction, multiplication and division on 32-bit operands. It is implemented and analyzed using VHDL simulation and synthesized using the Xilinx ISE suite. A block diagram of the proposed FPU structure is also presented, dividing the arithmetic operations into different blocks.
IRJET- Single Precision Floating Point Arithmetic using VHDL CodingIRJET Journal
The document describes a VHDL implementation of single precision floating point arithmetic operations using an FPGA. It begins with an introduction to floating point arithmetic and FPGAs. It then discusses related work on floating point implementations and the IEEE 754 single precision format. The proposed algorithm and block diagram for a single precision floating point adder are presented. Simulation results demonstrating addition, subtraction, multiplication and division are also shown. The implementation of single precision floating point arithmetic using VHDL coding allows for low-cost and reprogrammable hardware. The design was synthesized using Xilinx tools and implemented on a Virtex-7 FPGA.
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...IRJET Journal
This document describes the implementation of an effective self-timed multiplier for single precision floating point values using a carry-look ahead adder. It begins by introducing floating point representation and the need for floating point arithmetic in applications requiring a large dynamic range. It then discusses the IEEE 754 standard for single precision floating point format and the steps to multiply two floating point values. The key aspects of the proposed self-timed multiplier are that it uses a carry-look ahead adder to add the exponents, making the operation faster than a traditional ripple carry adder. VHDL is used to design and simulate the self-timed multiplier, which is shown to correctly perform multiplications under normal, overflow, and underflow conditions.
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
Area and power performance analysis of floating point ALU using pipeliningIRJET Journal
This document discusses the area, power, and timing analysis of a pipelined floating point arithmetic logic unit (ALU) using Verilog on Cadence tools. It analyzes the performance of adders, subtractors, multipliers, and dividers implemented with and without pipelining at 45nm and 32nm technology nodes. Pipelining the units improves throughput by processing data in stages but increases area and power compared to non-pipelined designs. Analysis shows the pipelined units operate 0.0178 times faster while using more area and power.
Survey On Two-Term Dot Product Of Multiplier Using Floating PointIRJET Journal
This document summarizes a survey on using floating point in two-term dot product multipliers. It discusses how floating point can increase accuracy, speed, and performance while reducing delay, area, and power consumption. Floating point is commonly used in digital signal processing and graphics algorithms. The survey found that a "fused floating point" approach using both single and double precision in multiplication, addition, and subtraction can improve performance. The document then provides details on floating point number representation and the algorithms for floating point multiplication and dot product operations. It proposes that a fused floating point dot product unit using 48-bit double precision can reduce delay and silicon area compared to 32-bit single precision designs.
A Pipelined Fused Processing Unit for DSP Applicationsijiert bestjournal
This document describes the design of a pipelined processing unit for a DSP FFT processor. It includes fused floating point units like a dot product unit and add/subtract unit to perform FFT butterfly operations more efficiently. The dot product unit performs two multiplications and an addition/subtraction in one cycle to reduce latency and area compared to discrete implementations. The add/subtract unit calculates the sum and difference of two numbers in parallel. These fused units are used to implement a radix-2 FFT butterfly that is 20% faster and 30% smaller than a conventional design. The processing unit can perform 26 different floating point and logical operations needed for FFT processing. Simulation results show the performance benefits of the fused units and radix-2
IRJET- Fault- Tolerant Fir Filter ImplementationIRJET Journal
This document discusses the implementation of a fault-tolerant finite impulse response (FIR) filter using error correcting codes. FIR filters are widely used in digital signal processing but are susceptible to faults. The authors propose a scheme to implement FIR filters using Bose–Chaudhuri–Hocquenghem (BCH) codes to provide fault tolerance of up to 6 bits. They design FIR filters in MATLAB and implement error detection and correction using hardware description languages and field programmable gate arrays. Simulation results show the filter output is error-free even when the input contains errors, demonstrating the effectiveness of the fault-tolerant design.
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...jmicro
This document summarizes a paper that presents the design of a double precision floating point multiplication algorithm with vector support. It describes the IEEE 754 floating point number representation format, including single and double precision specifications. It also discusses rounding modes, special values like infinities and NaNs, and exceptions like invalid operations, division by zero, overflow, and underflow. Simulation results are shown for basic logic components and a floating point multiplier. Synthesis results are provided for single and double precision floating point multipliers. The paper concludes that a pipelined, vectorized floating point multiplier was implemented supporting FP16, FP32, and FP64 formats to reduce area, power, latency and increase throughput.
High Speed and Area Efficient Matrix Multiplication using Radix-4 Booth Multi...IRJET Journal
This document describes several designs for high-speed matrix multiplication. It proposes a new design called Parallel-Parallel Input Multi-Output (PPI-MO) that uses multiple multipliers and registers to perform matrix multiplication in parallel. This increases throughput. For an n×n matrix multiplication, it uses n2 multipliers, n2 registers, and n(n-2) adders. Elements of the first matrix are input to rows of multipliers simultaneously, while elements of the second matrix are input to columns. The partial products from each column are added to calculate elements of the output matrix.
This document presents a comparative study of implementing single precision floating point division using different computational algorithms on FPGAs. It describes two commonly used division algorithms: Goldschmidt and Newton-Raphson. The Goldschmidt algorithm continually multiplies the numerator and denominator by a common factor to converge the denominator to 1. The Newton-Raphson algorithm calculates the multiplicative inverse of the denominator through iterative processing. A 32-bit floating point divider is designed using a 32-bit floating point multiplier module based on 24-bit Vedic multiplication and a 32-bit floating point subtractor module. Synthesis results on a Xilinx Spartan 6 FPGA show the resource utilization and propagation delay for the proposed design, which is
A High Speed Transposed Form FIR Filter Using Floating Point Dadda MultiplierIJRES Journal
There is a huge demand in high speed area efficient parallel FIR filter using floating point dadda algorithm, due to increase performance of processing units. Area and spped are usually confictiong constraints so that improving speed results mostly in large areas. In our research we will try to determine the best solution to this problem by comparing the results of different multipliers. Different sized of two algorithm for high speed hardware multipliers were studied and implemented ie.dadda and booth multipliers. The working of these two multipliers were studied and implementing each of them separately in VHDL. The results of this research will help us to choose the better option between multipliers for floating point multiplier for fabricating different system.
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...IRJET Journal
This document describes the design of a bit manipulation instruction IP using Bluespec SystemVerilog for the RISC-V architecture. The IP implements 106 bit manipulation instructions proposed as an extension to the RISC-V instruction set. The design is a combinational logic block that takes instruction encoding and source operands as input and produces a result register in a single clock cycle. The IP was optimized to reduce logic gates and LUT count. Simulation results showed that all instructions executed correctly in a single cycle. Area analysis showed a reduction in LUT usage from optimizing common functions and reducing decoder multiplexer inputs.
This document summarizes an academic paper about implementing a floating point arithmetic unit using an FPGA that follows the IEEE 754-2008 standard for decimal64 numbers. It discusses the paper's abstract, introduction on digital arithmetic and floating point formats. It also provides background on the IEEE 754 standard, describing the basic single and double precision binary formats. The summary highlights that the implemented unit can perform addition, subtraction, multiplication and division on 64-bit operands and operates at 130MHz on a Cyclone-III FPGA with 8 cycle latency.
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‘Six Sigma Technique’ A Journey Through its Implementationijtsrd
The manufacturing industries all over the world are facing tough challenges for growth, development and sustainability in today’s competitive environment. They have to achieve apex position by adapting with the global competitive environment by delivering goods and services at low cost, prime quality and better price to increase wealth and consumer satisfaction. Cost Management ensures profit, growth and sustainability of the business with implementation of Continuous Improvement Technique like Six Sigma. This leads to optimize Business performance. The method drives for customer satisfaction, low variation, reduction in waste and cycle time resulting into a competitive advantage over other industries which did not implement it. The main objective of this paper ‘Six Sigma Technique A Journey Through Its Implementation’ is to conceptualize the effectiveness of Six Sigma Technique through the journey of its implementation. Aditi Sunilkumar Ghosalkar "‘Six Sigma Technique’: A Journey Through its Implementation" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64546.pdf Paper Url: https://www.ijtsrd.com/other-scientific-research-area/other/64546/‘six-sigma-technique’-a-journey-through-its-implementation/aditi-sunilkumar-ghosalkar
Edge Computing in Space Enhancing Data Processing and Communication for Space...ijtsrd
Edge computing, a paradigm that involves processing data closer to its source, has gained significant attention for its potential to revolutionize data processing and communication in space missions. With the increasing complexity and data volume generated by modern space missions, traditional centralized computing approaches face challenges related to latency, bandwidth, and security. Edge computing in space, involving on board processing and analysis of data, offers promising solutions to these challenges. This paper explores the concept of edge computing in space, its benefits, applications, and future prospects in enhancing space missions. Manish Verma "Edge Computing in Space: Enhancing Data Processing and Communication for Space Missions" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64541.pdf Paper Url: https://www.ijtsrd.com/computer-science/artificial-intelligence/64541/edge-computing-in-space-enhancing-data-processing-and-communication-for-space-missions/manish-verma
Dynamics of Communal Politics in 21st Century India Challenges and Prospectsijtsrd
Communal politics in India has evolved through centuries, weaving a complex tapestry shaped by historical legacies, colonial influences, and contemporary socio political transformations. This research comprehensively examines the dynamics of communal politics in 21st century India, emphasizing its historical roots, socio political dynamics, economic implications, challenges, and prospects for mitigation. The historical perspective unravels the intricate interplay of religious identities and power dynamics from ancient civilizations to the impact of colonial rule, providing insights into the evolution of communalism. The socio political dynamics section delves into the contemporary manifestations, exploring the roles of identity politics, socio economic disparities, and globalization. The economic implications section highlights how communal politics intersects with economic issues, perpetuating disparities and influencing resource allocation. Challenges posed by communal politics are scrutinized, revealing multifaceted issues ranging from social fragmentation to threats against democratic values. The prospects for mitigation present a multifaceted approach, incorporating policy interventions, community engagement, and educational initiatives. The paper conducts a comparative analysis with international examples, identifying common patterns such as identity politics and economic disparities. It also examines unique challenges, emphasizing Indias diverse religious landscape, historical legacy, and secular framework. Lessons for effective strategies are drawn from international experiences, offering insights into inclusive policies, interfaith dialogue, media regulation, and global cooperation. By scrutinizing historical epochs, contemporary dynamics, economic implications, and international comparisons, this research provides a comprehensive understanding of communal politics in India. The proposed strategies for mitigation underscore the importance of a holistic approach to foster social harmony, inclusivity, and democratic values. Rose Hossain "Dynamics of Communal Politics in 21st Century India: Challenges and Prospects" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64528.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/history/64528/dynamics-of-communal-politics-in-21st-century-india-challenges-and-prospects/rose-hossain
Assess Perspective and Knowledge of Healthcare Providers Towards Elehealth in...ijtsrd
Background and Objective Telehealth has become a well known tool for the delivery of health care in Saudi Arabia, and the perspective and knowledge of healthcare providers are influential in the implementation, adoption and advancement of the method. This systematic review was conducted to examine the current literature base regarding telehealth and the related healthcare professional perspective and knowledge in the Kingdom of Saudi Arabia. Materials and Methods This systematic review was conducted by searching 7 databases including, MEDLINE, CINHAL, Web of Science, Scopus, PubMed, PsycINFO, and ProQuest Central. Studies on healthcare practitioners telehealth knowledge and perspectives published in English in Saudi Arabia from 2000 to 2023 were included. Boland directed this comprehensive review. The researchers examined each connected study using the AXIS tool, which evaluates cross sectional systematic reviews. Narrative synthesis was used to summarise and convey the data. Results Out of 1840 search results, 10 studies were included. Positive outlook and limited knowledge among providers were seen across trials. Healthcare professionals like telehealth for its ability to improve quality, access, and delivery, save time and money, and be successful. Age, gender, occupation, and work experience also affect health workers knowledge. In Saudi Arabia, healthcare professionals face inadequate expert assistance, patient privacy, internet connection concerns, lack of training courses, lack of telehealth understanding, and high costs while performing telemedicine. Conclusions Healthcare practitioners telehealth perceptions and knowledge were examined in this systematic study. Its collection of concerned experts different personal attitudes and expertise would help enhance telehealths implementation in Saudi Arabia, develop its healthcare delivery alternative, and eliminate frequent problems. Badriah Mousa I Mulayhi | Dr. Jomin George | Judy Jenkins "Assess Perspective and Knowledge of Healthcare Providers Towards Elehealth in Saudi Arabia: A Systematic Review" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64535.pdf Paper Url: https://www.ijtsrd.com/medicine/other/64535/assess-perspective-and-knowledge-of-healthcare-providers-towards-elehealth-in-saudi-arabia-a-systematic-review/badriah-mousa-i-mulayhi
The Impact of Digital Media on the Decentralization of Power and the Erosion ...ijtsrd
The impact of digital media on the distribution of power and the weakening of traditional gatekeepers has gained considerable attention in recent years. The adoption of digital technologies and the internet has resulted in declining influence and power for traditional gatekeepers such as publishing houses and news organizations. Simultaneously, digital media has facilitated the emergence of new voices and players in the media industry. Digital medias impact on power decentralization and gatekeeper erosion is visible in several ways. One significant aspect is the democratization of information, which enables anyone with an internet connection to publish and share content globally, leading to citizen journalism and bypassing traditional gatekeepers. Another aspect is the disruption of conventional media industry business models, as traditional organizations struggle to adjust to the decrease in advertising revenue and the rise of digital platforms. Alternative business models, such as subscription models and crowdfunding, have become more prevalent, leading to the emergence of new players. Overall, the impact of digital media on the distribution of power and the weakening of traditional gatekeepers has brought about significant changes in the media landscape and the way information is shared. Further research is required to fully comprehend the implications of these changes and their impact on society. Dr. Kusum Lata "The Impact of Digital Media on the Decentralization of Power and the Erosion of Traditional Gatekeepers" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64544.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/political-science/64544/the-impact-of-digital-media-on-the-decentralization-of-power-and-the-erosion-of-traditional-gatekeepers/dr-kusum-lata
Online Voices, Offline Impact Ambedkars Ideals and Socio Political Inclusion ...ijtsrd
This research investigates the nexus between online discussions on Dr. B.R. Ambedkars ideals and their impact on social inclusion among college students in Gurugram, Haryana. Surveying 240 students from 12 government colleges, findings indicate that 65 actively engage in online discussions, with 80 demonstrating moderate to high awareness of Ambedkars ideals. Statistically significant correlations reveal that higher online engagement correlates with increased awareness p 0.05 and perceived social inclusion. Variations across colleges and a notable effect of college type on perceived social inclusion highlight the influence of contextual factors. Furthermore, the intersectional analysis underscores nuanced differences based on gender, caste, and socio economic status. Dr. Kusum Lata "Online Voices, Offline Impact: Ambedkar's Ideals and Socio-Political Inclusion - A Study of Gurugram District" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64543.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/political-science/64543/online-voices-offline-impact-ambedkars-ideals-and-sociopolitical-inclusion--a-study-of-gurugram-district/dr-kusum-lata
Problems and Challenges of Agro Entreprenurship A Studyijtsrd
Noting calls for contextualizing Agro entrepreneurs problems and challenges of the agro entrepreneurs and for greater attention to the Role of entrepreneurs in agro entrepreneurship research, we conduct a systematic literature review of extent research in agriculture entrepreneurship to overcome the study objectives of complications of agro entrepreneurs through various factors, Development of agriculture products is a key factor for the overall economic growth of agro entrepreneurs Agro Entrepreneurs produces firsthand large scale employment, utilizes the labor and natural resources, This research outlines the problems of Weather and Soil Erosions, Market price fluctuation, stimulates labor cost problems, reduces concentration of Price volatility, Dependency on Intermediaries, induces Limited Bargaining Power, and Storage and Transportation Costs. This paper mainly devoted to highlight Problems and challenges faced for the sustainable of Agro Entrepreneurs in India. Vinay Prasad B "Problems and Challenges of Agro Entreprenurship - A Study" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64540.pdf Paper Url: https://www.ijtsrd.com/other-scientific-research-area/other/64540/problems-and-challenges-of-agro-entreprenurship--a-study/vinay-prasad-b
Comparative Analysis of Total Corporate Disclosure of Selected IT Companies o...ijtsrd
Disclosure is a process through which a business enterprise communicates with external parties. A corporate disclosure is communication of financial and non financial information of the activities of a business enterprise to the interested entities. Corporate disclosure is done through publishing annual reports. So corporate disclosure through annual reports plays a vital role in the life of all the companies and provides valuable information to investors. The basic objectives of corporate disclosure is to give a true and fair view of companies to the parties related either directly or indirectly like owner, government, creditors, shareholders etc. in the companies act, provisions have been made about mandatory and voluntary disclosure. The IT sector in India is rapidly growing, the trend to invest in the IT sector is rising and employment opportunities in IT sectors are also increasing. Therefore the IT sector is expected to have fair, full and adequate disclosure of all information. Unfair and incomplete disclosure may adversely affect the entire economy. A research study on disclosure practices of IT companies could play an important role in this regard. Hence, the present research study has been done to study and review comparative analysis of total corporate disclosure of selected IT companies of India and to put forward overall findings and suggestions with a view to increase disclosure score of these companies. The researcher hopes that the present research study will be helpful to all selected Companies for improving level of corporate disclosure through annual reports as well as the government, creditors, investors, all business organizations and upcoming researcher for comparative analyses of level of corporate disclosure with special reference to selected IT companies. Dr. Vaibhavi D. Thaker "Comparative Analysis of Total Corporate Disclosure of Selected IT Companies of India" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64539.pdf Paper Url: https://www.ijtsrd.com/other-scientific-research-area/other/64539/comparative-analysis-of-total-corporate-disclosure-of-selected-it-companies-of-india/dr-vaibhavi-d-thaker
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A Study on the Effective Teaching Learning Process in English Curriculum at t...ijtsrd
“One Language sets you in a corridor for life. Two languages open every door along the way” Frank Smith English as a foreign language or as a second language has been ruling in India since the period of Lord Macaulay. But the question is how much we teach or learn English properly in our culture. Is there any scope to use English as a language rather than a subject How much we learn or teach English without any interference of mother language specially in the classroom teaching learning scenario in West Bengal By considering all these issues the researcher has attempted in this article to focus on the effective teaching learning process comparing to other traditional strategies in the field of English curriculum at the secondary level to investigate whether they fulfill the present teaching learning requirements or not by examining the validity of the present curriculum of English. The purpose of this study is to focus on the effectiveness of the systematic, scientific, sequential and logical transaction of the course between the teachers and the learners in the perspective of the 5Es programme that is engage, explore, explain, extend and evaluate. Sanchali Mondal | Santinath Sarkar "A Study on the Effective Teaching Learning Process in English Curriculum at the Secondary Level of West Bengal" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd62412.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/education/62412/a-study-on-the-effective-teaching-learning-process-in-english-curriculum-at-the-secondary-level-of-west-bengal/sanchali-mondal
The Role of Mentoring and Its Influence on the Effectiveness of the Teaching ...ijtsrd
This paper reports on a study which was conducted to investigate the role of mentoring and its influence on the effectiveness of the teaching of Physics in secondary schools in the South West Region of Cameroon. The study adopted the convergent parallel mixed methods design, focusing on respondents in secondary schools in the South West Region of Cameroon. Both quantitative and qualitative data were collected, analysed separately, and the results were compared to see if the findings confirm or disconfirm each other. The quantitative analysis found that majority of the respondents 72 of Physics teachers affirmed that they had more experienced colleagues as mentors to help build their confidence, improve their teaching, and help them improve their effectiveness and efficiency in guiding learners’ achievements. Only 28 of the respondents disagreed with these statements. With majority respondents 72 agreeing with the statements, it implies that in most secondary schools, experienced Physics teachers act as mentors to build teachers’ confidence in teaching and improving students’ learning. The interview qualitative data analysis summarized how secondary school Principals use meetings with mentors and mentees to promote mentorship in the school milieu. This has helped strengthen teachers’ classroom practices in secondary schools in the South West Region of Cameroon. With the results confirming each other, the study recommends that mentoring should focus on helping teachers employ social interactions and instructional practices feedback and clarity in teaching that have direct measurable impact on students’ learning achievements. Andrew Ngeim Sumba | Frederick Ebot Ashu | Peter Agborbechem Tambi "The Role of Mentoring and Its Influence on the Effectiveness of the Teaching of Physics in Secondary Schools in the South West Region of Cameroon" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64524.pdf Paper Url: https://www.ijtsrd.com/management/management-development/64524/the-role-of-mentoring-and-its-influence-on-the-effectiveness-of-the-teaching-of-physics-in-secondary-schools-in-the-south-west-region-of-cameroon/andrew-ngeim-sumba
Design Simulation and Hardware Construction of an Arduino Microcontroller Bas...ijtsrd
This study primarily focuses on the design of a high side buck converter using an Arduino microcontroller. The converter is specifically intended for use in DC DC applications, particularly in standalone solar PV systems where the PV output voltage exceeds the load or battery voltage. To evaluate the performance of the converter, simulation experiments are conducted using Proteus Software. These simulations provide insights into the input and output voltages, currents, powers, and efficiency under different state of charge SoC conditions of a 12V,70Ah rechargeable lead acid battery. Additionally, the hardware design of the converter is implemented, and practical data is collected through operation, monitoring, and recording. By comparing the simulation results with the practical results, the efficiency and performance of the designed converter are assessed. The findings indicate that while the buck converter is suitable for practical use in standalone PV systems, its efficiency is compromised due to a lower output current. Chan Myae Aung | Dr. Ei Mon "Design Simulation and Hardware Construction of an Arduino-Microcontroller Based DC-DC High-Side Buck Converter for Standalone PV System" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64518.pdf Paper Url: https://www.ijtsrd.com/engineering/mechanical-engineering/64518/design-simulation-and-hardware-construction-of-an-arduinomicrocontroller-based-dcdc-highside-buck-converter-for-standalone-pv-system/chan-myae-aung
Sustainable Energy by Paul A. Adekunte | Matthew N. O. Sadiku | Janet O. Sadikuijtsrd
Energy becomes sustainable if it meets the needs of the present without compromising the ability of future generations to meet their own needs. Some of the definitions of sustainable energy include the considerations of environmental aspects such as greenhouse gas emissions, social, and economic aspects such as energy poverty. Generally far more sustainable than fossil fuel are renewable energy sources such as wind, hydroelectric power, solar, and geothermal energy sources. Worthy of note is that some renewable energy projects, like the clearing of forests to produce biofuels, can cause severe environmental damage. The sustainability of nuclear power which is a low carbon source is highly debated because of concerns about radioactive waste, nuclear proliferation, and accidents. The switching from coal to natural gas has environmental benefits, including a lower climate impact, but could lead to delay in switching to more sustainable options. “Carbon capture and storage” can be built into power plants to remove the carbon dioxide CO2 emissions, but this technology is expensive and has rarely been implemented. Leading non renewable energy sources around the world is fossil fuels, coal, petroleum, and natural gas. Nuclear energy is usually considered another non renewable energy source, although nuclear energy itself is a renewable energy source, but the material used in nuclear power plants is not. The paper addresses the issue of sustainable energy, its attendant benefits to the future generation, and humanity in general. Paul A. Adekunte | Matthew N. O. Sadiku | Janet O. Sadiku "Sustainable Energy" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64534.pdf Paper Url: https://www.ijtsrd.com/engineering/electrical-engineering/64534/sustainable-energy/paul-a-adekunte
Concepts for Sudan Survey Act Implementations Executive Regulations and Stand...ijtsrd
This paper aims to outline the executive regulations, survey standards, and specifications required for the implementation of the Sudan Survey Act, and for regulating and organizing all surveying work activities in Sudan. The act has been discussed for more than 5 years. The Land Survey Act was initiated by the Sudan Survey Authority and all official legislations were headed by the Sudan Ministry of Justice till it was issued in 2022. The paper presents conceptual guidelines to be used for the Survey Act implementation and to regulate the survey work practice, standardizing the field surveys, processing, quality control, procedures, and the processes related to survey work carried out by the stakeholders and relevant authorities in Sudan. The conceptual guidelines are meant to improve the quality and harmonization of geospatial data and to aid decision making processes as well as geospatial information systems. The established comprehensive executive regulations will govern and regulate the implementation of the Sudan Survey Geomatics Act in all surveying and mapping practices undertaken by the Sudan Survey Authority SSA and state local survey departments for public or private sector organizations. The targeted standards and specifications include the reference frame, projection, coordinate systems, and the guidelines and specifications that must be followed in the field of survey work, processes, and mapping products. In the last few decades, there has been a growing awareness of the importance of geomatics activities and measurements on the Earths surface in space and time, together with observing and mapping the changes. In such cases, data must be captured promptly, standardized, and obtained with more accuracy and specified in much detail. The paper will also highlight the current situation in Sudan, the degree to which survey standards are used, the problems encountered, and the errors that arise from not using the standards and survey specifications. Kamal A. A. Sami "Concepts for Sudan Survey Act Implementations - Executive Regulations and Standards" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd63484.pdf Paper Url: https://www.ijtsrd.com/engineering/civil-engineering/63484/concepts-for-sudan-survey-act-implementations--executive-regulations-and-standards/kamal-a-a-sami
Towards the Implementation of the Sudan Interpolated Geoid Model Khartoum Sta...ijtsrd
The discussions between ellipsoid and geoid have invoked many researchers during the recent decades, especially during the GNSS technology era, which had witnessed a great deal of development but still geoid undulation requires more investigations. To figure out a solution for Sudans local geoid, this research has tried to intake the possibility of determining the geoid model by following two approaches, gravimetric and geometrical geoid model determination, by making use of GNSS leveling benchmarks at Khartoum state. The Benchmarks are well distributed in the study area, in which, the horizontal coordinates and the height above the ellipsoid have been observed by GNSS while orthometric heights were carried out using precise leveling. The Global Geopotential Model GGM represented in EGM2008 has been exploited to figure out the geoid undulation at the benchmarks in the study area. This is followed by a fitting process, that has been done to suit the geoid undulation data which has been computed using GNSS leveling data and geoid undulation inspired by the EGM2008. Two geoid surfaces were created after the fitting process to ensure that they are identical and both of them could be counted for getting the same geoid undulation with an acceptable accuracy. In this respect, statistical operation played an important role in ensuring the consistency and integrity of the model by applying cross validation techniques splitting the data into training and testing datasets for building the geoid model and testing its eligibility. The geometrical solution for geoid undulation computation has been utilized by applying straightforward equations that facilitate the calculation of the geoid undulation directly through applying statistical techniques for the GNSS leveling data of the study area to get the common equation parameters values that could be utilized to calculate geoid undulation of any position in the study area within the claimed accuracy. Both systems were checked and proved eligible to be used within the study area with acceptable accuracy which may contribute to solving the geoid undulation problem in the Khartoum area, and be further generalized to determine the geoid model over the entire country, and this could be considered in the future, for regional and continental geoid model. Ahmed M. A. Mohammed. | Kamal A. A. Sami "Towards the Implementation of the Sudan Interpolated Geoid Model (Khartoum State Case Study)" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd63483.pdf Paper Url: https://www.ijtsrd.com/engineering/civil-engineering/63483/towards-the-implementation-of-the-sudan-interpolated-geoid-model-khartoum-state-case-study/ahmed-m-a-mohammed
Activating Geospatial Information for Sudans Sustainable Investment Mapijtsrd
Sudan is witnessing an acceleration in the processes of development and transformation in the performance of government institutions to raise the productivity and investment efficiency of the government sector. The development plans and investment opportunities have focused on achieving national goals in various sectors. This paper aims to illuminate the path to the future and provide geospatial data and information to develop the investment climate and environment for all sized businesses, and to bridge the development gap between the Sudan states. The Sudan Survey Authority SSA is the main advisor to the Sudan Government in conducting surveying, mappings, designing, and developing systems related to geospatial data and information. In recent years, SSA made a strategic partnership with the Ministry of Investment to activate Geospatial Information for Sudans Sustainable Investment and in particular, for the preparation and implementation of the Sudan investment map, based on the directives and objectives of the Ministry of Investment MI in Sudan. This paper comes within the framework of activating the efforts of the Ministry of Investment to develop technical investment services by applying techniques adopted by the Ministry and its strategic partners for advancing investment processes in the country. Kamal A. A. Sami "Activating Geospatial Information for Sudan's Sustainable Investment Map" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd63482.pdf Paper Url: https://www.ijtsrd.com/engineering/information-technology/63482/activating-geospatial-information-for-sudans-sustainable-investment-map/kamal-a-a-sami
Educational Unity Embracing Diversity for a Stronger Societyijtsrd
In a rapidly changing global landscape, the importance of education as a unifying force cannot be overstated. This paper explores the crucial role of educational unity in fostering a stronger and more inclusive society through the embrace of diversity. By examining the benefits of diverse learning environments, the paper aims to highlight the positive impact on societal strength. The discussion encompasses various dimensions, from curriculum design to classroom dynamics, and emphasizes the need for educational institutions to become catalysts for unity in diversity. It highlights the need for a paradigm shift in educational policies, curricula, and pedagogical approaches to ensure that they are reflective of the diverse fabric of society. This paper also addresses the challenges associated with implementing inclusive educational practices and offers practical strategies for overcoming barriers. It advocates for collaborative efforts between educational institutions, policymakers, and communities to create a supportive ecosystem that promotes diversity and unity. Mr. Amit Adhikari | Madhumita Teli | Gopal Adhikari "Educational Unity: Embracing Diversity for a Stronger Society" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64525.pdf Paper Url: https://www.ijtsrd.com/humanities-and-the-arts/education/64525/educational-unity-embracing-diversity-for-a-stronger-society/mr-amit-adhikari
Integration of Indian Indigenous Knowledge System in Management Prospects and...ijtsrd
The diversity of indigenous knowledge systems in India is vast and can vary significantly between different communities and regions. Preserving and respecting these knowledge systems is crucial for maintaining cultural heritage, promoting sustainable practices, and fostering cross cultural understanding. In this paper, an overview of the prospects and challenges associated with incorporating Indian indigenous knowledge into management is explored. It is found that IIKS helps in management in many areas like sustainable development, tourism, food security, natural resource management, cultural preservation and innovation, etc. However, IIKS integration with management faces some challenges in the form of a lack of documentation, cultural sensitivity, language barriers legal framework, etc. Savita Lathwal "Integration of Indian Indigenous Knowledge System in Management: Prospects and Challenges" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd63500.pdf Paper Url: https://www.ijtsrd.com/management/accounting-and-finance/63500/integration-of-indian-indigenous-knowledge-system-in-management-prospects-and-challenges/savita-lathwal
DeepMask Transforming Face Mask Identification for Better Pandemic Control in...ijtsrd
The COVID 19 pandemic has highlighted the crucial need of preventive measures, with widespread use of face masks being a key method for slowing the viruss spread. This research investigates face mask identification using deep learning as a technological solution to be reducing the risk of coronavirus transmission. The proposed method uses state of the art convolutional neural networks CNNs and transfer learning to automatically recognize persons who are not wearing masks in a variety of circumstances. We discuss how this strategy improves public health and safety by providing an efficient manner of enforcing mask wearing standards. The report also discusses the obstacles, ethical concerns, and prospective applications of face mask detection systems in the ongoing fight against the pandemic. Dilip Kumar Sharma | Aaditya Yadav "DeepMask: Transforming Face Mask Identification for Better Pandemic Control in the COVID-19 Era" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64522.pdf Paper Url: https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/64522/deepmask-transforming-face-mask-identification-for-better-pandemic-control-in-the-covid19-era/dilip-kumar-sharma
Streamlining Data Collection eCRF Design and Machine Learningijtsrd
Efficient and accurate data collection is paramount in clinical trials, and the design of Electronic Case Report Forms eCRFs plays a pivotal role in streamlining this process. This paper explores the integration of machine learning techniques in the design and implementation of eCRFs to enhance data collection efficiency. We delve into the synergies between eCRF design principles and machine learning algorithms, aiming to optimize data quality, reduce errors, and expedite the overall data collection process. The application of machine learning in eCRF design brings forth innovative approaches to data validation, anomaly detection, and real time adaptability. This paper discusses the benefits, challenges, and future prospects of leveraging machine learning in eCRF design for streamlined and advanced data collection in clinical trials. Dhanalakshmi D | Vijaya Lakshmi Kannareddy "Streamlining Data Collection: eCRF Design and Machine Learning" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-1 , February 2024, URL: https://www.ijtsrd.com/papers/ijtsrd63515.pdf Paper Url: https://www.ijtsrd.com/biological-science/biotechnology/63515/streamlining-data-collection-ecrf-design-and-machine-learning/dhanalakshmi-d
Elevate Your Nonprofit's Online Presence_ A Guide to Effective SEO Strategies...TechSoup
Whether you're new to SEO or looking to refine your existing strategies, this webinar will provide you with actionable insights and practical tips to elevate your nonprofit's online presence.
Creative Restart 2024: Mike Martin - Finding a way around “no”Taste
Ideas that are good for business and good for the world that we live in, are what I’m passionate about.
Some ideas take a year to make, some take 8 years. I want to share two projects that best illustrate this and why it is never good to stop at “no”.
🔥🔥🔥🔥🔥🔥🔥🔥🔥
إضغ بين إيديكم من أقوى الملازم التي صممتها
ملزمة تشريح الجهاز الهيكلي (نظري 3)
💀💀💀💀💀💀💀💀💀💀
تتميز هذهِ الملزمة بعِدة مُميزات :
1- مُترجمة ترجمة تُناسب جميع المستويات
2- تحتوي على 78 رسم توضيحي لكل كلمة موجودة بالملزمة (لكل كلمة !!!!)
#فهم_ماكو_درخ
3- دقة الكتابة والصور عالية جداً جداً جداً
4- هُنالك بعض المعلومات تم توضيحها بشكل تفصيلي جداً (تُعتبر لدى الطالب أو الطالبة بإنها معلومات مُبهمة ومع ذلك تم توضيح هذهِ المعلومات المُبهمة بشكل تفصيلي جداً
5- الملزمة تشرح نفسها ب نفسها بس تكلك تعال اقراني
6- تحتوي الملزمة في اول سلايد على خارطة تتضمن جميع تفرُعات معلومات الجهاز الهيكلي المذكورة في هذهِ الملزمة
واخيراً هذهِ الملزمة حلالٌ عليكم وإتمنى منكم إن تدعولي بالخير والصحة والعافية فقط
كل التوفيق زملائي وزميلاتي ، زميلكم محمد الذهبي 💊💊
🔥🔥🔥🔥🔥🔥🔥🔥🔥
How to Manage Reception Report in Odoo 17Celine George
A business may deal with both sales and purchases occasionally. They buy things from vendors and then sell them to their customers. Such dealings can be confusing at times. Because multiple clients may inquire about the same product at the same time, after purchasing those products, customers must be assigned to them. Odoo has a tool called Reception Report that can be used to complete this assignment. By enabling this, a reception report comes automatically after confirming a receipt, from which we can assign products to orders.
A Free 200-Page eBook ~ Brain and Mind Exercise.pptxOH TEIK BIN
(A Free eBook comprising 3 Sets of Presentation of a selection of Puzzles, Brain Teasers and Thinking Problems to exercise both the mind and the Right and Left Brain. To help keep the mind and brain fit and healthy. Good for both the young and old alike.
Answers are given for all the puzzles and problems.)
With Metta,
Bro. Oh Teik Bin 🙏🤓🤔🥰
Andreas Schleicher presents PISA 2022 Volume III - Creative Thinking - 18 Jun...EduSkills OECD
Andreas Schleicher, Director of Education and Skills at the OECD presents at the launch of PISA 2022 Volume III - Creative Minds, Creative Schools on 18 June 2024.
THE SACRIFICE HOW PRO-PALESTINE PROTESTS STUDENTS ARE SACRIFICING TO CHANGE T...indexPub
The recent surge in pro-Palestine student activism has prompted significant responses from universities, ranging from negotiations and divestment commitments to increased transparency about investments in companies supporting the war on Gaza. This activism has led to the cessation of student encampments but also highlighted the substantial sacrifices made by students, including academic disruptions and personal risks. The primary drivers of these protests are poor university administration, lack of transparency, and inadequate communication between officials and students. This study examines the profound emotional, psychological, and professional impacts on students engaged in pro-Palestine protests, focusing on Generation Z's (Gen-Z) activism dynamics. This paper explores the significant sacrifices made by these students and even the professors supporting the pro-Palestine movement, with a focus on recent global movements. Through an in-depth analysis of printed and electronic media, the study examines the impacts of these sacrifices on the academic and personal lives of those involved. The paper highlights examples from various universities, demonstrating student activism's long-term and short-term effects, including disciplinary actions, social backlash, and career implications. The researchers also explore the broader implications of student sacrifices. The findings reveal that these sacrifices are driven by a profound commitment to justice and human rights, and are influenced by the increasing availability of information, peer interactions, and personal convictions. The study also discusses the broader implications of this activism, comparing it to historical precedents and assessing its potential to influence policy and public opinion. The emotional and psychological toll on student activists is significant, but their sense of purpose and community support mitigates some of these challenges. However, the researchers call for acknowledging the broader Impact of these sacrifices on the future global movement of FreePalestine.
2. International Journal of Trend in Scientific Research and Development (IJTSRD) @ www.ijtsrd.com eISSN: 2456-6470
@ IJTSRD | Unique Paper ID – IJTSRD38049 | Volume – 5 | Issue – 1 | November-December 2020 Page 779
data in floating point format is more exact than fixed point
format [8].
1.4. Applications of floating-point representation
Scientific and higher engineering applications demand
exceptionally high floating point performance which in turn
requires high speed floating point units to reduce executing
time. Floating Point units are used in high speed objects
recognition system and also in high performance computer
systems as well as embedded systems and mobile
applications [2]. Floating point units are widely used in
digital applications such as digital signal processing, digital
image processing and multimedia [5]. In medical image
recognition, greater accuracy supports the many levels of
signal input from light, x-rays, ultrasound and other sources
that must be defined and processed to create output images
with useful diagnostic information. Wide dynamic range is
essential to radar, where a system may need to track over a
range from zero to infinity, and then use only a small subset
of that range for target acquisition and identification.Awide
dynamic range can also allow a robot to deal with
unpredictable conditions, such as an obstruction to its
normally limited range of motion. By contrast with these
applications, the enormouscommunicationsmarketisbetter
served by floating-point devices [8].
The floating point format is also very useful for audio and
video applications. Audio needs wider range of values than
video applications that requirement id fulfilled by floating
point hardware [6]. Floating point unit performs addition,
subtraction, multiplication, division, square root etcthatare
widely used in large set of scientific,commerce,financial and
in signal processing applications [7].
2. Floating Point Arithmetic Unit
The block diagram of the proposed floating point arithmetic
unit is given in figure 3. The unit supports four arithmetic
operations: Add, Subtract, Multiply and Divide. All the basic
mathematical arithmetic operationshave beencarriedoutin
four separate modules one for addition, one for subtraction,
one for multiplication and one for division.
The unit has following inputs:
1. Two 64-bit input operands
2. One 3-bit operation code (3 bits, 000 = add, 001 =
subtract, 010 = multiply, 011 divide)
3. Rounding mode (2 bits, 00 = nearest, 01 = zero, 10 =
possitive infinity, 11 = negative infinity)
4. Reset (Global) 5. Clock (Global)
Figure 3: Block Diagram of FPAU
The unit has following outputs:
1. 64-bit output
2. Five Exceptions
2.1. Inexact
2.2. Invalid
2.3. Overflow
2.4. Underflow
2.5. Divide-by-zero
In this design the operation to be performed on the 64-bit
operands by a 3-bit operational code and the same
operational code selects the output from that particular
module and connects it to the final output of the unit.
Particular exception signal will be high whenever that type
of exception wills occur. In this design the complex logic
operations segmented and implemented into various
multiple numbers of stages are converted into single stage
implementation in simplewordswecansaythatthemultiple
stages are converted into single stage. Once the inputs are
applied to the input terminals the final output is obtained at
the output terminals there are no intermediate stages. So
now the inputs take less time to reach at output terminals
and due to single stage implementation the number of flip
flops and other intermediate required circuits are less as a
result the area require is less in the presented design.
2.1. Fpu_Add - Floating Point Adder-
Two floating point numbers are added as shown.
(f1 x 2E1) + (f2 x 2E2) = F x 2E
Figure 4: RTL view of double precision floating point
arithmetic unit
In order to add two fractions, the associatedexponentsmust
be equal. Thus, if the exponents E1 and E2 are different, we
must normalize one ofthefractionsandadjusttheexponents
accordingly. The smaller number is the one that should
adjusted so that if significant digits are lost, the effect is not
significant.
The steps required to carry out floating point addition
are as follows:
1. Compare exponents. If the exponents arenotequal,shift
the fraction with the smaller exponent rightandadd1to
its exponent; repeat until the exponents are equal.
3. International Journal of Trend in Scientific Research and Development (IJTSRD) @ www.ijtsrd.com eISSN: 2456-6470
@ IJTSRD | Unique Paper ID – IJTSRD38049 | Volume – 5 | Issue – 1 | November-December 2020 Page 780
2. Add the fractions.
3. If the result is 0, set the exponents to the appropriate
representation for 0 and exit.
4. If fraction overflow occurs, shift right and add 1 to the
exponent to correct the overflow.
5. If the fraction is un normalized, shift left and subtracts1
from the exponent until the fraction is normalized.
6. Check for exponent overflow. Set overflow indicator, if
necessary
7. Round to the appropriate number of bits.
2.2. Fpu_Sub- Floating Point Subtractor
Two floating point numbers are subtracted as shown.
(f1 x 2E1 ) - (f2 x 2E2) = F x 2E
In order to subtract two fractions, the associated exponents
must be equal. Thus, if the exponents E1 and E2 are different,
we must unnormalize one of the fractions and adjust the
exponents accordingly. The smaller number is the one that
should adjusted so that if significant digits are lost, theeffect
is not significant.
The steps required to carry out floating point
subtraction are as follows:
1. Compare exponents. If the exponents arenotequal,shift
the fraction with the smaller exponent rightandadd1to
its exponent; repeat until the exponents are equal.
2. Subtract the fractions.
3. If the result is 0, set the exponents to the appropriate
representation for 0 and exit.
4. If fraction overflow occurs, shift right and add 1 to the
exponent to correct the overflow.
5. If the fraction is un normalized, shift left and subtracts1
from the exponent until the fraction is normalized.
6. Check for exponent overflow. Set overflow indicator, if
necessary
7. Round to the appropriate number of bits. Still
normalized? Go to back to step 4.
2.3. Fpu_Mul- Floating Point Multiplier-
Two floating point numbers are multiplied as shown.
(f1 x 2E1) x (f2 x 2E2) = (f1 x f2) x 2(E1+E2) = F x 2E
In this section, the design of multiplier for 64-bit floating
point numbers is proposed. The fraction part of the product
is the product of the fractions, and exponent part of the
product is the sum of the exponents.
The general procedure for performing floating point
multiplication is the following:
1. Add the exponents
2. Multiply the two fractions
3. If the product is zero, adjust the representation to the
proper representation for zero.
A. If the product fraction is too big, normalize by
shifting it right and incrementing the exponent.
B. If the product fraction is too small, normalize by
shifting left and decrementing the exponent .
4. If an exponent underflow or overflow occurs, generate
an exception or error indicator.
5. Round to the appropriate number of bits. If rounding
resulted in loss of normalization, go to step 3 again.
2.4. Fpu_Div- Floating Point Division
In this section, divider for floating point numbers is
designed. It uses 4 bit fractions and 4 bit exponents, with
negative numbers representedin2’scomplement.Giventwo
floating point numbers, the product is
(f1 x 2E1) / (f2 x 2E2) = (f1 / f2) x 2(E1-E2) = F x 2E
The floating point division is like a basic fixed point binary
number division algorithm.
The general procedure for performingfloatingpointdivision
is the following:
1. Left shift divisor by the no. of bits and right shift
dividend by no. of bits.
2. Compare the divisor with the dividend.
3. If divisor is greater than dividend set the corresponding
quotient bit to zero.
4. If divisor is less than dividend subtract the divisor from
the dividend and place the result in the divisor place,
and put one in quotient position.
5. After each comparison right shift divisor by one
position.
6. Repeat the above steps by the number of bits time.
7. The number in the dividend place gives remainder and
quotient place gives quotient.
2.5. Fpu_Round-Floating Point Rounding Unit-
Rounding module is used to modifies a number and fit it in
the destination’s format. It is performed in the fpu_round
module. From the core mathematical operations such as
addition, subtraction, Multiplication and divisionthesignals
are given to fpu round part of unit. The fpu round perform
rounding operation and in this unit four rounding modesare
defined.
The standard defines the following four rounding modes
Round to nearest even: It is a default roundingstandard.In
this standard the value is rounded up or down to the nearest
infinitely precise result.
Unrounded Rounded
3.5 4
3.4 3
5.6 6
Table 1 Examples for Round to nearest even
Round-to-Zero: In this rounding mode the excess bits will
be truncated. e.g. 3.47 will be truncated to 3.5
Round-Up: In this rounding mode the number will be
rounded up towards positive infinity,e.g.5.2will be rounded
to 6, while -4.2 to -4
Round-Down: In this rounding mode the number will be
rounded down towards negative infinity. e.g. 5.2 will be
rounded to 5, while -4.2 to -5
2.6. Fpu_Exception- Floating Point Exception Unit-
The exceptions are occurring when an operation on any
particular operands has no outputs suitable fora reasonable
application.
The five exceptions are:
Invalid: The results which are not valid for any simple
application is called invalid exception. For example square
root of a negative number etc., output of which does not
exist.
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Division by zero: This type of exceptions is occurs when
there is infinite in the result. For e.g., 1/0 or log (0) that
returns positive or negative infinity.
Overflow: This type of exceptionoccurswhentherearevery
large values in the result. These large values cannot be
represented correctly i.e. which returns ±infinity by default
Underflow: This type of exception occurs when there are
very small values in the result i.e. outside the normal range.
Inexact: This type of exception occurs whenevertheresult of
an arithmetic operation is not exact due to the restricted
exponent or precision range.
3. Results and Discussions:
The complete code is synthesis using Verilog,Simulateusing
Questa Sim Simulator which is an advance version of model
sim simulator and implementation is done using Vertex-7
FPGA. The FPGA that is used for the implementation of the
design is the Xilinx Vertex-7 (family), XC7VLX30 (Device),
FF324 (Package) FPGA device. The working
environment/tool for the design is the Xilinx ISE 12.4.1 is
used for FPGA design flow of Verilog code.
3.1. Simulation Result of floating point addition
It is calculated for the two input operands of 64 bits each. 15
clock cycles are required by floating point unit to complete
addition process. As frequency is 282MHz so one clock cycle
completes 3.54ns and 15 clock cycles completes in 3.54ns x
15 =53.10ns. Therefore the addition process completes in
53.10ns.
Similarly others operations subtraction, multiplication also
required 53.10ns
Figure 5: Simulation Result of Floating Point Addition
3.2. Synthesis Results of Proposed FPAU:
The Table below showing the Area & Speed Results for
floating point arithmetic unit implementedonvertex7FPGA
Logic Utilization Used Available
Number of Slice Registers 4762 437600
Number of Slice LUTs 6525 437600
Number of fully used LUT-FF pairs 3013 91200
Number of bonded IOBs 206 2680
Number of DSP48A1s 9 1680
Maximum Frequency 282 MHz
Delay 53.10ns
Table 2: Design Summary of floating point arithmetic
unit for vertex 7 FPGA
3.3. Timing Result of Proposed Floating Point Unit
Since addition requires 15 clock cycles and maximum
frequency 282MHz so one clock cycle completes 3.54ns and
15 clock cycles completes in 3.54nsx15=53.10ns.Therefore
the addition process completes in 53.10ns. Similarly
subtraction operation completes in 53.10ns, multiplication
operation completes in 53.10ns and division operation
completes in 240.72ns (68 clock cycles)
4. Conclusions and Future Work
Floating point arithmetic unit has been designed to perform
four arithmetic operations, addition, subtraction,
multiplication and division on floating point numbers. The
unit has been coded in VHDL. Code has been synthesised for
the Virtex-7 FPGA board using XILINX ISE and has been
implemented and verified on the software successfully.
Single stage implementation techniques are utilized in the
proposed floating point arithmetic unit. Due to single stage
design implementation thelongercombinational pathcanbe
compensated by shorter path delays in the subsequent logic
stages and maximum frequency of the design will increased
to 282 MHz. Iin the proposed floating point unit the complex
logic operations which consist of various multiple numbers
of stages are converted into single stage implementation.
The proposed floating point unit takes 15 clock cycles for
addition operation, 15 clock cyclesforsubtractionoperation,
15 clock cycles for multiplication operation and 68 clock
cycles for division operation. Proposed floating point unit
consumed 6525 Slice LUT and 9 DSP48A1s.
The designed arithmetic unit operates on 64-bit operands
and implemented on Virtex-7 FPGA it can also be
implemented on high performanceFPGAlikeVirtex-8FPGA.
When the floating point unit implements on higher
performance FPGA like Virtex-8 both the speed and area of
the design will improve but thesystem becomesmorecostly.
It can also be extended to have more mathematical
operations like trigonometric, logarithmic and exponential
functions. When such mathematical units are also
implemented on the floating point unit it will work for more
mathematical operations. We do not require other units to
perform such operations but by implementing such extra
mathematical units the floating point unit requires more
area and system becomes more complex.
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