pentium

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 An improvement over the architecture found in the 80486 microprocessor
 It is Compatible with 8086, 80286, 80386, 80486
 It Has all the features of 80486 plus some additional enhancements
Additional features
1. 64 bit data bus
 8 bytes of data information can be transferred to and from memory in a
single bus cycle
 Supports burst read and burst write back cycles
 Supports pipelining
2. Instruction cache
 8 KB of dedicated instruction cache
 Two Integer execution units, one Floating point execution unit
 Dual instruction pipeline
 256 lines between instruction cache and prefetch buffers; allows 32 bytes to
be transferred from cache to buffer
3. Data cache
 8 KB dedicate data cache gives data to execution units
 32 byte lines
4. Two parallel integer execution units
 Allows the execution of two instructions to be executed simultaneously in
a single processor clock
5. Floating point unit
 It includes
 Faster internal operations

2.  Local advanced programmable interrupt controller
 Speeds up upto 5 times for common operations including add, multiply and
load, than 80486
6. Branch Prediction Logic
 To reduce the time required for a branch caused by internal delays
 When a branch instruction is encountered, microprocessor begins prefetch
instruction at the branch address
7. Data Integrity and Error Detection
 Has significant error detection and data integrity capability
 Data parity checking is done on byte – byte basis
 Address parity checking and internal parity checking features are added
8. Dual Integer Processor
 Allows execution of two instructions per clock cycle
9. Functional redundancy check
 To provide maximum error detection of the processor and interface to the
processor
 A second processor ‘checker’ is used to execute in lock step with the
‘master’ processor
 It checks the master’s output and compares the value with the internal
computed values
 An error signal is generated in case of mismatch
10. Superscalar architecture
 Three execution units
 One execution unit executes floating point instructions
 The other two (U pipe and V pipe) execute integer instructions
 Parallel execution of several instructions – superscalar processor

3.  Describe features of Pentium pro-processor.
 The Pentium Pro processor has 36 address lines
 The Pentium Pro processor has an additional 256/512 KB L2 cache memory
on chip
 On chip L2 cache speeds processing and reduces the number of components
in a system
 The L2 cache is connected to BIU, BIU generates memory addresses and
control signals and passes or fetches data or instructions either to L1 data
cache or L1 instruction cache.
 The Instruction Fetch and Decode Unit (IFDU), contains three separate
instruction decoders that decode three instructions simultaneously
 It also include is Branch Prediction Logic
 It predicts if the branch will be taken or not for a conditional jump
instruction
 The instruction are then put into the instruction pool.
 The instruction pool is a memory accessible with its content
 The execute unit consists of three units namely two integer execution unit
and one floating point unit – two integer and one floating instruction can be
executed simultaneously
 Pentium Pro also has one jump execution unit (address generation unit)
 The instruction once executed is retired and the result is written into the
destination location by the retire unit

4.  It is the last stage of the instruction execution
 It is capable of removing up to three instructions per cycle
 The scheduling is performed by reservation station (RS) which can schedule
up to five events for execution and process four simultaneously
Special Pentium Pro-processor internal memory system
Features
Control register 4 (CR4)
 VME Virtual module extension
 Enables support for the virtual mode in protected mode If VME = 0,
virtual support is disabled
 PVI Protected mode virtual interrupt
 Enables support for the virtual interrupt flag in protected mode
 TDS Time Stamp disable
 Controls the RDTSC instruction
 DE Debugging Extension
 Enables I/O breakpoint debugging when set
 PSE Page size extension
 Enables 2 Mbyte memory pages when set in the pentium pro
processor

5.  PAE Page address extension
 Enables address lines A32 – A35
 MCE Machine check
 Enables machine checking interrupt
 PGE Page extension
 Controls new, larger 64G addressing mode whenever it is set along
with PAE and PSE

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 Additional features
1. Dual core processing
 Two independent processor cores in one physical package
 Run at same frequency
 Share up to 6 MB of L2 cache as well as up to 1333 MHz Front Side
Bus (FSB)
 Parallel computing
2. Wide dynamic execution
 Each core can compute up to four full instructions simultaneously
3. Smart memory access
 Newly designed prediction mechanisms
 New prefetch algorithms, keeps pipelining full
4. Advanced smart cache
 Shared L2 cache is dynamically allocated to each processor core
based on workload
5. Advanced digital
 Accelerate the execution of Streaming SIMD Extension (SSE)
instructions to significantly improve the performance of video,
audio, image processing, multimedia, engineering etc.

7. 6. Virtualization technology
 Allows one hardware platform to function as multiple ‘virtual’
platform
7. Trusted execution technology
 Protection against software based attack
 Protects the confidentiality and integrity of data solved or created on
the system
8. Intel 64 architecture
 Can access larger amount of memory
9. Execute disable bit
 Provides enhanced virus protection when deployed with a
supported operation system
 Allows memory to be marked as executable or non-executable
10.Designed thermal solution for boxed processor
 4 pin connector for fan speed control
 Minimizes the acoustic noise level generated from running the fan at
higher speeds