Directed Acyclic Graph Representation of basic blocks is the most important topic of compiler design.This will help for student studying in master degree in computer science.
Directed Acyclic Graph Representation of basic blocks is the most important topic of compiler design.This will help for student studying in master degree in computer science.
The purpose of types:
To define what the program should do.
e.g. read an array of integers and return a double
To guarantee that the program is meaningful.
that it does not add a string to an integer
that variables are declared before they are used
To document the programmer's intentions.
better than comments, which are not checked by the compiler
To optimize the use of hardware.
reserve the minimal amount of memory, but not more
use the most appropriate machine instructions.
The purpose of types:
To define what the program should do.
e.g. read an array of integers and return a double
To guarantee that the program is meaningful.
that it does not add a string to an integer
that variables are declared before they are used
To document the programmer's intentions.
better than comments, which are not checked by the compiler
To optimize the use of hardware.
reserve the minimal amount of memory, but not more
use the most appropriate machine instructions.
Introduction to combinational logic is here. We discuss analysis procedures and design procedures in this slide set. Several adders, multiplexers, encoder and decoder are discussed.
I am Frank Allen. I am a Computer Architecture Assignment Expert at architectureassignmenthelp.com. I hold a Master's in Computer Architecture from, Ontario Tech University, Canada. I have been helping students with their assignments for the past 10 years. I solve assignments related to Computer Architecture.
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Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Democratizing Fuzzing at Scale by Abhishek Aryaabh.arya
Presented at NUS: Fuzzing and Software Security Summer School 2024
This keynote talks about the democratization of fuzzing at scale, highlighting the collaboration between open source communities, academia, and industry to advance the field of fuzzing. It delves into the history of fuzzing, the development of scalable fuzzing platforms, and the empowerment of community-driven research. The talk will further discuss recent advancements leveraging AI/ML and offer insights into the future evolution of the fuzzing landscape.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Quality defects in TMT Bars, Possible causes and Potential Solutions.PrashantGoswami42
Maintaining high-quality standards in the production of TMT bars is crucial for ensuring structural integrity in construction. Addressing common defects through careful monitoring, standardized processes, and advanced technology can significantly improve the quality of TMT bars. Continuous training and adherence to quality control measures will also play a pivotal role in minimizing these defects.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
1. UNIT V
Code Optimization &
Code Generation
Mrs.D.Jena Catherine Bel,
Assistant Professor, CSE,
Velammal Engineering College
2. Position of a Code Generator in
the Compiler Model
2
Front-End
Code
Optimizer
Source
program
Symbol Table
Lexical error
Syntax error
Semantic error
Intermediate
code Code
Generator
Intermediate
code
Target
program
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
3. Code Generation
• Code produced by compiler must be correct
• Source to target program transformation is semantics preserving
• Code produced by compiler should be of high quality
• Effective use of target machine resources
• Heuristic techniques can generate good but suboptimal code,
because generating optimal code is undecidable
3
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
4. Target Program Code
• The back-end code generator of a compiler may generate
different forms of code, depending on the requirements:
• Absolute machine code (executable code)
• Relocatable machine code (object files for linker)
• Assembly language (facilitates debugging)
• Byte code forms for interpreters (e.g. JVM)
4
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
5. The Target Machine
• Implementing code generation requires
thorough understanding of the target machine
architecture and its instruction set
• Our (hypothetical) machine:
• Byte-addressable (word = 4 bytes)
• Has n general purpose registers R0, R1, …, Rn-1
• Two-address instructions of the form
op source, destination
5
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
6. The Target Machine: Op-codes
and Address Modes
• Op-codes (op), for example
MOV (move content of source to
destination)
ADD (add content of source to destination)
SUB (subtract content of source from dest.)
6
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
7. 7
Mode
For
m
Address
Added
Cost
Absolute M M 1
Register R R 0
Indexed c(R) c+contents(R) 1
Indirect
register
*R contents(R) 0
Indirect
indexed
*c(R
)
contents(c+contents
(R))
1
Literal #c N/A 1
Address modes
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
8. Instruction Costs
• Machine is a simple, non-super-scalar processor
with fixed instruction costs
• Realistic machines have deep pipelines, I-cache,
D-cache, etc.
• Define the cost of instruction
= 1 + cost(source-mode) + cost(destination-
mode)
8
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
9. Examples
9
Instruction Operation Cost
MOV R0,R1 Store content(R0) into register R1 1
MOV R0,M Store content(R0) into memory location M 2
MOV M,R0 Store content(M) into register R0 2
MOV 4(R0),M Store contents(4+contents(R0)) into M 3
MOV *4(R0),M Store contents(contents(4+contents(R0))) into M 3
MOV #1,R0 Store 1 into R0 2
ADD 4(R0),*12(R1) Add contents(4+contents(R0))
to contents(12+contents(R1)) 3
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
10. Instruction Selection
• Instruction selection is important to obtain
efficient code
• Suppose we translate three-address code
x:=y+z
to: MOV y,R0
ADD z,R0
MOV R0,x
10
a:=a+1 MOV a,R0
ADD #1,R0
MOV R0,a
ADD #1,a INC a
Cost = 6
Cost = 3 Cost = 2
Better Better
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
11. Instruction Selection: Utilizing
Addressing Modes
• Suppose we translate a:=b+c into
MOV b,R0
ADD c,R0
MOV R0,a
• Assuming addresses of a, b, and c are stored in
R0, R1, and R2
MOV *R1,*R0
ADD *R2,*R0
• Assuming R1 and R2 contain values of b and c
ADD R2,R1
MOV R1,a
11
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
12. Need for Global Machine-
Specific Code Optimizations
• Suppose we translate three-address code
x:=y+z
to: MOV y,R0
ADD z,R0
MOV R0,x
• Then, we translate
a:=b+c
d:=a+e
to: MOV a,R0
ADD b,R0
MOV R0,a
MOV a,R0
ADD e,R0
MOV R0,d
12
Redundant
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
13. Register Allocation and
Assignment
• Efficient utilization of the limited set of registers
is important to generate good code
• Registers are assigned by
• Register allocation to select the set of variables that
will reside in registers at a point in the code
• Register assignment to pick the specific register that a
variable will reside in
• Finding an optimal register assignment in general
is NP-complete
13
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
14. Example
14
t:=a+b
t:=t*c
t:=t/d
MOV a,R1
ADD b,R1
MUL c,R1
DIV d,R1
MOV R1,t
t:=a*b
t:=t+a
t:=t/d
MOV a,R0
MOV R0,R1
MUL b,R1
ADD R0,R1
DIV d,R1
MOV R1,t
{ R1=t } { R0=a, R1=t }
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
15. Choice of Evaluation Order
• When instructions are independent, their
evaluation order can be changed
15
t1:=a+b
t2:=c+d
t3:=e*t2
t4:=t1-t3
a+b-(c+d)*e
MOV a,R0
ADD b,R0
MOV R0,t1
MOV c,R1
ADD d,R1
MOV e,R0
MUL R1,R0
MOV t1,R1
SUB R0,R1
MOV R1,t4
t2:=c+d
t3:=e*t2
t1:=a+b
t4:=t1-t3
MOV c,R0
ADD d,R0
MOV e,R1
MUL R0,R1
MOV a,R0
ADD b,R0
SUB R1,R0
MOV R0,t4
reorder
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
16. Flow Graphs
• A flow graph is a graphical depiction of a sequence of
instructions with control flow edges
• A flow graph can be defined at the intermediate code level or
target code level
16
MOV 1,R0
MOV n,R1
JMP L2
L1: MUL 2,R0
SUB 1,R1
L2: JMPNZ R1,L1
MOV 0,R0
MOV n,R1
JMP L2
L1: MUL 2,R0
SUB 1,R1
L2: JMPNZ R1,L1
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
17. Basic Blocks
• A basic block is a sequence of consecutive instructions with
exactly one entry point and one exit point (with natural flow
or a branch instruction)
17
MOV 1,R0
MOV n,R1
JMP L2
MOV 1,R0
MOV n,R1
JMP L2
L1: MUL 2,R0
SUB 1,R1
L2: JMPNZ R1,L1
L1: MUL 2,R0
SUB 1,R1
L2: JMPNZ R1,L1
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
18. Basic Blocks and Control Flow
Graphs
• A control flow graph (CFG) is a directed graph with basic
blocks Bi as vertices and with edges BiBj iff Bj can be
executed immediately after Bi
18
MOV 1,R0
MOV n,R1
JMP L2
MOV 1,R0
MOV n,R1
JMP L2
L1: MUL 2,R0
SUB 1,R1
L2: JMPNZ R1,L1
L1: MUL 2,R0
SUB 1,R1
L2: JMPNZ R1,L1
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
19. Successor and Predecessor
Blocks
• Suppose the CFG has an edge B1B2
• Basic block B1 is a predecessor of B2
• Basic block B2 is a successor of B1
19
MOV 1,R0
MOV n,R1
JMP L2
L1: MUL 2,R0
SUB 1,R1
L2: JMPNZ R1,L1
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
20. Partition Algorithm for Basic
Blocks
20
Input: A sequence of three-address statements
Output: A list of basic blocks with each three-address statement
in exactly one block
1. Determine the set of leaders, the first statements of basic blocks
a) The first statement is the leader
b) Any statement that is the target of a goto is a leader
c) Any statement that immediately follows a goto is a leader
2. For each leader, its basic block consist of the leader and all
statements up to but not including the next leader or the end
of the program
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
21. Loops
• A loop is a collection of basic blocks, such that
• All blocks in the collection are strongly connected
• The collection has a unique entry, and the only way to reach a
block in the loop is through the entry
21
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
23. Equivalence of Basic Blocks
• Two basic blocks are (semantically) equivalent if they compute
the same set of expressions
23
b := 0
t1 := a + b
t2 := c * t1
a := t2
a := c * a
b := 0
a := c*a
b := 0
a := c*a
b := 0
Blocks are equivalent, assuming t1 and t2 are dead: no longer used (no longer live)
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
24. Transformations on Basic
Blocks
• A code-improving transformation is a code
optimization to improve speed or reduce code
size
• Global transformations are performed across
basic blocks
• Local transformations are only performed on
single basic blocks
• Transformations must be safe and preserve the
meaning of the code
• A local transformation is safe if the transformed basic
block is guaranteed to be equivalent to its original
form
24
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
25. Common-Subexpression
Elimination
• Remove redundant computations
25
a := b + c
b := a - d
c := b + c
d := a - d
a := b + c
b := a - d
c := b + c
d := b
t1 := b * c
t2 := a - t1
t3 := b * c
t4 := t2 + t3
t1 := b * c
t2 := a - t1
t4 := t2 + t1
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
26. Dead Code Elimination
• Remove unused statements
26
b := a + 1
a := b + c
…
b := a + 1
…
Assuming a is dead (not used)
b := x + y
…
if true goto L2
Remove unreachable code
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
27. Renaming Temporary
Variables
• Temporary variables that are dead at the end of a block can be
safely renamed
27
t1 := b + c
t2 := a - t1
t1 := t1 * d
d := t2 + t1
t1 := b + c
t2 := a - t1
t3 := t1 * d
d := t2 + t3
Normal-form block
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
28. Interchange of Statements
• Independent statements can be reordered
28
t1 := b + c
t2 := a - t1
t3 := t1 * d
d := t2 + t3
t1 := b + c
t3 := t1 * d
t2 := a - t1
d := t2 + t3
Note that normal-form blocks permit all
statement interchanges that are possible
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
29. Algebraic Transformations
• Change arithmetic operations to transform blocks to algebraic
equivalent forms
29
t1 := a - a
t2 := b + t1
t3 := 2 * t2
t1 := 0
t2 := b
t3 := t2 << 1
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
30. Next-Use
• Next-use information is needed for dead-code
elimination and register assignment
• Next-use is computed by a backward scan of a
basic block and performing the following actions
on statement
i: x := y op z
• Add liveness/next-use info on x, y, and z to statement i
• Set x to “not live” and “no next use”
• Set y and z to “live” and the next uses of y and z to i
30
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
31. Next-Use (Step 1)
31
i: a := b + c
j: t := a + b [ live(a) = true, live(b) = true, live(t) = true,
nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ]
Attach current live/next-use information
Because info is empty, assume variables are live
(Data flow analysis Ch.10 can provide accurate information)
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
32. Next-Use (Step 2)
32
i: a := b + c
j: t := a + b [ live(a) = true, live(b) = true, live(t) = true,
nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ]
live(a) = true nextuse(a) = j
live(b) = true nextuse(b) = j
live(t) = false nextuse(t) = none
Compute live/next-use information at j
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
33. Next-Use (Step 3)
33
i: a := b + c
j: t := a + b [ live(a) = true, live(b) = true, live(t) = true,
nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ]
Attach current live/next-use information to i
[ live(a) = true, live(b) = true, live(c) = false,
nextuse(a) = j, nextuse(b) = j, nextuse(c) = none ]
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
34. Next-Use (Step 4)
34
i: a := b + c
j: t := a + b
live(a) = false nextuse(a) = none
live(b) = true nextuse(b) = i
live(c) = true nextuse(c) = i
live(t) = false nextuse(t) = none
[ live(a) = false, live(b) = false, live(t) = false,
nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ]
[ live(a) = true, live(b) = true, live(c) = false,
nextuse(a) = j, nextuse(b) = j, nextuse(c) = none ]
Compute live/next-use information i
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
35. A Code Generator
• Generates target code for a sequence of three-
address statements using next-use information
• Uses new function getreg to assign registers to
variables
• Computed results are kept in registers as long as
possible, which means:
• Result is needed in another computation
• Register is kept up to a procedure call or end of block
• Checks if operands to three-address code are
available in registers
35
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
36. The Code Generation
Algorithm
• For each statement x := y op z
1. Set location L = getreg(y, z)
2. If y L then generate
MOV y’,L
where y’ denotes one of the locations where the
value of y is available (choose register if possible)
3. Generate
OP z’,L
where z’ is one of the locations of z;
Update register/address descriptor of x to include L
4. If y and/or z has no next use and is stored in
register, update register descriptors to remove y
and/or z
36
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
37. Register and Address
Descriptors
• A register descriptor keeps track of what is
currently stored in a register at a particular point
in the code, e.g. a local variable, argument,
global variable, etc.
MOV a,R0 “R0 contains a”
• An address descriptor keeps track of the location
where the current value of the name can be
found at run time, e.g. a register, stack location,
memory address, etc.
MOV a,R0
MOV R0,R1 “a in R0 and R1” 37
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
38. The getreg Algorithm
• To compute getreg(y,z)
1. If y is stored in a register R and R only holds the
value y, and y has no next use, then return R;
Update address descriptor: value y no longer in R
2. Else, return a new empty register if available
3. Else, find an occupied register R;
Store contents (register spill) by generating
MOV R,M
for every M in address descriptor of y;
Return register R
4. Return a memory location
38
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
39. Code Generation Example
39
Statements Code Generated
Register
Descriptor
Address
Descriptor
t := a - b
u := a - c
v := t + u
d := v + u
MOV a,R0
SUB b,R0
MOV a,R1
SUB c,R1
ADD R1,R0
ADD R1,R0
MOV R0,d
Registers empty
R0 contains t
R0 contains t
R1 contains u
R0 contains v
R1 contains u
R0 contains d
t in R0
t in R0
u in R1
u in R1
v in R0
d in R0
d in R0 and
memory
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
40. Peephole Optimization
• Examines a short sequence of target instructions
in a window (peephole) and replaces the
instructions by a faster and/or shorter sequence
when possible
• Applied to intermediate code or target code
• Typical optimizations:
• Redundant instruction elimination
• Flow-of-control optimizations
• Algebraic simplifications
• Use of machine idioms
40
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
41. Peephole Opt: Eliminating
Redundant Loads and Stores
• Consider
MOV R0,a
MOV a,R0
• The second instruction can be deleted, but only
if it is not labeled with a target label
• Peephole represents sequence of instructions with at
most one entry point
• The first instruction can also be deleted if
live(a)=false
41
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
42. Peephole Optimization:
Deleting Unreachable Code
• Unlabeled blocks can be removed
42
b := x + y
…
goto L2
b := x + y
…
if 0==0 goto L2
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
43. Peephole Optimization: Branch
Chaining
• Shorten chain of branches by modifying target labels
43
b := x + y
…
if a==0 goto L2
L2: goto L3
b := x + y
…
if a==0 goto L3
L2: goto L3
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC
45. Other Peephole Optimizations
• Reduction in strength: replace expensive
arithmetic operations with cheaper ones
• Utilize machine idioms
• Algebraic simplifications
45
…
a := x ^ 2
b := y / 8
…
a := x * x
b := y >> 3
…
a := a + 1
…
inc a
…
a := a + 0
b := b * 1
…
Mrs.D.Jena
Catherine
Bel,
AP/CSE,
VEC