This document compares electrical, optical, and plasmonic interconnects for on-chip communication based on delay and energy. Plasmonic interconnects can be used for local connections using metal structures that support surface plasmon polaritons for propagation. Optical interconnects are better suited for global connections due to their higher bandwidth compared to electrical interconnects. The document analyzes the delay and energy of different interconnect types and defines a critical length beyond which optical interconnects perform better than electrical interconnects.

1. Comparison of Electrical,
Optical and Plasmonic
On-Chip Interconnects
Based on Delay and
Energy Considerations
Presented by
Harish Peta – IMI2013002

2. Introduction
• Moore’s law is being sustained by scaling the device size.
• Because of scaling the delay, energy per bit and cross-talk among
wires are the prominent problems.
• In this respect, focus is on two alternative technology options that
can augment electrical interconnects on chip - Plasmonic and Optical
Interconnects.

3. Plasmons
• Plasma oscillations, also known as "Langmuir waves" (after Irving Langmuir), are
rapid oscillations of the electron density in conducting media such as plasmas or
metals.
• The quasiparticle resulting from the quantization of these oscillations is
the plasmon.
• A resonance condition is established when the frequency of the incident light
photons matches the natural frequency of plasma oscillations against the
restoring force of positive nuclei.

4. • Can facilitate information transport between nanoscale devices at optical
frequencies and bridge the gap between the world of nanoscale electronics and
microscale photonics.
• The extreme confinement of light can be useful as waveguides in interconnects.

5. Plasmonic Interconnects
• Plasmonic Interconnects can be designed by anyone of these
structures
• Metal cylinder in dielectric
• Metal-Insulator-Metal
• Insulator-Metal-Insulator
• Chain of metal nanoparticles
Optical microscopy image of a SiO2 substrate with an array
of Au stripes attached to a large launchpad generated by
electron beam lithography.

6. • Propagation length is not long enough to have long range surface plasmons for
global interconnect applications and hence can be used for local interconnects.
• The propagation length ranges from few microns (at smaller diameter and lower
wavelength) to tens of microns (at higher wavelength and larger diameters).
Propagation length through
various plasmonic waveguides
as a function of the free space
wavelength. The propagation
length is maximum at around
1.2μm where the loss through
silver is minimum.

7. Comparison of plasmonic
interconnects with electrical
interconnects
1. Delay Comparison:
• The resistance at small dimensions is affected by the scattering due to side-walls
and line width variation.
• The interconnect capacitance model including fringing effects and coupling
capacitance is taken. The RC delay of a delay-optimized RC interconnect is given
as per
• The plasmonic interconnect delay is given as
L  0.89 RC  0.89  K IK ox oL
2 1
Hx ox

1
WL S







8. Delay versus length of CMOS interconnect and plasmon interconnect. As the speed of plasmonic
interconnects is comparable to the speed of light, they can be orders of magnitude faster than CMOS
interconnects.

9. 2. Energy Comparison:
• The energy of CMOS interconnects is given as
• where C is the sum of the total interconnect capacitance and the load capacitance.
• For plasmon interconnects, shot noise limited transmission is considered.
• Due to loss on the plasmonic interconnect, minimum energy transmitted per bit
(assuming unity quantum efficiency) is given as
• where α= 1/Lprop
< m > is mean number of plasmons

10. Cross over length beyond which it is more energy efficient to communicate via conventional
electrical interconnects rather than via SP interconnects due to attenuation of SPs

11. Optical Interconnects
• Due to the limitation on propagation length, plasmonic interconnects can be used
only as short local interconnects.
• At the global interconnect level, optics emerges as a promising technology.
• Optical interconnects offer higher bandwidth compared to electrical
interconnects.
Block diagram of optical link. The optical link consists of a modulator driven by a
tapered chain of electrical drivers, the optical waveguide and a photo-detector
followed by a trans impedance amplifier

12. 1. Delay of optical interconnects
• The delay of an optical link topt is given as
• The design of a fast and cost efficient CMOS compatible electro-optical modulator is one of
the most challenging tasks.
• The performance of optical waveguides is primarily limited by the wavelength of the utilized
light and the choice of optical material.
• The limiting factor in the delay of photodetectors is the carrier transit time.
• The time delay due to global electrical interconnects is
L  0.89 RC  0.89  K IK ox oL
2 1
Hx ox

1
WL S







13. 2. Energy dissipation of optical interconnects
• Energy dissipation in optical interconnects consists of three components
• Energy dissipated to charge the modulator capacitance
• The energy needed at the photo-detector to generate the photocurrent proportional to the
incoming light
• The static power dissipation in the transimpedance amplifier

14. Comparison of Electrical and Optical
Interconnects by Critical Length
• The metrics of delay, bandwidth-density,
bandwidth-density/delay and energy per bit
are compared for electrical and optical
interconnects at global level.
• Critical length in this context is defined as the
length beyond which optical interconnects
offer superior performance compared to their
electrical counterparts
Critical length of optical interconnects as a
function of the width of electrical
interconnects at the 2016 technology node.

15. Summary
• Plasmonic interconnects are suitable at short local interconnect level while
optical interconnects are viable at the global interconnect level.
• Issues related to integration, cost and reliability need to be addressed.

16. References
[1] Shaloo Rakheja and Vachan Kumar, Georgia Institute of Technology,
“Comparison of Electrical, Optical and Plasmonic On-Chip Interconnects
Based on Delay and Energy Considerations”, 13th Int'l Symposium on
Quality Electronic Design, 978-1-4673-1036-9/12 ©2012 IEEE
[2] J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K.
Banerjee, K. Saraswat, A. Rahman, R. Reif, and J. D. Meindl,
“Interconnect limits on gigascale integration,” Proceedings of the IEEE, vol.
89, no. 3, March 2001.
[3] E. Ozbay, “Plasmonics: Merging photonics and electronics at
nanoscale dimensions,” Science, vol. 311, 2006.
[4] Plasmonics: the next chip-scale technology Rashid Zia, Jon A. Schuller,
Anu Chandran, and Mark L. Brongersma, Geballe Laboratory for
Advanced Materials, Stanford University.
[5] www.itrs.net