STM32 MCU Family

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An overview of STM32 MCU family and its key features

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STM32 MCU Family

  1. 1. STM32 MCU Family <ul><li>Source: STMicroelectronics </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This module provides information about the STM32 MCU family. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Provide an overview of STM32 MCU family. </li></ul></ul><ul><ul><li>Discuss the key features and applications of STM32 MCU. </li></ul></ul><ul><li>Contents </li></ul><ul><ul><li>17 pages </li></ul></ul><ul><li>Duration </li></ul><ul><ul><li>10 Minutes </li></ul></ul>
  3. 3. The World of STM32
  4. 4. Key Features <ul><li>ARM 32-bit Cortex™-M3 core with embedded Flash and SRAM </li></ul><ul><ul><li>Up to 512KB Flash memory </li></ul></ul><ul><ul><li>Up to 64KB SRAM </li></ul></ul><ul><li>Clock, reset and supply management </li></ul><ul><li>Multiple communication peripherals </li></ul><ul><ul><li>I 2 C, USART, SPI </li></ul></ul><ul><li>Sleep, Stop and Standby low power mode </li></ul><ul><li>Multiple 16-bit timer </li></ul><ul><li>Real-time clock </li></ul><ul><li>DMA controller </li></ul><ul><li>12-bit DAC </li></ul><ul><li>Easy development, fast time to market </li></ul>
  5. 5. Applications <ul><li>Industrial: </li></ul><ul><li>PLC </li></ul><ul><li>Inverters </li></ul><ul><li>Printers, scanners </li></ul><ul><li>Industrial networking </li></ul><ul><li>Building and security: </li></ul><ul><li>Alarm systems </li></ul><ul><li>Video intercom </li></ul><ul><li>HVAC </li></ul><ul><li>Low power: </li></ul><ul><li>Glucose meters </li></ul><ul><li>Power meters </li></ul><ul><li>Battery operated application </li></ul><ul><li>Appliances: </li></ul><ul><li>Motor drive </li></ul><ul><li>Application control </li></ul><ul><li>Consumer: </li></ul><ul><li>PC peripherals, gaming </li></ul><ul><li>Digital camera, GPS platforms </li></ul>
  6. 6. STM32 Product Lines
  7. 7. System Architecture
  8. 8. Power Control <ul><li>Power supplies </li></ul><ul><ul><li>2.0 to 3.6V operating voltage supply (V DD ) </li></ul></ul><ul><ul><li>The ADC has an independent power supply. </li></ul></ul><ul><ul><li>Battery backup domain </li></ul></ul><ul><ul><li>The voltage regulator is always enable after reset. </li></ul></ul><ul><li>Power supply supervisor </li></ul><ul><ul><li>Power on reset (POR)/Power down reset (PDR) </li></ul></ul><ul><ul><li>Programmable voltage detector (PVD) </li></ul></ul><ul><ul><li>Sleep/Stop/Standby low-power mode </li></ul></ul><ul><ul><li>Slowing down system clocks </li></ul></ul><ul><ul><li>Peripheral clock gating </li></ul></ul>
  9. 9. Backup Register (BKP) <ul><li>20-byte data registers (in access line) or 84-byte data registers (in performance line) </li></ul><ul><li>Status/control register for managing tamper detection with interrupt capability </li></ul><ul><li>Calibration register for storing the RTC calibration value </li></ul><ul><li>Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on TAMPER pin PC13 (when this pin is not used for tamper detection) </li></ul>
  10. 10. Reset and Clock Control (RCC) <ul><li>Reset </li></ul><ul><ul><li>System reset </li></ul></ul><ul><ul><li>Power reset </li></ul></ul><ul><ul><li>Low-power management reset </li></ul></ul><ul><li>Clock </li></ul><ul><ul><li>High speed internal (HIS) oscillator clock </li></ul></ul><ul><ul><li>High speed external (HSE) oscillator clock </li></ul></ul><ul><ul><li>PLL clock </li></ul></ul>
  11. 11. Real Timer Clock (RTC) <ul><li>Programmable prescaler: division factor up to 220 </li></ul><ul><li>32-bit programmable counter for long-term measurement </li></ul><ul><li>Two separate clocks: PCLK1 for the APB1 interface and RTC clock </li></ul><ul><li>The RTC clock source could be any of the following three </li></ul><ul><ul><li>HSE clock divided by 128 </li></ul></ul><ul><ul><li>LSE oscillator clock </li></ul></ul><ul><ul><li>LSI oscillator clock </li></ul></ul><ul><li>Two separate reset types </li></ul><ul><ul><li>The APB1 interface is reset by system reset </li></ul></ul><ul><ul><li>The RTC Core </li></ul></ul><ul><li>Three dedicated maskable interrupt lines </li></ul><ul><ul><li>Alarm interrupt, for generating a software programmable alarm interrupt. </li></ul></ul><ul><ul><li>Seconds interrupt, for generating a periodic interrupt signal with a programmable period length (up to 1 second). </li></ul></ul><ul><ul><li>Overflow interrupt, to detect when the internal programmable counter rolls over to zero. </li></ul></ul>
  12. 12. Watchdog (WDG) <ul><li>Independent watchdog (IWDG) </li></ul><ul><ul><li>Free-running downcounter </li></ul></ul><ul><ul><li>Clocked from an independent RC oscillator (can operate in Standby and Stop modes) </li></ul></ul><ul><ul><li>Reset (if watchdog activated) when the downcounter value of 0x000 is reached </li></ul></ul><ul><li>Window watchdog (WWDG) </li></ul><ul><ul><li>Programmable free-running downcounter </li></ul></ul><ul><ul><li>Conditional reset </li></ul></ul><ul><ul><ul><li>– Reset (if watchdog activated) when the downcounter value becomes less than 40h </li></ul></ul></ul><ul><ul><ul><li>– Reset (if watchdog activated) if the downcounter is reloaded outside the window </li></ul></ul></ul>
  13. 13. General Purpose I/Os (GPIOs) <ul><li>Two 32-bit configuration registers </li></ul><ul><li>Each I/O port bit is freely programmed in several mode </li></ul><ul><ul><li>Input floating </li></ul></ul><ul><ul><li>Input pull-up </li></ul></ul><ul><ul><li>Input-pull-down </li></ul></ul><ul><ul><li>Analog Input </li></ul></ul><ul><ul><li>Output open-drain </li></ul></ul><ul><ul><li>Output push-pull </li></ul></ul><ul><ul><li>Alternate function push-pull </li></ul></ul><ul><ul><li>Alternate function open-drain </li></ul></ul>
  14. 14. DMA Controller <ul><li>12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2 </li></ul><ul><li>Each of the 12 channels is connected to dedicated hardware DMA requests, software </li></ul><ul><li>trigger is also supported on each channel. </li></ul><ul><li>Priorities between requests from channels of one DMA are software programmable </li></ul><ul><li>Independent source and destination transfer size, emulating packing and unpacking </li></ul><ul><li>Support for circular buffer management </li></ul><ul><li>Memory-to-memory transfer </li></ul><ul><li>Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers </li></ul><ul><li>Access to Flash, SRAM, peripheral SRAM, APB1, APB2 and AHB peripherals as source and destination </li></ul>
  15. 15. ADC <ul><li>12-bit resolution </li></ul><ul><li>Interrupt generation at End of Conversion, End of Injected conversion and Analog Watchdog event </li></ul><ul><li>Single and continuous conversion modes </li></ul><ul><li>Scan mode for automatic conversion of channel 0 to channel ‘n’ </li></ul><ul><li>Self-calibration </li></ul><ul><li>Data alignment with in-built data coherency </li></ul><ul><li>Channel by channel programmable sampling time </li></ul><ul><li>External trigger option for both regular and injected conversion </li></ul><ul><li>ADC conversion time: </li></ul><ul><ul><li>Performance line devices: 1 μs at 56 MHz (1.17 μs at 72 MHz) </li></ul></ul><ul><ul><li>Access line devices: 1 μs at 28 MHz (1.55 μs at 36 MHz) </li></ul></ul><ul><li>DMA request generation during regular channel conversion </li></ul>
  16. 16. DAC <ul><li>Two DAC converters: one output channel each </li></ul><ul><li>8-bit or 12-bit monotonic output </li></ul><ul><li>Left or right data alignment in 12-bit mode </li></ul><ul><li>Synchronized update capability </li></ul><ul><li>Noise-wave generation </li></ul><ul><li>Triangular-wave generation </li></ul><ul><li>Dual DAC channel independent or simultaneous conversions </li></ul><ul><li>DMA capability for each channel </li></ul><ul><li>External triggers for conversion </li></ul>
  17. 17. Communication Peripherals <ul><li>Serial peripheral interface (SPI) </li></ul><ul><ul><li>8- or 16-bit transfer frame format selection </li></ul></ul><ul><ul><li>Master or slave operation </li></ul></ul><ul><ul><li>Multimaster mode capability </li></ul></ul><ul><li>Inter-integrated circuit interface (I 2 C) </li></ul><ul><ul><li>Parallel-bus/I 2 C protocol converter </li></ul></ul><ul><ul><li>Multimaster capability: the same interface can act as Master or Slave </li></ul></ul><ul><ul><li>Universal synchronous asynchronous receiver </li></ul></ul><ul><ul><li>Supports different communication speeds </li></ul></ul><ul><li>Transmitter (USART) </li></ul><ul><ul><li>Full duplex, asynchronous communications </li></ul></ul><ul><ul><li>NRZ standard format (Mark/Space) </li></ul></ul><ul><ul><li>Programmable data word length </li></ul></ul>
  18. 18. Additional Resource <ul><li>For ordering the STM32 products, please click the part list or </li></ul><ul><li>call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><li>www.st.com/stm32 </li></ul>Newark Farnell

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