ARM Architecture and Instruction set.pptx

Dr. Shireesh Kumar Rai
Thapar University, Patiala
Email: skumar.rai@thapar.edu
ARM Processors

ARM Architecture
• The ARM is a Reduced Instruction Set Computer
(RISC) system.
• It has a large array of uniform resistors.
• A load/store model of data-processing where
operations can only operate on registers and not
directly on memory.

• All data be loaded into registers before an
operation can be performed.
• The result can then be used for further processing
or stored back into memory.
• A small number of addressing modes with all
load/store addresses being determined from
registers and instruction field only.
• A uniform fixed length instruction (32 bit)

• Separate Arithmetic Logic Unit (ALU) and shifter
giving additional control over data processing to
maximize execution speed.
• Auto-increment and Auto-decrement addressing
modes to improve the operation of program loops.
• Conditional execution of instructions to reduce
pipeline and thus increase execution speed.

Processor modes
• The ARM supports the 7 processor modes.
• Mode changes can be made under software
control, or can be caused by external interrupt or
exception processing.
• Most application program used in user mode.

Processor Mode Description
User usr Normal program execution mode
FIQ fiq Fast interrupt for high speed data transfer
IRQ irq Used for general purpose interrupt handling
Supervisor svc A protected mode for the operating system
Abort abt Implements virtual memory and/or memory protection
Undefined und Supports software emulation of hardware coprocessors
System sys Runs privileged operating system tasks

Registers
• The ARM has a total of 37 registers.
• These comprise 30 general purpose registers, 6 status
registers and a program counter.
• Only fifteen of the general purpose registers are
available at any one time depending on the processor
mode.

 There are a standard set of eight general purpose
registers that are always available (r0 – r7) no matter
which mode the processor is in.
 These registers are truly general purpose, with no
special uses being placed on them by the processors’
architecture.
 A few registers (r8 – r12) are common to all processor
mode with the exception of the fiq mode.
 When the processor is in the fast interrupt mode these
registers are replaced with the different set of registers
(r8_fiq – r12_fiq)

 The general purpose register can be used to handle 8
bit bytes, 16 bit half words, or 32 bit words.
 When we use a 32 bit register in a byte instruction only
the least significant 8 bits are used.
 In a half word instruction only the least significant 16
bits are used.
 The remaining registers (r13 – r15) are special purpose
registers and have very specific roles.

 r13 is also known as the Stack pointer, while r14 is
known as the Link Register, and r15 is the program
counter.
 The “user” (usr) and “System” (sys) modes share the
same registers.
 There are also one or two status registers depending on
which mode the processor is in.
 Current processor status register (CPSR) holds
information about the current status of the processor
(including its current mode)

 In the exception modes there is an additional Saved
Processor Status register (SPSR) which holds
information on the processors state before the system
changed into this mode i.e. the processor status just
before an exception.

The stack pointer, SP or r13
 Register r13 is used as a stack pointer and is also
known as the SP register.
 Each exception mode has its own version of r13, which
points to a stack dedicated to that exception mode.
 The stack is typically used to store temporary values.

The link register, LR or r14
 Register r14 is also known as the Link register or LR
 It is used to hold the return address of a subroutine.
 When an execution occurs, the exception mode’s
version of r14 is set to the address after the instruction
which has just been completed.
 The SPSR is a copy of the CPSR just before the
exception occurred.

The Program Counter, PC or r15
 Register r15 holds the Program Counter known as the
PC.
 It is used to identify which instruction is to be
performed next.
 As the PC holds the address of the next instruction it is
often referred to as an instruction pointer.

Current Processor Status Register (CPSR)
 Current processor status register (CPSR) contains the
current status of the processor.
 This includes various conditional code flags Interrupt
Status Processor mode and other status and control
information.
 The exception modes also have a saved processor status
register (SPSR), that is used to preserve the value of
CPSR when the associated exception occurs.
 Because the User and System modes are not exception
modes, there is no SPSR available.

The processors’ status is split in to two distinct parts:
the User flags and the Systems Control flags.
The upper half word is accessible in User mode and
contains a set of flags which can be used to effect the
operation of a program.
Any bit not currently used is reserved for future use
and should be zero.
The I and F bits indicate if interrupts (I) or Fast
Interrupts (F) are allowed.

The system flags can only be altered when the processor is
in protected mode.
User mode programs can not alter the status register except
for the condition code flags.

Flags
The upper four bits of the status register contains a set of
four flags, collectively known at condition code.
The condition code flags are
Negative (N)
Zero (Z)
Carry (C)
Overflow (V)
The condition code can be used to control the flow of the
program execution.

Exceptions
Exceptions are generated by internal and
external sources to cause the processor to handle
an event, such as an externally generated
interrupt or an attempt to execute an defined
instruction.

 ARM supports seven types of exception, and provides
privileged processing modes for each type.
Exception processing modes
Exception Type Processor Mode
Reset Supervisor svc
Software Interrupt Supervisor svc
Undefined Instruction Undefined und
Prefetch Abort Abort abt
Data Abort Abort abt
Interrupt IRQ irq
Fast Interrupt FIQ fiq

When an exception occurs, some of the standard registers
are replaced with registers specific to the exception mode.
All exception modes have their own Stack Pointer (SP)
and Link (LR) registers.
The fast interrupt mode has more registers (r8_fiq –
r12_fiq) for fast interrupt processing.

The seven exceptions are
Reset when the reset pin is held low, this is normally when the
system is first turned on or when the reset button is pressed.
Software Interrupt is generally used to allow user mode
programs to call the operating system.
The user program executes a software interrupt (SWI)
instruction with a argument which identifies the function the
user wishes to perform.

Undefined Instruction is when an attempt is
made to perform an undefined instruction. This
normally happens when there is a logical error
in the program and the processor starts to
execute data rather than program code.

Prefetch Abort occurs when the
processor attempts to access memory
that does not exist or the processor has
executed the breakpoint (BKPT)
instruction.

Data Abort occurs when attempting to
access a word on a non – word aligned
boundary. The lower two bits of a memory
must be zero when accessing a word.

Interrupt occurs when an external device
asserts the IRQ (Interrupt) pin on the
processor. This can be used by external
device to request attention from the
processor.

Fast Interrupt occurs when an external device
asserts the FIQ (fast interrupt) pin. This is designed
to support data transfer and has sufficient private
registers to remove the need for register saving in
such applications. A fast interrupt can not be
interrupted.

When an exception occurs, the processor halts execution
after the current instruction.
The state of the processor is preserved in the Saved
Processor Status Register (SPSR) so that the original
program can be resumed when the exception routine has
completed.
The address of the instruction the processor was just about
to execute is placed into the Link register of the appropriate
processor mode.
The processor is now ready to begin execution of the
exception handling.

The exception handler are located a pre-defined
locations known as Exception vectors. It is the
responsibility of an operating system to provide
suitable exception handling.

Instruction Set
The ARM Instruction set can be divided into six broad classes of instruction
Data Movement
Arithmetic
Memory Access
Logical and bit manipulation
Flow Control
System Control/ Privileged

Condition code (cc) Mnemonic
Back

ARM instructions
Type of operation:
Arithmetic
Branch
Load and Store
Logical
Move

ADD Add
ADC Add with carry
SUB Subtract
SBC Subtract with carry
RSB Reverse subtract
RSC Reverse subtract with carry
MUL Multiply
MLA Multiply and accumulate
UMULL Multiply - unsigned long
UMLAL Multiply and accumulate - unsigned long
SMULL Multiply - signed long
SMLAL Multiply and accumulate - signed long
CMP Compare
CMN Compare negative
Arithmetic Instructions

Branch Instructions:
B Branch
BL Branch with link

Load and Store Instructions
LDR Load word
LDRB Load byte
LDRSB Load signed byte
LDRH Load half word
LDRSH Load signed half word
LDM Load multiple
LDM sp! Pop
STR Store word
STRB Store byte
STRH Store half word
STM Store multiple
STM sp! Push

AND AND
EOR Exclusive OR
ORR OR
BIC Bit clear
TST Test
TEQ Test equivalence
Logical Instructions:

Move Instructions
MOV Move
MVN Move and negate
SWP Swap
SWPB Swap byte
MRS Move program status register to register
MSR Move register to program status register

Arithmetic Instruction
Add
Syntax: ADD{cond}{S} Rd, Rn, Operand2
Elements inside curly brackets are optional.
Usage: Adds the value in Rn to Operand2 and places the sum in Rd.
Condition flags: If S is specified then all flags are updated according to the
result.
Examples:
ADD R7, R4, #99 ;adds 99 to the value in R4 and places the sum in R7
ADD R1, R2, R3 ;adds the value in R3 to the value in R2 and places the sum
in R1

Add with carry
Syntax: ADC{cond}{S} Rd, Rn, Operand2
Usage: Adds the value in Rn to Operand2 and adds another 1 if the carry
flag is set. The sum is placed in Rd.
Condition flags: If S is specified then all flags are updated according to
the result.
Examples:
ADC R7, R4, #99 ;adds 99 to the value in R4 and adds another 1 if the
carry flag is set. Places the sum in R7
ADC R1, R2, R3 ;adds the value in R3 to the value in R2 and adds 1 if
the carry flag is set. Places the sum in R1

Subtract
Syntax: SUB{cond}{S} Rd, Rn, Operand2
Usage: Subtracts Operand2 from the value in Rn and places the
difference in Rd.
the result.
Examples:
SUB R7, R4, #99 ;subtracts 99 from the value in R4 and places the
result in R7
SUB R1, R2, R3 ;subtracts the value in R3 from the value in R2 and
places the difference in R1.

Subtract with carry
Syntax: SBC{cond}{S} Rd, Rn, Operand2
Usage: Subtracts Operand2 from the value in Rn and subtracts another 1
if the carry flag is clear. Places the difference in Rd.
result.
Examples:
SBC R7, R4, #99;
SBC R1, R2, R3;

Reverse subtract
Syntax: RSB{cond}{S} Rd, Rn, Operand2
Usage: Subtracts the value in Rn from Operand2 and places the difference
in Rd.
result.
Examples:
RSB R7, R4, #99 ;subtracts the value in R4 from 99 and places the result in
R7
RSB R1, R2, R3 ;subtracts the value in R2 from the value in R3 and places
the difference in R1

Reverse subtract with carry
Syntax: RSC{cond}{S} Rd, Rn, Operand2
Usage: Subtracts the value in Rn from Operand2 and subtracts another
1 if the carry flag is clear. Places the difference in Rd.
the result.
Examples:
RSC R7, R4, #99
RSC R1, R2, R3

Multiply
Syntax: MUL{cond}{S} Rd, Rm, Rs
Usage: Multiples the values in registers Rm and Rs and places the least
significant 32 bits of the product in register Rd.
Condition flags: If S is specified then the N and Z flags are updated
according to the result, the V flag is not affected and the C flag is
unpredictable for the ARM7 and earlier processors.
Example:
MUL R5, R3, R9 ;multiply the values in R3 and R9 and places the result
in R5

Multiply and accumulate
Syntax: MLA{cond}{S} Rd, Rm, Rs, Rn
Usage: Adds the value in Rn to the product of the values in Rm and Rs and
places the least significant 32 bits of the result in register Rd.
according to the result, the V flag is not affected and the C flag is
unpredictable for the ARM7 and earlier processors.
Example:
MLA R5, R3, R9, R5 ;multiply the values in R3 and R9, add the product to
the value in R5 and places the result in R5

Multiply - unsigned long
Syntax: UMULL{cond}{S} RdLo, RdHi, Rm, Rs
Usage: Multiples the values (as unsigned integers) in registers Rm and
Rs and places the least significant 32 bits of the product in register RdLo
and the most significant 32 bits of the product in register RdHi.
according to the result and the V and C flags are unpredictable for the
ARM7 and earlier processors.
Example:
UMULL R6, R5, R3, R9 ;multiply the values in R3 and R9 and places the
result in R5 and R6

Multiply and accumulate - unsigned long
Syntax: UMLAL{cond}{S} RdLo, RdHi, Rm, Rs
Usage: Multiples the values (as unsigned integers) in registers Rm and
Rs and adds the 64 bit product to the unsigned 64 bit value in registers
RdLo (least significant 32 bits) and RdHi (most significant 32 bits).
Example:
UMLAL R6, R5, R3, R9 ;multiply the values in R3 and R9 and add the
product to the values in R5 and R6

Multiply - signed long
Syntax: SMULL{cond}{S} RdLo, RdHi, Rm, Rs
Usage: Multiples the values (as two's complement signed integers) in
registers Rm and Rs and places the least significant 32 bits of the
product in register RdLo and the most significant 32 bits of the product in
register RdHi.
Example:
SMULL R6, R5, R3, R9 ;multiply the values in R3 and R9 and places the
result in R5 and R6

Multiply and accumulate - signed long
Syntax: SMLAL{cond}{S} RdLo, RdHi, Rm, Rs
Usage: Multiples the values (as two's complement signed integers) in
registers Rm and Rs and adds the 64 bit product to the two's complement
signed 64 bit value in registers RdLo (least significant 32 bits) and RdHi
(most significant 32 bits).
according to the result and the V and C flags are unpredictable for the ARM7
and earlier processors.
Example:
SMLAL R6, R5, R3, R9 ;multiply the values in R3 and R9 and add the
product to the values in R5 and R6

Compare
Syntax: CMP{cond} Rn, Operand2
Usage: Subtracts Operand2 from the value in Rn and updates the flags
accordingly. The result is discarded.
Condition flags: All flags are updated according to the result.
Examples:
CMP R1, #9 ;set the flags as if 9 was subtracted from the value in R1.
CMP R6, R2 ;set the flags for the result of (R6 - R2) but discard the
result

Compare negative
Syntax: CMN{cond} Rn, Operand2
Usage: Add Operand2 to the value in Rn and updates the flags
accordingly. The result is discarded.
Condition flags: All flags are updated according to the result.
Examples:
CMN R1, #9 ;set the flags as if 9 was added to the value in R1.
CMN R6, R2 ;set the flags for the result of (R6 + R2) but discard the
result

Comparisons
 The only effect of the comparisons is to
 UPDATE THE CONDITION FLAGS.
Thus no need to set S bit.
 Operations are:
CMP operand1 - operand2, but result not written
CMN operand1 + operand2, but result not written

Branch
Syntax: B{cond} label
Usage: Reloads the program counter with the memory address given by
label. The label identifies the instruction to branch to in the assembly
language program.
Condition flags: Flags are not affected.
Examples:
BNE loop
B display

Branch with link
Syntax: BL{cond} label
Usage: Reloads the program counter with the memory address
given by label. The label identifies the instruction to branch to in
the assembly language program. The memory address of the
next instruction after the BL instruction is copied to register r14,
the link register.
Examples:
BLCS toobig
BL display

Load word
Syntax: LDR{cond} Rd, address mode
Usage: Loads register Rd with 4 bytes from a location in memory with
address determined by address mode. Ensure that the address is
divisible to 4.
Examples:
LDR r7, [r3] ;load r7 with the value in memory location with address
given by r3
LDR r1, [r2], #4 ;load r1 with the value in memory location with address
given by r2 then add 4 to r2

Load byte
Syntax: LDRB{cond} Rd, address mode
Usage: Loads the least significant byte of register Rd with 1
byte from a location in memory with address determined
by address mode. The top 24 bits of Rd are cleared.
Example:
LDRB r7, [r3] ;load r7 with the byte in memory location with
address given by r3 and clear the top 24 bits of r7

Load signed byte
Syntax: LDRSB{cond} Rd, address mode
Usage: Loads the least significant byte of register Rd with 1 byte
from a memory location with address determined by address
mode. The most significant bit of the loaded byte (the sign bit) is
extended across the top 24 bits of Rd.
Example:
LDRSB r7, [r3] ;load r7 with the byte in memory location with
address given by r3 and extend the sign bit to 32 bits

Load half word
Syntax: LDRH{cond} Rd, address mode
Usage: Loads the bottom 16 bits of register Rd with 2 bytes from a
location in memory with address determined by address mode.
The top 16 bits of Rd are cleared.
Example:
LDRH r7, [r3] ;load r7 with two bytes in memory location with
address given by r3 and clear the top 16 bits of r7

Load signed half word
Syntax: LDRSH{cond} Rd, address mode
Usage: Loads the bottom 16 bits of register Rd with 2 bytes
from a location in memory with address determined
by address mode. The most significant bit of the loaded
bytes (the sign bit) is extended across the top 16 bits of Rd.
Example:
LDRSH r7, [r3] ;load r7 with two bytes in memory location
with address given by r3 and extend the sign bit to 32 bits

Load multiple
Syntax: LDM{cond}mode Rn{!}, reglist
Usage: Loads the registers specified in reglist from a memory location
with address given by the base register, Rn. Ensure that the address is
divisible to 4. One of four modes must be specified. The base register,
Rn, is updated to the final address if there is an exclamation mark, !, after
Rn.
Example1:
LDMIA r7!, {r3-r5, r9, r11} ;load registers r3, r4, r5, r9 and r11 with values
starting from memory location with address given by r7. After each
transfer increment r7 by 4 and update r7 at the end of the instruction.
Example2

Pop
Syntax: LDM{cond}mode sp!, reglist
Usage: Loads the registers specified in reglist with values
from the stack. One of four modes must be specified; FD, FA,
ED or EA.
Example:
LDMFD sp!, {r3-r5, pc} ;load registers r3, r4, r5 and program
counter with values from the stack. The stack is 'full
descending'.

Write a program to find factorial of a number.
LDR R1, Value1
LDR R2, Value2
LOOP MUL R0, R1, R2
MOV R1, R0
SUB R2, R2, #0x01
CMP R2, #0x01
BNE LOOP
SWI &11
Programming Examples

Example: Find the larger of two numbers.
LDR R1, Value 1
LDR R2, Value 2
CMP R1, R2
BHI Done
MOV [R0], R2
SWI &11
Done MOV [R0], R1
SWI &11

Condition
code
Flags for
execution
Meaning
EQ Z set Equal
NE Z clear Not equal
CS or HS C set Higher or same (unsigned
>=)
CC or LO C clear Lower (unsigned <)
MI N set Negative
PL N clear Positive or zero
VS V set Overflow
VC V clear No overflow
HI C set and Z clear Higher (unsigned >)
LS C clear or Z set Lower or same (unsigned <=)
GE N and V the same Signed >=
LT N and V different Signed <
GT Z clear, and N = V Signed >
LE Z set and N  V Signed <=
AL Any Always
Almost all instructions can be conditionally executed.
The mnemonic for an instruction that is to be conditionally executed includes
one of the following condition codes:

One’s complement
LDR R1, value
MVN R1, R1
SWI &11

32 Bit Addition: Direct
LDR R1, value 1
LDR R2, value 2
ADD R1, R1, R2
SWI &11

32 Bit addition: Indirect
LDR R0, Value 1
LDR R1, [R0]
ADD R0, R0, #0x04
LDR R2, [R0]
ADD R1, R1, R2
SWI &11

64 bit addition
LDR R1, value 1
LDR R2, value 2
LDR R3, value 3
LDR R4, value 4
ADDS R5, R1, R3
ADCS R6, R2, R4
END

Load and store instruction in a loop
LDR R1, value 1
LDR R2, value 2
LDR R3, value 3
LOOP LDR R0, [R1]
STR R0, [R2]
ADD R1, R1, #0X04
ADD R2, R2, #0X04
SUB R3, R3, #0x01
BNE LOOP
SWI &11

Multiple register transfer instruction
LDR R9, value 1
LDR R10, value 2
LDMIA R9!, {R0-R3}
STMIA R10!, {R0-R3}
SWI &11

Example: Block Copy
 Copy a block of memory, which is an exact multiple of
12 words long from the location pointed to by r12 to
the location pointed to by r13. r14 points to the end of
block to be copied.
; r12 points to the start of the source data
; r14 points to the end of the source data
; r13 points to the start of the destination data
loop LDMIA r12!, {r0-r11} ; load 48 bytes
STMIA r13!, {r0-r11} ; and store them
CMP r12, r14 ; check for the end
BNE loop ; and loop until done
r13
r14
r12
IncreasingM
emory

Store word
Syntax: STR{cond} Rd, address mode
Usage: Stores the value in register Rd into 4 bytes of
memory with address determined by address mode.
Ensure that the address is divisible to 4.
Examples:
STR r7, [r3] ;store value in r7 into memory location with
address given by r3
STR r1, [r2], #4 ;store value in r1 into memory location
with address given by r2 then add 4 to r2

Store byte
Syntax: STRB{cond} Rd, address mode
Usage: Stores the least significant byte of register Rd into the
memory location with address determined by address mode.
Example:
STRB r7, [r3] ;store least significant byte of r7 into memory
location with address given by r3

Store half word
Syntax: STRH{cond} Rd, address mode
Usage: Stores the bottom 16 bits of register Rd into two
bytes of the memory with address determined
by address mode.
Example:
STRH r7, [r3] ;store least significant byte of r7 into
memory location with address given by r3

Store multiple
Syntax: STM{cond}mode Rn{!}, reglist
Usage: Stores the values in registers specified by reglist to memory
locations starting with address given by the base register, Rn. Ensure that
the address is divisible to 4. One of four modes must be specified. The base
register, Rn, is updated to the final address if there is an exclamation mark,
!, after Rn.
Example:
STMDA r7!, {r3-r5, r9, r11} ;stores values in registers r3, r4, r5, r9 and r11 to
memory locations starting from address given by r7. After each transfer
decrement r7 by 4 and update r7 at the end of the instruction.

Push
Syntax: STM{cond}mode sp!, reglist
Usage: Stores the values in registers specified by reglist to the stack.
One of four modes must be specified; FD, FA, ED or EA.
Example:
STMEA sp!, {r3-r5, lr} ;store values in registers r3, r4, r5 and value in link
register to the stack. The stack is 'empty ascending'.

Logical Instructions:
AND AND
EOR Exclusive OR
ORR OR
BIC Bit clear
TST Test
TEQ Test equivalence

AND
Syntax: AND{cond}{S} Rd, Rn, Operand2
Usage: Performs a bit by bit logical AND of Operand2 with the
value in Rn and places the result in Rd.
Condition flags: If S is specified then the N and Z flags are
updated according to the result, the C flag is updated
if Operand2 was calculated using a shift and the V flag is not
affected.
Examples:
AND r7, r4, #0xFF ;ANDs 0x000000FF with r4 and places the
result in r7
AND r1, r2, r3 ;ANDs r3 with r2 and places the result in r1

Exclusive OR
Syntax: EOR{cond}{S} Rd, Rn, Operand2
Usage: Performs a bit by bit exclusive OR of Operand2 with the value in Rn
and places the result in Rd.
Condition flags: If S is specified then the N and Z flags are updated according
to the result, the C flag is updated if Operand2 was calculated using a shift
and the V flag is not affected.
Examples:
EOR r7, r4, #0xFF ;Exclusive ORs 0x000000FF with r4 and places result in r7
EOR r1, r2, r3 ;Exclusive ORs r3 with r2 and places the result in r1

OR
Syntax: ORR{cond}{S} Rd, Rn, Operand2
Usage: Performs a bit by bit logical OR of Operand2 with the value in Rn
and places the result in Rd.
according to the result, the C flag is updated if Operand2 was calculated
using a shift and the V flag is not affected.
Examples:
ORR r7, r4, #0xFF ;ORs 0x000000FF with r4 and places the result in r7
ORR r1, r2, r3 ;ORs r3 with r2 and places the result in r1

Bit clear
Syntax: BIC{cond}{S} Rd, Rn, Operand2
Usage: Performs a logical AND of the bits in Rn with the
complement of the bits in Operand2 and places the result in
Rd. In effect a 1 in Operand2 will make a 1 in Rn into a 0 -
hence bit clear.
affected.
Examples:
BIC r7, r4, #0xFF ;clears the last 8 bits of r4 to 0 and places
the result in r7
BIC r1, r2, r3 ;clears 1's in r2 corresponding to 1's in r3 and
places result in r1

Test
Syntax: TST{cond} Rn, Operand2
Usage: Performs a bit by bit logical AND of Operand2 with
the value in Rn and updates the flags accordingly. The result
is discarded.
Condition flags: The N and Z flags are updated according to
the result, the C flag is updated if Operand2 was calculated
Examples:
TST r4, #0xFF ;ANDs 0x000000FF with r4 and sets the flags
accordingly
TST r2, r3 ;ANDs r3 with r2 and sets the flags accordingly

Test equivalence
Syntax: TEQ{cond} Rn, Operand2
Usage: Performs a bit by bit exclusive OR of Operand2 with the
value in Rn and updates the flags accordingly. The result is
discarded.
Condition flags: The N and Z flags are updated according to the
result, the C flag is updated if Operand2 was calculated using a
shift and the V flag is not affected.
Examples:
TEQ r4, #0xFF ;exclusive ORs 0x000000FF with r4 and sets the
flags
TEQ r2, r3 ;exclusive ORs r3 with r2 and sets the flags accordingly

Move
Syntax: MOV{cond}{S} Rd, Operand2
Usage: Copies the value of Operand2 into Rd.
affected.
Examples:
MOV r7, #0xFF ;copy 0x000000FF into register r7
MOV r7, r4 ;copy the value in register r4 into register r7

Move and negate
Syntax: MVN{cond}{S} Rd, Operand2
Usage: Takes the value of Operand2, performs a bitwise logical NOT
operation on the value and places the result into Rd.
according to the result, the C flag is updated if Operand2 was calculated
Examples:
MVN r7, #0xFF ;copy 0xFFFFFF00 into register r7
MVN r7, r4 ;invert the value in r4 and place the result into r7

Swap
Syntax: SWP{cond} Rd, Rm, [Rn]
Usage: Data from memory address given by value in Rn is loaded into
Rd. Data in register Rm is stored at memory location with address given
by value in Rn. Ensure that the memory address is divisible by 4.
Examples:
SWP r1, r1, [r9] ;swap the data in register r1 with the data held in memory
at address given by value in r9.
SWP r6, r8, [r2] ;load r6 with data from memory at address given by r2
and then store data in r8 at the same memory address.

Swap byte
Syntax: SWPB{cond} Rd, Rm, [Rn]
Usage: Byte from memory address given by value in Rn is loaded into
least significant byte of Rd and the top 24 bits of Rd are cleared. Least
significant byte in register Rm is stored at memory location with address
given by value in Rn.
Example:
SWPB r1, r1, [r9] ;swap least significant byte in register r1 with the byte
held in memory at address given by value in r9. Clear top 24 bits of r1.

Move program status register to register
Syntax: MRS{cond} Rd, psr
Usage: Moves the contents of the current program status register
(CPSR) or the saved program status register (SPSR) into register Rd.
Examples:
MRS r1, CPSR ;move the value in the CPSR into register r1
MRS r5, SPSR ;move the value in the SPSR into register r5

Move register to program status register
Syntax: MSR{cond} <psr>_<fields>, Rm
Usage: Moves the contents of register Rd into the current program status
register (CPSR) or the saved program status register (SPSR). One or more fields
must be specified; these are the control field, c, the extension field, x, the status
field, s and the flags field, f. The source register can be replaced by an
immediate value formed from 8 bits rotated by an even number of bits.
Condition flags: The current flags are updated if CPSR_f is specified.
Examples:
MSR CPSR_f, r1 ;update the flags using the value in register r1
MSR SPSR_c, #0x7A ;move the immediate value, #0x7A, into the control field of
the saved program status register

Examples
Format of CPSR or SPSR

A register shifted by an immediate value
LSL Logical shift left Shift in range 0 to 31
LSR Logical shift right Shift in range 1 to 32
ASR Arithmetic shift right Shift in range 1 to 32
ROR Rotate right Shift in range 1 to 31
RRX Extended rotate right
.
The value in the register is first shifted by a numeric constant before being
applied to the remainder of the instruction.
There are five different types of shift available.

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Addressing modes
Load and store instructions can use a number of
different addressing modes.
Zero offset
Pre-indexed offset
Post-indexed offset

Zero offset
Syntax: [Rn]
Data is loaded from or stored to a memory location with
address given by a register, Rn.
The register, Rn, containing the address is enclosed in
square brackets in the assembly language instruction.
For example:
LDR r7, [r3] ;load r7 with the value in memory location
with address given by r3

Pre-indexed offset
Syntax: [Rn, offset]{!}
address given by a value in a base register, Rn, added to
a second value, the 'offset'.
Both the base register, Rn, and the offset are enclosed in
square brackets in the assembly language instruction.
The base register, Rn, is updated by the value of the offset
only if an exclamation mark, !, is given after the square
brackets.

The offset value can be one of the following:
An immediate value in the range -4095 to +4095
A value in another register, Rm. Either positive or negative
offsets can be specified.
Syntax: [Rn, {-}Rm]{!}(For LDR, STR, LDRB and STRB only.)
A value in another register, Rm, shifted by an immediate value.
The immediate value is restricted to the same range as when
used to shift a second operand. Syntax: [Rn, {-}Rm, shift]{!}

Examples:
LDR r7, [r3, #4] ;load r7 with the value in memory location with
address given by 4 added to value in r3
LDR r7, [r3, #4]! ;load r7 with the value in memory location with
address given by 4 added to value in r3 and update r3
STR r5, [r2, -r7] ;store value in r5 at memory location with address
given by value in r7 subtracted from the value in r2
STR r5, [r2, r7, LSL #3] ;store value in r5 at memory location with
address given by value in r7 left shifted by three bits added from
the value in r2

Post-indexed offset
Syntax: [Rn], offset
Data is loaded from or stored to a memory location
with address given by a value in a base register, Rn.
Then the base register, Rn, is updated by the addition
of a second value, the 'offset'.
The base register, Rn, is enclosed in square brackets
in the assembly language instruction and the offset is
added on to the end of the instruction.

The offset value can be one of the following:
An immediate value in the range -4095 to +4095
A value in another register, Rm.
Either positive or negative offsets can be specified.
Syntax: [Rn], {-}Rm(For LDR, STR, LDRB and STRB only.)
A value in another register, Rm, shifted by an immediate
value.
The immediate value is restricted to the same range as
when used to shift a second operand.
Syntax: [Rn], {-}Rm, shift

Examples:
LDR r7, [r3], #4 ;load r7 with the value in memory location with
address given by r3 and then add 4 to the value in r3
STR r5, [r2,] -r7 ;store value in r5 at memory location with
address given by value in r2 and then subtract the value in r7 from
the value in r2
STR r5, [r2], r7, LSL #3 ;store value in r5 at memory location with
address given by value in r2 and then add the value in r7 left
shifted by three bits to the value in r2
back

Literals or program relative
address given by the program counter plus or minus an
immediate value, the 'offset'.
The offset must be in the range -4095 to +4095.
Using program relative addressing for load and store is
not simple and in general should be avoided.

However program relative addressing can be used to load a 32 bit constant,
known as a literal, into a register.
The addressing mode is replaced by an equals sign valued by the 32 bit
constant e.g. =0x9F683D41 in the assembly language instruction.
When the assembler encounters this instruction it produces two machines
code instructions, one is the actual value of the data and the other is a
program relative load.
It automatically calculates the offset from the program counter to the
memory address of the data to be loaded.
Example:
LDR r5, =0x9F683D41 ;load the value 0x9F683D41 into register r5

Second operand
Operand2 occurs in the syntax of a number of ARM instructions.
Any of the following can be used for Operand2
A numeric constant (known as an 'immediate value').
A register
A register shifted by an immediate value.
A register shifted by another register.

A numeric constant (known as an 'immediate value').
An immediate value is identified by a hash symbol, #.
The constant must correspond to an 8-bit pattern rotated by an even
number of bits within a 32-bit word.
Hence the following are all allowed:
ADD r2, r4, #255
MOV r6, #0xFF000000
SUB r7, r3, #0x3FC00
The following are not allowed:
ADD r2, r4, #257
MOV r6, #0xFF800000
SUB r7, r3, #0x1FE00

A register
Any register from r0 to r15.
Examples:
ADD r2, r4, r9
MOV r6, r0
SUB r7, r3, r14
Note that using the program counter, r15, can give
unexpected results.

Note that extended rotate does not use an immediate value
because a shift by one bit is assumed.
Example:
MOV r6, r0, LSL #5 ;logical shift left the value in r0 by 5 bits and
place it in r6
ADD r4, r7, r2, ASR #8 ;arithmetic shift right the value in r2 by 8
bits and add it to the value in r7. Place the sum in r4.
SUB r3, r9, r12, RRX ;extended rotate right the value in r12 by one
bit and subtract it from the value in r9. Place the difference in r3.

A register shifted by another register.
LSL Logical shift left
LSR Logical shift right
ASR Arithmetic shift right
ROR Rotate right
The value in the register is first shifted by a value in another register before
being applied to the remainder of the instruction.
Only the least significant byte is used as the shift value so that same shift
occurs if the value held by the register is 0x00000014 or 0x031A0014.
4 types of shift can be used.

Example:
MOV r6, r0, LSL r3 ;logical shift left the value in r0 by the value in
r3 and place it in r6
ADD r4, r7, r2, ASR r8 ;arithmetic shift right the value in r2 by the
value in r8 and add it to the value in r7. Place the sum in r4.
SUB r3, r9, r12, ROR r1 ;rotate right the value in r12 by the value
in r1 and subtract it from the value in r9. Place the difference in
r3.

Logical shift left (LSL)
The value in the register is shifted to the left by a specified
number, n, of bits and the right hand n bits are set to 0.
Example:
Execute instruction MOV r3, r2, LSL #2
Before r2 holds the value:
1000 1101 1000 1001 0011 0100 0010 0001
After r3 holds the value:
0011 0110 0010 0100 1101 0000 1000 0100

Logical shift right (LSR)
The value in the register is shifted to the right by a specified
number, n, of bits and the left hand n bits are set to 0.
Example:
Execute instruction MOV r3, r2, LSR #2
1000 1101 1000 1001 0011 0100 0010 0001
0010 0011 0110 0010 0100 1101 0000 1000

Arithmetic shift right (ASR)
The value in the register is shifted to the right by a specified number, n, of bits and the left hand
n bits are set to the value of the most significant bit (sign bit) before the shift.
This preserves the sign of a two's complement number.
Example:
Execute instruction MOV r3, r2, ASR #2
Before r2 holds the value: 1000 1101 1000 1001 0011 0100 0010 0001
After r3 holds the value: 1110 0011 0110 0010 0100 1101 0000 1000
or
0000 1101 1000 1001 0011 0100 0010 0001
0000 0011 0110 0010 0100 1101 0000 1000

Rotate right (ROR)
The value in the register is rotated to the right by a specified
number, n, of bits and the left hand n bits are set to the value
of the right hand n bit before the shift.
Example:
Execute instruction MOV r3, r2, ROR #2
1000 1101 1000 1001 0011 0100 0010 0001
0110 0011 0110 0010 0100 1101 0000 1000

Extended rotate (RRX)
The value in the register is rotated to the right by one bit and
the most significant bit is set to the value of the carry
flag before the shift.
Example:
Execute instruction MOV r3, r2, RRX
1000 1101 1000 1001 0011 0100 0010 0001
And the carry flag is set.
1100 0110 1100 0100 1001 1010 0001 0000

Register lists
 The register list is a list of registers contained in curly brackets.
 The registers should be listed in ascending order and separated by
commas.
 Registers in a range from Rm to Rn (including Rm and Rn) can be
specified using {Rm-Rn}.
 r15, the program counter, can be replaced by pc.
 r14, the link register, can be replaced by lr.
 r13, the stack pointer, can be replaced by sp.

Register lists
 Avoid including the base register in the register list.
 Do not include the stack pointer when using push or pop.
Examples:
{r0, r13, pc} ;Registers r0, r13 (stack pointer) and r15
(program counter).
{r2, r5-r8, sp} ;Registers r2, r5, r6, r7, r8 and r13 (stack
pointer).
back
back1

Modes for multiple load and store
There are four modes for LDM and STM; these are increment after (IA),
increment before (IB), decrement after (DA) and decrement before (DB).
IA: The base register is incremented by 4 after each transfer
IB: The base register is incremented by 4 before each transfer
DA: The base register is decremented by 4 after each transfer
DB: The base register is decremented by 4 before each transfer
back
back1

Modes for push and pop
 One of four type of stack must be used; these are full descending
(FD), empty descending (ED), full ascending (FA) and empty
ascending (EA).
 A 'full' stack means that the value held by the stack pointer is the
address of valid data at the top of the stack.
 An 'empty' stack means that the value held in the stack pointer is
the address of the empty memory location above the top of the
stack.
 A descending stack means that the stack pointer is decremented by
a push and incremented by a pop.
 An ascending stack means that the stack pointer is incremented by
a push and decremented by a pop.
back

Conditional Execution
MOVCS R0, R1
The instruction will move the value of the register R1 into the R0
register only when the carry flag has been set. R0 will remain unaffected
if the C flag was clear
 Greater and the Less conditions are for use with signed numbers.
Higher and Lower conditions are for use with unsigned numbers.
 These condition codes only really make sense after a comparison
(CMP) instruction

Most data-processing instructions can also update the condition codes
according to their result.
Placing an “S” after the mnemonic will cause the flags to be updated.
For example there are two versions of the MOV instruction:
MOV R0, #0 will move the value 0 into the register R0 without setting
the flags.
MOVS R0, #0 will do the same, move the value 0 into the register R0,
but it will also set the condition code flags accordingly,
the Zero flag will be set, the Negative flag will be reset
and the Carry and overflow flags will not be affected.

MOVS R0, R1
MOVEQS R0, R2
MOVEQ R0, R3
The first instruction will move R1 into R0 unconditionally, but it will
also set the N and Z flags accordingly.
Thus the second instruction is only executed if the Z flag is set, i.e., the
value of R1 was zero. If the value of R1 was not zero the instruction is
skipped.
If the second instruction is executed it will copy the value of R2 into R0
and it will also set the N and Z flags according to the value of R2.
Thus the third instruction is only executed if both R1 and R2 are both
zero.

Data Processing Operands: <op1>
 The majority of the instructions relate to data processing of some form.
 One of the operands to these instructions is routed through the Barrel Shifter.
 This means that the operand can be modified before it is used.
 This can be very useful when dealing with lists, tables and other
complex data structures.
 We denote instructions of this type as taking one of its arguments from
<op1>
 An <op1> argument may come from one of two sources, a constant value or
a register, and can be modified in five different ways.

Unmodified Value
MOV R0, #1234 Will move the immediate constant value 123410 into
the register R0
MOV R0, R1 Will move the value in the register R1 into the register R0.

Logical Shift Left
 This will take the value of a register and shift the value up, towards the most
significant bit, by n bits.
 The number of bits to shift is specified by either a constant value or another
register.
 The lower bits of the value are replaced with a zero.
 This is a simple way of performing a multiply by a power of 2 (×2n
).
MOV R0, R1, LSL #2 R0 will become the value of R1 shifted left by 2 bits.
The value of R1is not changed.
MOV R0, R1, LSL R2 R0 will become the value of R1 shifted left by the
number of bits specified in the R2 register.
R0 is the only register to change, both R1and R2 are not affected by this operation.
If the instruction is to set the status register, the carry flag (C) is the last bit that
was shifted out of the value.

Logical Shift Right
 Logical Shift Right is very similar to Logical Shift Left except it
will shift the value to the right towards the least significant bit, by
n bits.
 It will replace the upper bits with zeros, thus providing an efficient
unsigned divide by 2n
function (|÷ 2n|).
 The number of bits to shift may be specified by either a constant
value or another register.
MOV R0, R1, LSR #2 ;R0 will take on the value of R1 shifted to the
right by 2 bits.
The value of R1 is not changed.
MOV R0, R1, LSR R2 As before R0 will become the value of R1
shifted to the right by the number of bits
specified in the R2 register.
 R1 and R2 are not altered by this operation.
 If the instruction is to set the status register, the carry flag (C) is
the last bit to be shifted out of the value.

Arithmetic Shift Right
 The Arithmetic Shift Right is rather similar to the Logical Shift
Right, but rather than replacing the upper bits with a zero, it
maintains the value of the most significant bit.
 As the most significant bit is used to hold the sign, this means the
sign of the value is maintained, thus providing a signed divide by
2n
operation (÷2n).
MOV R0, R1, ASR #2 Register R0 will become the value of register R1
shifted to the right by 2 bits, with the sign
maintained.
MOV R0, R1, ASR R2 Register R0 will become the value of the
register R1 shifted to the right by the number of
bits specified by the R2 register.
R1 and R2 are not altered by this operation.

Rotate Right
 In the Rotate Right operation, the least significant bit is copied into the carry
(C) flag, while the value of the C flag is copied into the most significant bit
of the value.
 In this way none of the bits in the value are lost, but are simply moved from
the lower bits to the upper bits of the value.
MOV R0, R1, ROR #2 This will rotate the value of R1 by two bits. The most
significant bit of the resulting value will be the same as
the least significant bit of the original value.
 The second most significant bit will be the same as the Carry flag.
 In the S version the Carry flag will be set to the second least significant bit
of the original value.
 The value of R1 is not changed by this operation.
MOV R0, R1, ROR R2 Register R0 will become the value of the register R1
rotated to the right by the number of bits specified by the
R2 register. R1 and R2 are not altered by this operation.

Rotate Right Extended
 This is similar to a Rotate Right by one bit.
 The extended section of the fact that this function moves the value
of the Carry (C) flag into the most significant bit of the value, and
the least significant bit of the value into the Carry (C) flag.
 Thus it allows the Carry flag to be propagated though multi-word
values, thereby allowing values larger than 32-bits to be used in
calculations.
MOV R0, R1 RRX The register R0 become the same as the value
of the register R1 rotated though the carry
flag by one bit.
 The most significant bit of the value becomes the same as the
current Carry flag, while the Carry flag will be the same as the
least significant bit or R1.
 The value of R1 will not be changed.

Different Addressing Mode for Memory Access
Offset Addressing
 In offset addressing the memory address is formed by adding (or
subtracting) an offset to or from the value held in a base register.
LDR R0, [R1] Will load the register R0 with the 32-bit word at the memory
address held in the register R1.
 In this instruction there is no offset specified, so an offset of zero is
assumed.
 The value of R1 is not changed in this instruction.

LDR R0, [R1, #4] Will load the register R0 with the word at the
memory address calculated by adding the constant
value 4 to the memory address contained in the R1
register.
The register R1 is not changed by this instruction.

LDR R0, [R1, R2] Loads the register R0 with the value at the memory
address calculated by adding the value in the register
R1 to the value held in the register R2.
Both R1 and R2 are not altered by this operation.

LDR R0, [R1, R2, LSL #2] Will load the register R0 with the 32-bit value at the
memory address calculated by adding the value in the
R1 register to the value obtained by shifting the value
in R2 left by 2 bits.
Both registers, R1 and R2 are not affected by this operation.

Pre-Index Addressing
 In pre-index addressing the memory address is formed in the same way as
for offset addressing.
 The address is not only used to access memory, but the base register is also
modified to hold the new value.
 In the ARM system this is known as a write-back and is denoted by placing
a exclamation mark after at the end of the <op2> code.
 Pre-Index address can be particularly useful in a loop as it can be used to
automatically increment or decrement a counter or memory pointer.

LDR R0, [R1, #4]! Will load the register R0 with the word at the
memory address calculated by adding the constant
value 4 to the memory address contained in the R1
register. The new memory address is placed back
into the base register, register R1.

LDR R0, [R1, R2]! Loads the register R0 with the value at the memory address
calculated by adding the value in the register R1 to the value
held in the register R2.
The offset register, R2, is not altered by this operation, the register holding the base
address, R1, is modified to hold the new address.

LDR R0, [R1, R2, LSL #2]! First calculates the new address by adding the value
in the base address register, R1, to the value obtained
by shifting the value in the offset register, R2, left by
2 bits. It will then load the 32-bit at this address into
the destination register, R0.
 The new address is also written back into the base register, R1.
 The offset register, R2, will not be affected by this operation.

Post index addressing
 In post-index address the memory address is the base register value.
 As a side-effect, an offset is added to or subtracted from the base register
value and the result is written back to the base register.
 Post-index addressing uses the value of the base register without
modification. It then applies the modification to the address and writes the
new address back into the base register.
 This can be used to automatically increment or decrement a memory pointer
after it has been used, so it is pointing to the next location to be used.

LDR R0, [R1], #4 Will load the register R0 with the word at the memory address
contained in the base register, R1.
It will then calculate the new value of R1 by adding the constant value 4 to the
current value of R1.
LDR R0, [R1], R2 Loads the register R0 with the value at the memory address
held in the base register, R1.
 It will then calculate the new value for the base register by adding the value
in the offset register, R2, to the current value of the base register.
 The offset register, R2, is not altered by this operation.

LDR R0, [R1], R2, LSL #2 First loads the 32-bit value at the memory address
contained in the base register, R1, into the destination
register, R0.
 It will then calculate the new value for the base register by adding the
current value to the value obtained by shifting the value in the offset register,
R2, left by 2 bits.
 The offset register, R2, will not be affected by this operation.

Example
Pre-indexing with write back
 LDR R0, [R1, #4]!
• Before instruction execution
 R0 = 0x00000000, R1=0x00009000
 Mem32[0x00009000] = 0x01010101
 Mem32[0x00009004] = 0x02020202
• After instruction execution
 R0 = 0x02020202
 R1 = 0x00009004

Branch instructions
 All ARM processors support a branch instruction that
allows a conditional branch forwards or backwards up
to 32MB.
 As the PC is one of the general-purpose registers
(R15), a branch or jump can also be generated by
writing a value to R15.
 A subroutine call can be performed by a variant of the
standard branch instruction.

 As well as allowing a branch forward or backward up to
32MB, the Branch with Link (BL) instruction preserves
the address of the instruction after the branch (the return
address) in the LR (R14).

List of multiply instructions
MLA Multiply Accumulate
MUL Multiply
SMLAL Signed multiply accumulate long
SMULL Signed multiply long
UMLAL Unsigned multiply accumulate long
UMULL Unsigned multiply long

Multiply Instructions
ARM has two classes of Multiply instruction:
• normal, 32-bit result
• long, 64-bit result
All Multiply instructions take two register operands as the input to the multiplier.
The ARM processor does not directly support a multiply-by-constant instruction.

Normal multiply
There are two Multiply instructions that produce 32-bit results:
MUL Multiplies the values of two registers together, truncates the result to 32 bits,
and stores the result in a third register.
MLA Multiplies the values of two registers together, add the value of a third
register, truncates the result to 32 bits, and stores the result in a fourth register.
This can be used to perform multiply-accumulate operations.

Long multiply
There are four Multiply instructions that produce 64-bit results (long multiply).
Two of the variants multiply the values of two registers together and store the 64-
bit result in third and fourth registers.
There are signed SMULL and unsigned UMULL variants.
The signed variants produce a different result in the most significant 32 bits if
either or both of the source operands is negative.

The remaining two variants multiply the values of two registers together, add the
64-bit value from the third and fourth registers and store the 64-bit result back into
those registers (third and fourth).
There are signed SMLAL and unsigned UMLAL variants. These instructions
perform a long multiply and accumulate.
All four long multiply instructions can optionally set the N (Negative) and Z (Zero)
condition code flags.

Data Processing Instructions
 Most data-processing instructions take two source
operands, though Move and Move Not take only one.
 The compare and test instructions only update the
condition flags.
 Other data-processing instructions store a result to a
register and optionally update the condition flags as well.

 Of the two source operands, one is always a register.
 The other is called a shifter operand and is either an immediate
value or a register.
 If the second operand is a register value, it can have a shift applied
to it.
 CMP, CMN, TST and TEQ always update the condition code flags.
 The assembler automatically sets the S bit in the instruction for
them.
 The remaining instructions update the flags if an S is appended to
the instruction mnemonic (which sets the S bit in the instruction).

Data Processing Operands
There are 11 addressing modes used to calculate the <op1>
in an ARM data-processing instruction.
The general instruction syntax is:
opcode <cc> <S> Rd, Rn, <op1>

Write a program in ARM Assembly Language to load any
register with 32 bit data and perform following.
a) Shift left by 2 bit.
b) Shift right by number of bits stored in register R2.
c) Shift left 5 bits conditionally when ‘0’ flag is set.
d) Arithmetic shift by the value contained in register R2.

A) Shift left by 2 bits
LDR R1, Value
MOV R1, R1, LSL#0x02
SWI &11
Value DCD &00000005 ; DCD: Define constant
double
Result: R1 = 0x00000014

B) Shift right by number of bits stored in register R2.
LDR R1, Value 1
LDR R2, Value 2
MOV R1, R1, LSR R2
SWI &11
Value1 DCD &00000005
Value2 DCD &00000003
Result: R1 = 0x00000000

C) Shift left 5 bits conditionally when ‘0’ flag is set.
LDR R1, Value 1
MOV R2, #0xFFFFFFFF
ADDS R2, R2, #0x01
MOVCS R1, R1, LSL# 0 x05 or MOVEQS R1, R1, LSL# 0x05
SWI &11
Value 1 DCD &00000005
Result: R1 = 0x000000A0

D) Arithmetic shift by value contained in
register R2
LDR R1, value 1
LDR R2, value 2
MOV R1, R1, ASR R2
SWI &11
value 1 DCD &00000005
Value 2 DCD &00000002
Result: R1 = 0x00000001

Write a program in ARM assembly language
to add two 32 bit numbers using
A) Direct method
B) Indirect method
C) Using Barrel shifter

A) Direct Method
LDR R1, value 1
LDR R2, value 2
ADD R1, R1, R2
SWI &11
value 1 DCD &10000100
value 2 DCD &00000002
Result: 0x10000102

B) Indirect Method
LDR R2, value 1
LDR R4, value 2
LDR R1, [R2]
LDR R3, [R4]
ADD R0, R1, R3
SWI &11
value 1 DCD &100000100
value 2 DCD &00000002

Using Barrel Shifter
LDR R2, value 1
LDR R4, value 2
LDR R1, [R2]
LDR R3, [R4]
ADD R0, R1, R3, LSL#0x02
SWI &11

Conditional Codes
The property of conditional execution is common to all
ARM instructions.
NV Never

EOR: Logical exclusive OR
Example

TEQ: Test Equivalence
The TEQ instruction performs the EOR operation on its <lhs>
and <rhs> operands. The result is not stored anywhere, but the
result flags are set according to the result.

MVN : Move value
The MOV instruction transfers the logical NOT of its
<rhs> operand to the register specified by <dest>.
Inverting the <rhs> before transfer enables negative
immediate operands to be loaded.
There is no <lhs> specified in the instruction.
MVN <dest>,<rhs>

In general, -n = NOT (n-1). This means that to load a
negative number, you subtract one from its positive value
and use that in the MVN.
For example, to load the number -128 you would do a
MVN of 127.
Examples:
MVNS R0, R0 ;Invert all bits of R0, setting flags MVN

Arithmetic Instruction
ADD Addition
Examples:
ADD R0,R0,#1 ;Increment R0
ADD R0,R0,R0,LSL#2 ;Multiple R0 by 5
ADDS R2,R2,R7 ;Add result; check for overflow

ADC Addition with carry
ADD: <dest> = <lhs> + <rhs>
ADC : <dest> = <lhs> + <rhs> + <carry>
Example:
;Add the 64-bit number in R2,R3 to that in R0,R1
ADDS R0,R0,R2 ;Add the lower words, getting carry
ADC R1,R1,R3 ;Add upper words, using carry SUB Subtract

Subtraction: SUB
This instruction subtracts the <rhs> operand from the
<lhs> operand, storing the result in <dest>.
Examples:
SUB R0,R0,#1 ;Decrement R0
SUB R0,R0,R0,ASR#2 ;Multiply R0 by 3/4 (R0=R0-
R0/4)

SBC: Subtract with carry
<dest> = <lhs> - <rhs> - NOT <carry>
*Notice that the carry is inverted because the C flag is cleared
by a subtract that needed a borrow and set by one that didn't.
Example:
;Subtract the 64-bit number in R2,R3 from that in R0,R1
SUBS R0,R0,R2 ;Sub the lower words, getting borrow
SBC R1,R1,R3 ;Sub upper words, using borrow

RSC: Reverse subtract with carry
CMP: Compare

Compare Negative
The CMN instruction compares two numbers, but
negates the right hand side before performing the
comparison.
CMN R0,#1 ;Compare R0 with -1

Load and store multiple registers in ARM
Instructions are available in ARM to load and store multiple
registers.
LDM : Load Multiple Registers
STM: Store Multiple Registers
PUSH: Store multiple registers onto the stack and update the
stack pointer.
POP: Load multiple registers off the stack, and update the stack
pointer

In LDM and STM instructions:
The list of registers loaded or stored can include:
• In ARM instructions, any or all of R0-R12, SP, LR, and PC.
The address can be:
Incremented after each transfer.
Incremented before each transfer (ARM instructions only).
Decremented after each transfer (ARM instructions only).

The base register can be either:
• Updated to point to the next block of data in memory.
• Left as it was before the instruction.
When the base register is updated to point to the next block
in memory, this is called writeback, that is, the adjusted
address is written back to the base register.

• In PUSH and POP instructions:
The stack pointer (SP) is the base register, and is
always updated.
• The address is incremented after each transfer
in POP instructions.
and decremented before each transfer
in PUSH instructions.

The list of registers loaded or stored in stack can
include:
any or all of R0-R12, SP, LR, and PC in ARM
instructions.

Block copy without LDM and STM
LDR R0, =src
LDR R1, =dst
MOV R2, #20
word copy
LDR R3, [R0], #4
STR R1, [R3], #4
SUBS R2, R2, #1
BNE word copy
SWI &11
src DCD 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4
dst DCD 0, 0, 0, 0, 0, 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0,0 ,0 ,0 ,0

Addressing Modes of ARM
1. Data Processing Operands
There are 11 addressing modes used to calculate the <op1 > in
an ARM data-processing instruction.

2. Memory Access
There are nine addressing modes used to calculate the
address for a Load and Store Word or Unsigned Byte
instruction.

One’s complement
LDR R1, value
MVN R1, R1
SWI &11

16 Bit Addition: Direct
LDR R1, value 1
LDR R2, value 2
ADD R1, R1, R2
SWI &11

16 Bit addition: Indirect
LDR R0, Value 1
LDR R1, [R0]
ADD R0, R0, #0x04
LDR R2, [R0]
ADD R1, R1, R2
SWI &11

Find the larger of two numbers.
LDR R1, Value 1
LDR R2, Value 2
CMP R1, R2
BHI Done
MOV [R0], R2
SWI &11
Done MOV [R0], R1
SWI &11

64 bit addition
LDR R1, value 1
LDR R2, value 2
LDR R3, value 2
LDR R4, value 4
ADDS R5, R1, R3
ADC R6, R2, R4
SWI &11

Write a program in ARM assembly language to copy consecutive word
from source to destination in memory using
A)Multiple register transfer instruction
B) Load and store instruction in a loop

Load and store instruction in a loop
LDR R1, value 1
LDR R2, value 2
LDR R3, value 3
Loop
LDR R0, [R1]
STR R0, [R2]
ADD R1, R1, #0X04
ADD R2, R2, #0X04
SUB R3, R3, #0x01
bne loop
SWI &11

write a program for multiplication of
numbers by repetitive addition.

Alternate program
LDR R1, Value 1
LDR R2, Value 2
LOOP
ADD R3, R2,R2
SUBS R1, R1, #0x01
BNE LOOP

Write a program for division of
numbers by repetitive subtraction.

Write a program to find factorial of a
number.

Write a program to verify how many bytes are present in
a given set which resembles the value 0xAC.
LDR R0, Value
MOV R3, # 0x08
MOV R2, # 0x00
LOOP LDRB R1, [R0], #1
CMP R1, #0xAC
ADDEQ R2, R2, #0x01
SUBS R3, R3, #0x01
BNE LOOP

Write a program in ARM assembly language to count the
number of 1’s and 0’s in a given word and verify the
result.
MOV R1,#0x03
MOV R2, #32
MOV R3, #0x00
MOV R4, #0x00
NEXT MOVS R1, R1, RRX
ADDCC R3,R3,#0x01
ADDCS R4, R4, #0x01
SUB R2, R2, #0x01
BNE NEXT

Write a program in ARM assembly language to perform
multiplication of numbers by repetitive addition.
LDR R1, Value1
LDR R2, Value2
LOOP ADD R3, R2, R2
SUBS R1, R1, #0x01
BNE LOOP

Write a program in ARM assembly language to copy
consecutive word from source to destination in memory using
A) Multiple register transfer instruction
B) Load and store instruction in a loop
LDR R9! Value1
LDR R10! Value2
LDMIA R9! {R0-R3}
STMIA R10! {R0-R3}
SWI &11

ARM Architecture and Instruction set.pptx

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