Introduction to emi hf feb_16_10am

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Introduction to emi hf feb_16_10am

  1. 1. Introduction to EMI/EMC Challenges and Their Solution Dr. Hany Fahmy HSD Application Expert Agilent Technologies Davy Pissort, K.U. Leuven Charles Jackson, Nvidia Charlie Shu, Nvidia Chen Wang, Nvidia Amolak Badesha, Avago Copyright © 2012 Agilent Technologies
  2. 2. Current Solution Put on a bandaid to stop the Bleeding (radiation..) •Not optimal •Does not always work •Costly Copper band-aid R4N Suppressor band-aid Copyright © 2012 Agilent Technologies
  3. 3. Complexity of EMI problem I/Os can inject Common-mode Noise Or Power-pins inject Noise into PDN Badly routed traces generate EMI High-speed connectors and cables amplify the EMI problems MINIMIZE I C, PKG , AND P C B E M I TO REDUCE OVERALL S YSTEM E M I Connectors High-speed PCB High-speed IC * From EM-Scan Measurement of GPU Board Copyright © 2012 Agilent Technologies
  4. 4. Mechanism of Noise Propagation (2) Radiation Noise Noise Source Noise Source (1) Conductive Noise Equipment or device exposed to noise (3) Conductive Noise Conductive Noise Noise Source Equipment or device exposed to noise Equipment or device exposed to noise Copyright © 2012 Agilent Technologies
  5. 5. Different types of Emission Trace-Emission I/O-Buffers Injecting Signal Power-Pins Injecting Noise GND Return-currents & Slots Common-Mode noise travelling Copyright through Connectors© 2012 Agilent Technologies
  6. 6. Introducing the concept of “Virtual-EMI Lab” O PTIMIZE FOR E M I DEVELOP EMI G UIDELINES VAL I D AT I O N W I T H M EASUREMENTS *Full-wave EM Simulation, What-if Analysis, Root-cause debugging **Measurements to Isolate the problem and Correlate with Simulation Copyright © 2012 Agilent Technologies
  7. 7. Radiated-emission on packages due to return-path-discontinuity Copyright © 2012 Agilent Technologies
  8. 8. DDR3 Package Modeling using MOM DC to 20GHz Data- (DQ-) nets major referencing to GND Copyright © 2012 Agilent Technologies
  9. 9. Routing of DQ signals from Die-Bumps-Top to Layer-3 running as Symmetric-SL sandwiched between GND on Layers 2 & 4 DQ signals on Layer-3 as Symmetric-SL DQ signals @ Die-Bumps Copyright © 2012 Agilent Technologies
  10. 10. Moving from Layer-3 to Layer-6 through SignalPTH to pickup the Balls DQ signals on Layer-6 routed between GND on layers 5 DQ signals on Layer-3 Copyright © 2012 Agilent Technologies
  11. 11. Impact of GND-PTH stitching: Proximity & # Original-Package: Cost-Reduced-Package: With 15-GND-PTH with 3-GND-PTH Copyright © 2012 Agilent Technologies
  12. 12. Comparison of Return-current on GND-L4 Original-Package: Cost-Reduced-Package: With 15-GND-PTH With 3-GND-PTH Larger NEXT by 10dB Copyright © 2012 Agilent Technologies
  13. 13. Comparison of eye-diagram @ 1.33GBps Original-Package: Cost-Reduced-Package: With 15-GND-PTH With 3-GND-PTH DQ 40ps loss of margin +95ps worst Setup-Margin DQS DQ +55ps worst Setup-Margin DQS Copyright © 2012 Agilent Technologies
  14. 14. Do Dispersion of GND-Current leads to MoreRadiated Emission? (Movie) Copyright © 2012 Agilent Technologies
  15. 15. PKG-Antenna-Parameters Comparison of 15-GND-PTH compared to 3-GND-PTH Antenna-Gain -19dB  -11dB (+8dB) Radiated-Power 40-uWatts  220-uWatts (6x) Maximum Intensity: 5u-watts/Steradian  40uwatts/Steradian (8X) Angle of U-max: 160-degrees vs. 140-degrees Copyright © 2012 Agilent Technologies
  16. 16. Trade-off Low-cost & Performance Reducing # of GND-Stitches  Medium-2-low-risk for 1.33GB/s operation with +55ps worst-case Setup-margin but with +8dB Antenna-Gain Most probably we need to Turn-ON Spread spectrum. What is the cost of PLL vs. Reduction of GND-Stitch? Copyright © 2012 Agilent Technologies
  17. 17. Trace Emission on PCBs due to costreduction Low-Layer count PCB CASE:1 Memory emission from MA/CMD lanes Copyright © 2012 Agilent Technologies
  18. 18. 4-layer PCB with Memory Emission Problem Problem: Investigate Emission problem at 1.25 times the memory clock frequency (1.623 GHz) Notes: Address/Command Nets are routed on bottom-layer Referencing power plane (due to lack of real-estate) Copyright © 2012 Agilent Technologies
  19. 19. EMI Simulation Methodology Step-1: Simulate and Visualize Current-density plot* Method-of-Moments (Momentum) Simulations showing current-density plots and hot-spot regions on the PCB Emscan Measurements *Using Agilent Momentum Field Solver Copyright © 2012 Agilent Technologies
  20. 20. EMI Simulation Methodology, Cont’ Step-2: Isolate Problem Observe hot-spot area closely, and identify root-cause Root-cause: There is small λ/8 power-plane patch that is radiating like patch-antenna Use the Momentum-uwave EM-engine with Antenna-Gain parameter to measure the merit of the PCB as non-intended antenna Develop EMI guidelines along with SI/PI Guidelines using Antenna-Gain Parameter to compare Layout guidelines Copyright © 2012 Agilent Technologies
  21. 21. What is the remedy? Instead of REF MA/CMD to a VddQ Patch on Bottom layer continue routing on Bottom Layer 3m Chamber at least 16dB Improvement Copyright © 2012 Agilent Technologies
  22. 22. Trace Emission on PCBs due to costreduction Low-Layer count PCB CASE:2 TMDS Emissions Copyright © 2012 Agilent Technologies
  23. 23. Problem Statement TMDS Emission @ 770MHz on 4-layer PCB & Coupling to Neighbor Ethernet-Card Copyright © 2012 Agilent Technologies
  24. 24. Which one is better Copper band-aid R4N Suppressor band-aid Copyright © 2012 Agilent Technologies
  25. 25. Copyright © 2012 Agilent Technologies
  26. 26. Copyright © 2012 Agilent Technologies
  27. 27. Is it E-coupling or H-coupling? With Metallic Shield *Lab data confirms simulation results Solution: Simulation shows that suppression material is improving EMI emission, whereas, metallic shied is making it worse Choose Suppression material over metallic shied -> Improve both cost and performance  Copyright © 2012 Agilent Technologies
  28. 28. Near-field scan results R4N Suppressor band-aid Emscan measurements Copyright © 2012 Agilent Technologies
  29. 29. Copyright © 2012 Agilent Technologies
  30. 30. Copyright © 2012 Agilent Technologies
  31. 31. What is the Remedy? Sometimes it is cheaper to dampen the receiver not Emitter because adding R4N suppression materials is more cost than using RJ45 shielded connector on the Ethernet-card. Selected to change RJ45 Connector on Ethernet-card to shielded one to suppress the receiver Copyright © 2012 Agilent Technologies
  32. 32. PCB Edge Emission due to Power delivery Noise Copyright © 2012 Agilent Technologies
  33. 33. Simulation Challenges in EMI •System level (source, coupling path, unintentional antenna •Full wave simulation is often needed •Time and memory consuming Copyright © 2012 Agilent Technologies
  34. 34. Combining Measured Icc(t) with FDTD simulations to study the critical on-board-decaps under the GPU Power Delivery Network Current Probe @ VddQ pins Drivers Channel Receivers •SSO current is obtained by a combined simulation of the power delivery network model and the memory IO channel model Copyright © 2012 Agilent Technologies
  35. 35. Measured Dynamic-current profile Icc(t) fft ifft steady-state frequencies •Time-domain noise pattern directly imported into FDTD solver Copyright © 2012 Agilent Technologies
  36. 36. Importing PCB layout of the Memory Channel Stackup 8 cm Signal Ground Signal VDD Ground VDD 11 cm board thickness: 1.57mm Copyright © 2012 Agilent Technologies
  37. 37. SSO Noise Source on Top Layer Noise sources IC Copyright © 2012 Agilent Technologies
  38. 38. Decaps on Bottom Layer decaps Copyright © 2012 Agilent Technologies
  39. 39. Far-Field Radiation at 0.5 GHz With Decaps at 1.0 GHz Without Decaps With Decaps Without Decaps Reduction of 3-4 dB Copyright © 2012 Agilent Technologies
  40. 40. Current Density At 0.5 GHz Without Decaps At 0.5 GHz With Decaps Copyright © 2012 Agilent Technologies
  41. 41. What is the benefit of PCB decaps? New method to optimize the PCB decaps: 1. Measure or simulate the Dynamic-current profile Icc(t) @ the VddQ-pins with maximum activity on the memory-channel 2. Import the Icc(t) into FDTD (wide-band-phenomena) 3. Study the critical PCB decaps to mitigate the SSO noise emission Copyright © 2012 Agilent Technologies
  42. 42. Connector/Cable Emission Copyright © 2012 Agilent Technologies
  43. 43. Board +Connector +Mate Copyright © 2012 Agilent Technologies
  44. 44. Combining CAD and Board Files Precise landing of connector fingers on board signal pad Copyright © 2012 Agilent Technologies
  45. 45. Near-Field Radiation: Do we need Shielded Connector? ($0.15 more cost) Do we need copper-tape under connector? •Simulated with FDTD-solver (Agilent EMPro) •Accelerated on GPU system •Simulation time ≈ ½ day with 1-GPU card and 2-hrs with 3-GPU cards Study if improved grounding & shielding of the connector improves EMI behavior Copyright © 2012 Agilent Technologies
  46. 46. Improved Grounding of the Connector: What is the impact of a copper-tape under the connector No copper tape Extra copper tape Copyright © 2012 Agilent Technologies
  47. 47. Improved Grounding: Far-field impact of CU-tape Reduction of 5 dB for EMI emission In direction of chassis Copyright © 2012 Agilent Technologies
  48. 48. Conclusion •“Virtual-EMI” Lab is a MUST for Speed-of-Light Product-to-Market •Radiated/Conducted-Emission: •Packages Return-Path-Discontinuity driving the need to turn-ON SS ORDER A TRIAL VERSION FOR ADS http://www.agilent.com/find/ee sof-ads-si-evaluation • PCBs due to Cost-Reduction 4L-PCBs” – MA/CMD Emission by referencing to VddQ – TMDS Emission due to routing on Bottom layer • SSO Noise Emission by VddQ Current-Profile on PCB Decaps are very effective • Emission of Connector+Cables from HDMI common-mode noise Copyright © 2012 Agilent Technologies

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