Slow dancing pdn on memory-controller-packages may-10th_2012_hf_last

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Slow dancing pdn on memory-controller-packages may-10th_2012_hf_last

  1. 1. ‘SLOW-DANCING’ PDN FOR MEMORY CONTROLLER PACKAGES Hany M Fahmy HSD Application Expert Agilent Technologies Inc. Davy Pissoort, KHBO-K.U. Leuven May 10th , 2012 1 Confidentiality Label May 10, 2012
  2. 2. What is the Spectral Content of the SSO noise? We have Strong Harmonics close to 10GHz for DDR3-1866 2 Confidentiality Label May 10, 2012
  3. 3. I am driving from the Voltage-Regulator to the VddQ Die-Bumps, why I am having so many accidents!!!!! • Noise Frequency Distribution: 1. 2. 3. 4. IR Drop (DC losses) through the whole path VR noise in the KHz range (switching VR noise usually 450Khz to 500KHz for DDR3 systems)  Controlled by the on-PCB decaps mainly Low-Freq noise in the MHz range is controlled by the on-PCB decaps and also the on-PKG decaps do support as well SSO noise in the GHz range is controlled by the on-die ad on-PKG decaps MOM do provide a Single-Shot Solution from DC up to the GHz range of the SSO noise unlike conventional tools that do have separate solutions for IR-Drop then Low-Freq and Hybrid-Techniques can’t be used for SSO GHz noise 3 Confidentiality Label May 10, 2012
  4. 4. Proposed PDN Optimization Strategy: - PDN Resonances & FD optimization of decaps  MOM + ADS Schematic - Co-SI/PI eye-sim  Convolution Transient engine - EMI & P2P  FDTD Simulations with Icc(t) OR CPM 4 Confidentiality Label May 10, 2012
  5. 5. New Outlook at PI Problems in HSD systems 1. MOM-FD  extraction of PDN for PKG & PCB 2. ADS-Schematic  Lump on-die PDN model & VR & on-PKG decaps & on-PCB decaps 3. ADS-Optimizer Optimize the PDN decaps for Target Impedance profile from DC to the GHz range (detecting resonances & damp them using all decap schemes on-die+on-PKG+on-PCB 4. MOM-FD  Extraction of PDN+Data-nets for PCB & PKG (Example # 1) 5. ADS-Schematic  lump on-die PD model & VR & on-PKG decaps & on-PCB decaps obtained from # 3. Add VR low-frequency noise profile (switching VR noise in the KHz range). 6. Transient Convolution TD analysis with IBIS model or BSIM4 models to study the impact of VR-noise & SSO-noise & IR-drop all together on the data-eye-opening. 7. Measure the Current-profile Icc(t) on VddQ pins on PCB 8. FDTD of PCB  Inject the current profile Icc(t) from # 7 to fine-tune the onPCB decaps for minimum Radiated-Emission of SSO noise (Example # 2) 5 Confidentiality Label May 10, 2012
  6. 6. EXAMPLE 1: STEPS # 1-3 DETECTION OF RESONANT FREQUENCY OF THE WHOLE PDN SYSTEM OPTIMIZATION OF DECAPS TO MEET CERTAIN IMPEDANCE PROFILE 6 Confidentiality Label May 10, 2012
  7. 7. FD Optimization of the PDN network 7 Confidentiality Label May 10, 2012
  8. 8. Impact of decoupling schemes? FD Optimization PKG DIE VR PCB 8 Confidentiality Label May 10, 2012
  9. 9. EXAMPLE 2: STEP # 4 STUDYING THE RELATIONSHIP BETWEEN RPD & NOISECOUPLING BETWEEN VDDQ & DATA-NETS 9 Confidentiality Label May 10, 2012
  10. 10. Co-SI/PI Modeling OF Multi-Giga-bit EMI effects Optimizing on-PKG decaps for Minimum coupling of Power-Noise to Data-Signals • Signal layer transitions: L1-2-L3 is it same like L1-2-L5? • Open-stubs of Vias • Stitching vias impact (# & Locality) 10
  11. 11. DDR3 Package Modeling using MOM DC to 20GHz DQ nets major referencing to GND 11 May 10, 2012
  12. 12. Routing of DQ signals from Bumps-Top to Layer-3 running as Symmetric-SL sandwiched between GND on Layers 2 & 4 DQ signals on Layer-3 as Symmetric-SL DQ signals @ Die-Bumps Optimizing on-PKG decaps for Minimum Power-Noise to SignalCoupling 12 May 10, 2012
  13. 13. Moving from Layer-3 to Layer-6 through Signal-PTH to pickup the Balls DQ signals on Layer-6 routed between GND on layers 5 13 DQ signals on Layer-3 May 10, 2012
  14. 14. Impact of GND-PTH stitching: Proximity & # Original-Package: PKG1 with 15-GND-PTH 14 2011 EMEA
  15. 15. Impact of GND-PTH stitching: Proximity & # New Proposal-Package:PKG2 with ONLY 3-GNDPTH 15 May 10, 2012
  16. 16. Impact of GND-PTH stitching: Proximity & # Test-case Package: PKG3 with 0-GND-PTH 16 May 10, 2012
  17. 17. FD Risk Assessment of VddQ-Noise coupling to Data-Signals AC NOISE-SOURCE PACKAGE MOM S-MODEL PORTS DIE-BUMP & DECAPS & BALLS & 8-DATA SIGNALS + DQS/DQS# + DQM SWEEPING AMPLITUDE @ VDDQBUMP ON-PKG DECAPS 17 MB LOADING MODEL Confidentiality Label May 10, 2012
  18. 18. NOISE-COUPLING TO TOGGELLING DATA-SIGNALS 0V noise @ VddQ-Bump Cpkg 15 GND-PTH 18 Confidentiality Label May 10, 2012
  19. 19. DO ON-PKG DECAPS IMPACT THE COUPLING-FREQ AND AMOUNT OF COUPLING? 19 Confidentiality Label May 10, 2012
  20. 20. NOISE-COUPLING TO TOGGELLING DATA-SIGNALS 300mV noise @ VddQ-Bump Cdie 50pF per I/O Cpkg is 4.7uF 15 GND-PTH 100mV noise coupling at 2.57GHz 20 Confidentiality Label May 10, 2012
  21. 21. NOISE-COUPLING TO TOGGELLING DATA-SIGNALS 300mV noise @ VddQ-Bump Cdie 50pF per I/O Cpkg is 0.001uF 15 GND-PTH 100mV noise coupling at 2.57GHz & 180MHz 21 Confidentiality Label May 10, 2012
  22. 22. NOISE-COUPLING TO TOGGELLING DATA-SIGNALS 300mV noise @ VddQ-Bump Cdie 50pF per I/O Cpkg is 1pF 15 GND-PTH 700mV noise coupling at 1.39GHz 22 Confidentiality Label May 10, 2012
  23. 23. IS THERE A RELATIONSHIP BETWEEN RPD AND NOISECOUPLING? 23 Confidentiality Label May 10, 2012
  24. 24. NOISE-COUPLING TO TOGGELLING DATA-SIGNALS 0mV noise @ VddQ-Bump Cdie 50pF per I/O Cpkg is 4.7uF 3 GND-PTH 24 Confidentiality Label May 10, 2012
  25. 25. NOISE-COUPLING TO TOGGELLING DATA-SIGNALS 300mV noise @ VddQ-Bump Cdie 50pF per I/O Cpkg is 4.7uF 3 GND-PTH 40mV MORE noise coupling at 2.57GHz for 3-GND-PTH than 15-GND-PTH 25 Confidentiality Label May 10, 2012
  26. 26. NOISE-COUPLING TO TOGGELLING DATA-SIGNALS 300mV noise @ VddQ-Bump Cdie 50pF per I/O Cpkg is 4.7uF 1 GND-PTH 26 20mV LESS noise coupling at 2.57GHz for 1GND-PTH than 15-GND-PTH BUT 200mV wide-band coupling around 4.7GHz Confidentiality Label May 10, 2012
  27. 27. EXAMPLE 3: STEP # 8 WHAT IS THE BENEFIT OF ONPCB DECAPS UNDER THE IC? 27 Confidentiality Label May 10, 2012
  28. 28. Combining Measured Icc(t) SSO Noise Source Extraction with FDTD simulations to study the critical on-boarddecaps under the GPU Power Delivery Network Current Probe @ VddQ pins Drivers Channel Receivers • SSO current is obtained by a combined simulation of the power delivery network model and the memory IO channel model WORKSHOP EMEA
  29. 29. SSO Noise Measured Dynamic-current profile Icc(t) fft ifft steady-state frequencies •Time-domain noise pattern directly imported into FDTD solver 29 WORKSHOP EMEA
  30. 30. Board Geometry Improting PCB layout of the Memory- Channel Stackup 8 cm Signal Ground Signal VDD Ground VDD 11 cm board thickness: 1.57mm 30 WORKSHOP EMEA
  31. 31. SSO Noise Source on Top Layer Noise sources IC 31 31 WORKSHOP EMEA
  32. 32. Decaps on Bottom Layer decaps 32 32 WORKSHOP EMEA
  33. 33. Far-Field Radiation at 0.5 GHz With Decaps Without Decaps Reduction of 3-4 dB 33 33 WORKSHOP EMEA
  34. 34. Far-Field Radiation at 1.0 GHz With Decaps Without Decaps Reduction of 3-4 dB 34 34 WORKSHOP EMEA
  35. 35. Current Density at 0.5 GHz (1) Without Decaps 35 35 WORKSHOP EMEA
  36. 36. Current Density at 0.5 GHz (2) With Decaps 36 36 WORKSHOP EMEA
  37. 37. Conclusion • Accurate modeling of Data-signals along with VddQ & VssQ is important to capture VddQ-Noise Coupling to Data-Signals • MOM is well suited to Model Data-Signals + VddQ + VssQ including Return-Path-Discontinuity • PDN Decoupling & GND-Stitching (Return-path-discontinuity) impacts the Amount of VddQ-Noise coupling as well as the Coupling-Frequency & Bandwidth of noise-coupling • FDTD is best suited for SSO noise Modeling the impact of onPCB decaps to mitigate Radiated Emission caused by PCB edge-emission due to noise pn PDN 37 Confidentiality Label May 10, 2012

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