multilevel inverter

1. Design and Simulation of Five Level Cascaded Inverter using Multilevel Sinusoidal Pulse
Width Modulation Strategies
V.Manimala
PG Student/EEE Department
Mepco Schlenk Engineering College
Sivakasi,Tamilnadu,India
E-mail:malajan22@gmail.com
Mrs.N.Geetha M.E.,
Asst Professor/EEE Department
Mepco Schlenk Engineering College
Sivakasi,Tamilnadu,India
Email:geethanatarajan04@gmail.com
Dr.P.Renuga
Asso Professor/EEE Department
Thiagarajar College of Engineering
Madurai-15,Tamilnadu,India
E-mail:preee@tce.edu.in
Abstract-This paper proposes design and simulation of single
phase cascaded five level inverter. The inverter can produce five
different output voltage levels across the load. The multilevel
sinusoidal pulse width modulation switching strategy was used
and THD value for every scheme was analyzed. The main
advantage of this technique is the ability to reduce harmonics.
MATLAB/SIMULINK software was used for simulation and
verification of the proposed circuit for implementing FPGA
based five level cascaded inverter. The proposed circuit produces
high output voltage without use of transformers and lower
electromagnetic interference.
Keywords- multilevel inverter, multilevel Sinusoidal pulse
width modulation, five level inverter, total harmonic distortion
I. INTRODUCTION
Recently the multilevel inverter topology has drawn
tremendous interest in the power industry since it can easily
provide the high power required for high power
applications such as static VAR compensation, active filters
so that large motors can be controlled by high power
adjustable frequency drives. The unique structure of
multilevel voltage source inverters allows them to reach
high voltages with low harmonics without the use of
transformers or series connected synchronized switching
devices. There are three main topologies of multilevel
inverter, they are diode clamped, flying capacitor and
cascaded inverters [1]-[3].
Field-Programmable Gate Arrays (FPGA) are standard
integrated circuits that can be programmed by the user to
perform a variety of complex logic functions. The high
level of integration available with these devices are
currently upto 500,000 gates.
PWM is a common control strategy used in many
different applications. This technique is the heart of the
inverter control signal. Several modulation control
strategies have been proposed or adopted for multilevel
inverters including the following: multilevel sinusoidal
pulse width modulation, multilevel selective harmonic
elimination, and space-vector modulation. In this paper
multilevel sinusoidal pulse width modulation for five level
cascaded inverter is developed. To develop the model of
five level cascaded multilevel inverter, simulation is done
based on MATLAB/SIMULINK software.
II. CASCADED MULTILEVEL INVERTER
A cascaded multilevel inverter consists of a series of H-
Bridge (single phase full bridge) inverter units. The general
function of this multilevel inverter is to synthesize a desired
voltage from several separate dc sources (SDCSs), which
may be obtained from batteries, fuel cells or solar cells
[1],[8]. The number of H-Bridge module (M), depends on
the number of levels (N) and can be written as
M = (N-1)/2
For example, a 5-level cascaded inverter has two full
bridges. The structure of single phase cascaded five level
inverter is shown in the figure 1. By different combinations
of the four switches S1-S4, each inverter level can generate
three different voltage outputs, +Vdc, -Vdc, and zero. The
AC output of each of the different levels of inverters are
connected in series such that the synthesized voltage
waveform is the sum of the inverter outputs.
Advantages:
• Elimination of excessively large number of bulky
transformers required by the multi-phase inverters.
• Avoidance of extra clamping diodes and flying
capacitors which are required by diode clamped
and flying capacitors multilevel inverters.
• Simple and modular configuration.
• Flexibility in extending to higher number of levels.
III. MULTILEVEL SINUSODIAL PULSE WIDTH
MODULATION
The advent of the transformer less multilevel inverter
topology has brought various pulse width modulation
schemes to control the switching of the active devices in
each of the multiple voltage levels in the inverter.
Multilevel inverter is based on classical two levels
sinusoidal pulse width modulation (SPWM) with triangular
carrier and reference waveform. Only difference between
two level SPWM and multilevel SPWM [4]-[7] is the
number of carriers used. For N level inverter N-1 carriers
are used. For example for constructing five level we need
four carriers. Carriers have the same frequency fc and the
peak–peak amplitude Ac and are disposed so that the bands
they occupy are contiguous. The zero reference is placed in
the middle of the carrier set. The modulating signal is a
sinusoidal waveform of frequency fr and amplitude Ar. At
every instant each carrier is compared with the modulating
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978-1-4244-8679-3/11/$26.00 ©2011 IEEE

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signal. Each c
signal is grea
the first o
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the voltage le
the inverters.
pulse width m
TABLE I SWITC
Switches
S11
S21
S31
S41
S12
S22
S32
S42
A. Alternative
All the c
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Fig
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Figure 1. T
CHING STRATEGY
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e Phase Oppo
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figure 2. In th
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Types of MSPWM
Y FOR FIVE LEVE
Load Voltag
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OFF OFF
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osition Dispos
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his method ca
amplitude; the
jacent carriers
Waveform for APO
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triangular car
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he output term
multilevel sinu
hown in the fi
M
L CASCADED INV
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sition (APOD)
n position wh
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VERTER
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ure 3. PWM Wav
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hod there are
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litude and are
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the zero refer
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per module
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have
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281

3. Modulation P
The am
of MSPWM t
Modulation
index
Ma
Where N
N- numbe
Frequency
IV. SIMUL
The sing
various PWM
technique ar
R2007a.For f
needed for sim
the each brid
output. MOSF
reducing the h
proposed cir
modulation t
technique. F
techniques, si
in the simul
voltages are
analysis for a
Figure 6. Simu
Parameters
mplitude modu
techniques are
TABLE II M
APOD
A
A
c
r
N '
’ is given by
N’
er of levels in
y modulation
M
LATION CIRCUI
IN
gle phase cas
M techniques
re simulated
five level casc
mulation as sh
dge is added
FET switches
harmonics in
rcuit uses mu
technique tha
For all the
imulations are
ation circuit
noted. Tota
all the PWM te
ulation circuit of
ulation indice
e shown in the
MODULATION IND
POD
A
A
c
r
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= (N-1)/2
the inverter
ratio is given
Mf = fr /fc
IT FOR CASCA
NVERTER
scaded five l
s and Switch
with the
caded inverte
hown in the f
in series to o
s are used as p
the output vo
ultilevel sinu
an the switch
e configurati
e done by var
and their co
al Harmonic
echniques are
f five level cascad
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e table.
DEX
PD P
A
A
c
r
N ' A
A
n by
ADED FIVE LE
level inverter
hing angle va
use of MA
er two H-bridg
figure. The ou
obtain the fiv
power switch
oltage wavefor
usoidal pulse
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e done.
ded multilevel in
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A
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ariation
ATLAB
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rm, the
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system
output
(THD)
nverter
Figure 7. Outpu
Figure 8.
Figure 9.
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ut voltage wavefo
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Output Voltage w
. Output Voltage
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chnique
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POD PWM
ng PD PWM
on
282

4. Figur
THD valu
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modulation i
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Figure
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five level inv
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re 11. Output volt
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ulation indice
as shown in
indices resul
all the types o
r POD PWM t
12. THD analysi
V. C
rk proposed
ulse width m
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an be reduce
figuration of m
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sposition PW
he harmonics
modulation ind
armonics in th
tage waveform us
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THD value
es for every M
n figure 12. T
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than the other
s for different typ
ONCLUSION
the simula
modulation sc
harmonics in
ed significant
multilevel sin
he harmonic
WM contains lo
s can be reduc
dices. By incr
he output volta
sing PS PWM
echniques are
om switching
of 45%. TH
MSPWM tech
The increase
tion of harm
have slightly
rs.
pes of MSPWM
ation of mu
cheme for ca
the output v
tly by utilizi
nusoidal pulse
contents for
ower harmoni
ced by selecti
reasing the lev
age waveform
nearly
g angle
HD for
hniques
in the
monics.
y lower
ltilevel
ascaded
voltage
ng the
e width
r phase
cs than
ing the
vels we
m.
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[2]
[3]
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