A high density, high-efficiency, isolated on-board vehicle battery charger utilizing silicon carbide power devices

2606 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 5, MAY 2014
A High-Density, High-Efficiency, Isolated On-Board
Vehicle Battery Charger Utilizing Silicon
Carbide Power Devices
Bret Whitaker, Member, IEEE, Adam Barkley, Member, IEEE, Zach Cole, Brandon Passmore, Member, IEEE,
Daniel Martin, Member, IEEE, Ty R. McNutt, Member, IEEE, Alexander B. Lostetter, Member, IEEE,
Jae Seung Lee, and Koji Shiozaki
Abstract—This paper presents an isolated on-board vehicular
battery charger that utilizes silicon carbide (SiC) power devices to
achieve high density and high efficiency for application in electric
vehicles (EVs) and plug-in hybrid EVs (PHEVs). The proposed
level 2 charger has a two-stage architecture where the first stage is
a bridgeless boost ac–dc converter and the second stage is a phase-
shifted full-bridge isolated dc–dc converter. The operation of both
topologies is presented and the specific advantages gained through
the use of SiC power devices are discussed. The design of power
stage components, the packaging of the multichip power module,
and the system-level packaging is presented with a primary focus
on system density and a secondary focus on system efficiency. In
this work, a hardware prototype is developed and a peak system
efficiency of 95% is measured while operating both power stages
with a switching frequency of 200 kHz. A maximum output power
of 6.1 kW results in a volumetric power density of 5.0 kW/L and
a gravimetric power density of 3.8 kW/kg when considering the
volume and mass of the system including a case.
Index Terms—AC–DC power converters, battery charger, dc–dc
power converters, electric vehicles (EVs), power electronics, silicon
carbide (SiC).
I. INTRODUCTION
THE negative environmental and sociopolitical impacts of
fossil fuel consumption coupled with finite fuel resources
has recently prompted environmental and oil independence ini-
tiatives in both federal and state governments. Many of these
initiatives focus on furthering the development of vehicular tech-
nology for both fully electric vehicles (EVs) and plug-in hybrid
EVs (PHEVs) [1]. Specifically, advances in power electronics
Manuscript received February 14, 2013; revised June 6, 2013 and August 7,
2013; accepted August 12, 2013. Date of current version January 10, 2014. This
work was supported in part by the Advanced Research Projects Agency-Energy
(ARPA-E), U.S. Department of Energy, under Award DE-AR-0000110. Rec-
ommended for publication by Associate Editor L. M. Tolbert.
B. Whitaker, A. Barkley, Z. Cole, B. Passmore, D. Martin, T. R. McNutt, and
A. B. Lostetter are with the Arkansas Power Electronics International (APEI),
Inc., Fayetteville, AR 72701 USA (e-mail: bwhitak@apei.net; abarkle@
apei.net; zcole@apei.net; bpassmo@apei.net; dmartin@apei.net; tmcnutt@
apei.net; alostet@apei.net).
J. S. Lee and K. Shiozaki are with the Toyota Research Institute, North
America Toyota Motor Engineering and Manufacturing North America, Inc.,
Ann Arbor, MI 48105 USA (e-mail: jae.lee@tema.toyota.com; koji.shiozaki@
tema.toyota.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2279950
are required to meet the increasing demands for automotive
electrical power while minimizing the weight and volume of
the system, to lessen the impact on vehicular system packaging,
and to maximize the efficiency of the system [2], [3]. In addition
to providing performance improvements, it is critical that these
technologies increase the usability, marketability, and consumer
acceptance of these vehicles.
On-board battery charging is one such technology that can
reduce end user range anxiety by allowing for the vehicle’s
battery to be charged from any available power outlet. While
having such a system on board the vehicle provides conve-
nience, it also adds volume and weight. A compact, lightweight
charger is needed in order to maintain vehicle operating effi-
ciency and to limit system costs for effective competition with
conventional combustion engines. Densification of power elec-
tronic systems can be achieved through a reduction in passive
filter component size by operating at high switching frequencies
and/or through minimization of the thermal management sys-
tem by either increasing operational efficiency or by allowing
for higher operating temperatures. Current silicon (Si) technol-
ogy can support high-frequency operation however Si power
device performance degrades severely at higher junction tem-
peratures. A high-frequency PHEV battery charger with reduced
magnetic component size is presented in [4] however thermal
limitations in Si technology prevent further densification. As Si
devices reach their intrinsic limits, other semiconductor technol-
ogy must be considered to achieve further advances in system
density and efficiency.
Silicon carbide (SiC) is a wide bandgap semiconductor with
many advantages over Si technology. The high breakdown elec-
tric field of SiC allows for the voltage blocking layers to be
designed such that an approximately 100× advantage in on-
state resistance over Si can be achieved [5]. The active area of a
SiC device, when compared to a Si device with the same current
rating, can be reduced that decreases the device capacitance
and promotes operation at higher switching frequencies [6].
The wide bandgap properties allow for higher junction temper-
atures and the high thermal conductivity and low coefficient of
thermal expansion (CTE) makes the packaging of SiC power
devices more reliable across a wide range of temperatures [7].
Although SiC power device technology is still relatively imma-
ture, the theoretical benefits of SiC are continually being demon-
strated in laboratory hardware. For example, SiC JFETs were
found to be electrically and thermally superior to Si CoolMOS
devices for comparably designed boost converters for HEV
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WHITAKER et al.: HIGH-DENSITY, HIGH-EFFICIENCY, ISOLATED ON-BOARD VEHICLE BATTERY CHARGER UTILIZING SiC POWER DEVICES 2607
TABLE I
CHARGER SYSTEM PERFORMANCE METRICS
applications [8]. The high switching frequency capability of
SiC devices was demonstrated in [9] and the high operating
temperature capability was showcased in [10]. The impact of
SiC devices across various converter topologies has been stud-
ied and was found to be significant for medium-voltage (0.4–
5 kV) isolated dc–dc converters [11] as has been theorized in
previous literature [12]. Overall, the advanced properties of SiC
devices allow for significant reductions in a converter’s thermal
management system and improvements in system density and
efficiency when compared to a similar Si-based system [13].
This paper presents an on-board battery charger for future
application in EVs and PHEVs utilizing SiC power devices to
achieve a high-density, high-efficiency solution. The proposed
charger can operate from a universal input and provide a max-
imum output power of 6 kW. This power level classifies the
charger as a level 2 system [14] which has been theorized to
have a higher likelihood of widespread adoption due to the
prevalence of suitable power outlets and the lack of infrastruc-
ture for higher power fast chargers [15]. The performance met-
rics of the proposed charger are shown in Table I where they are
compared to specifications of the on-board battery charger for
the 2010 model Toyota Prius Plug-in Hybrid [16] and prelim-
inary (in progress) future targets proposed by the Department
of Energy (DOE) [17]. The proposed charger achieves more
than a 10× increase in volumetric power density and a 9×
increase in gravimetric power density, when compared to the
2010 Toyota Prius Plug-in Hybrid battery charger. Additionally,
the proposed charger achieves a volumetric power density more
than 5× higher, and a gravimetric power density 4× higher than
the DOE’s targets for the year 2022.
The circuit schematic for the proposed charger is shown in
Fig. 1 where a conventional two-stage approach is implemented.
The primary focus of the design is system density with a sec-
ondary focus placed on system efficiency. The density target
was selected to be an order of magnitude above that of the
previously mentioned Toyota charger and the efficiency was se-
lected to be greater than the DOE target of 94%. The selection
of power topology, design of power stage components, design of
the multichip power module (MCPM), and system-level pack-
aging considerations are presented in the paper. Additionally,
a hardware prototype is built and tested to verify the operation
of the system. Experimental results of the system show a peak
efficiency of 95% and a peak power level of 6.1 kW. These
measurements, along with the volume and mass of the con-
verter including a case, result in a volumetric power density of
5.0 kW/L and a gravimetric power density of 3.8 kW/kg. These
figures represent an order of magnitude improvement over the
2010 Toyota Prius Plug-in Hybrid battery charger and signifi-
cant improvement over the projected future DOE targets.
II. FIRST STAGE: AC–DC CONVERTER
A. Topology Selection
A bridgeless boost power factor correction (PFC) converter
was selected to implement the ac–dc conversion for the system
based on both high achievable density and high efficiency. This
topology provides significant benefits over a conventional full-
bridge-rectified boost PFC converter by eliminating the diode
bridge, reducing the total number of power semiconductor de-
vices, and reducing the conduction loss due to fewer power
devices in the current-carrying path [18]. These factors al-
low for significant improvements in the efficiency of bridgeless
boost converters when compared to the conventional full-bridge-
rectified alternatives [19]. The bridgeless boost converter also
benefits from using only low-side MOSFETs that eliminates the
need for isolated high-side gate drivers and reduces the amount
of auxiliary components. Previous research has found this topol-
ogy to have high achievable density due in part to this converter
having the smallest MOSFET area required for equal conduc-
tion losses when compared to alternative topologies [20]. Ad-
ditionally, the utilization of SiC power devices in this topology
provides significant improvements in efficiency, operational fre-
quency, and converter density. SiC Schottky diodes provide an
advantage over Si power diodes in boost PFC applications [21],
especially at frequencies in excess of 100 kHz [22], due to their
negligible reverse recovery current. The frequency limit of this
converter is extended further by using SiC power MOSFETs
with inherently low switching energy.
B. Theory of Operation
The bridgeless boost converter is operated by switching only
one MOSFET per half-cycle of the ac input voltage while hold-
ing the other MOSFET on to conduct current. This operating
mode is depicted in Fig. 2 where switch S3 is modulated and S4
is turned on continuously in a positive half-cycle. The duty cycle
of S3 is varied to shape the input current into a sine wave that
matches the phase of the input voltage. The duty cycle of switch
S3 in the positive half-cycle of the input voltage is expressed as
d3(t) = 1 −
vin(t)
Vdc
, vin > 0. (1)
In this same half-cycle, S4 is on continuously.
Upon transitioning to the negative half-cycle, the operation is
reversed and S3 is held on continuously while S4 is modulated
to shape the input current. The duty cycle of S4 in the negative
half-cycle of the input voltage is expressed as
d4(t) = 1 −
|vin(t)|
Vdc
, vin < 0. (2)
In this half-cycle, S3 is on continuously.

Fig. 1. Proposed two-stage vehicle battery charger comprised of a bridgeless boost ac–dc converter and a phase-shifted full-bridge isolated dc–dc converter.
Fig. 2. Ideal operating waveforms for the bridgeless boost converter with
exaggerated gate signals to demonstrate duty cycle trends.
This method of operation actively switches each device for
only half of the ac period, allowing for the total switching losses
of this two-MOSFET stage to be equivalent to the switching
loss of a single MOSFET in a conventional full-bridge-rectified
boost PFC converter.
III. SECOND STAGE: ISOLATED DC–DC CONVERTER
A. Topology Selection
The phase-shifted full-bridge (PSFB) converter is a well-
researched topology for medium- to high-power applications
where isolation is required [23], [24]. Its main advantages are
low voltage stress on the primary-side power devices, low cur-
rent stress, and the ability to achieve zero-voltage switching
(ZVS) without the addition of auxiliary components or complex
control implementation. ZVS is especially critical for volume-
and weight-sensitive applications because it allows for a reduc-
tion in required thermal management due to more efficient oper-
ation of the converter. Another well researched topology, which
has a similar architecture to the PSFB converter, is the dual-
active bridge converter. Previous research has demonstrated the
capability of a dual-active bridge converter to achieve high den-
sity [25] and the potential benefits of using SiC power devices
with this topology has also been discussed [12]. The major
downside to this topology is that it requires four additional
MOSFETs and additional auxiliary circuitry that will increase
the cost, complexity, and potentially the volume of the system.
The previous research on the PSFB converter focuses mainly
on efficiency improvements and neglects the potential for den-
sification through the use of SiC power device and higher
frequency operation. The low output capacitance of SiC
MOSFETs, relative to their voltage blocking capability, al-
lows for a higher achievable switching frequency and extended
ZVS range. These devices also benefit from relatively stable
on-resistance at elevated temperatures [26] which is critical for
this topology due to the high circulating currents under nonideal
operating conditions. Another advantage is gained through the
high voltage blocking capability of SiC devices, especially for
the rectifying diode bridge that is subject to high amplitude
voltage spikes. This improves the converter efficiency by elim-
inating the need for a lossy RCD snubber circuit on the output
diode bridge that is conventionally required [24].
B. Theory of Operation
The PSFB converter operates with an approximately 50%
duty cycle for each switch position. Deadtime is inserted be-
tween the upper and lower devices in a given bridge leg to pre-
vent shoot-through currents and to allow the resonant transition
for ZVS switching. Power flow is controlled by adjusting the
phase shift between bridge legs that effectively modulates the
time per switching cycle when diagonal switch pairs are simul-
taneously conducting. ZVS is achieved by utilizing the energy
stored in inductors downstream of the MOSFETs to discharge
their effective output capacitance before the device is turned on.
Idealized waveforms highlighting the fundamental operation of

Fig. 3. Ideal operational waveforms for the PSFB converter.
the converter are shown in Fig. 3. Key time instants (t0 through
t7) are denoted by dashed vertical lines.
At time t0, the device S6 is turned off. This completes an
interval in which current is circulating through the converter,
via switches S5 and S6, and initiates the voltage transition for
the lagging bridge leg. In the time interval between t0 and t1,
the current in the secondary begins to freewheel through the
rectifying diodes and the secondary circuit becomes decoupled
from the primary. Due to this decoupling, only the energy stored
in the resonant inductor Lr can be utilized to discharge the ef-
fective device capacitance. Thus, full soft-switching only occurs
when the following condition is satisfied
iLr
(t0) ≥ Vdc
2Ceff
Lr
(3)
where Ceff is the effective capacitance of one full-bridge quad-
rant that includes the parallel combination of the MOSFET
output capacitance, diode junction capacitance, and other stray
parasitic capacitances. Reduced switching losses may still be
achieved at lower current levels where (3) is not met due to
partial soft-switching.
At time t1, the voltage across S8 has reached zero and that
device turns on under ZVS conditions at time t2. The peak ampli-
tude of the resonant voltage transition occurs at approximately
one-quarter of the resonant period of the resonant inductor and
the effective capacitance of two quadrants, which is expressed
as
tres =
π
2
2Lr Ceff . (4)
The deadtime inserted between upper and lower devices on
the lagging leg should be set to this quarter resonance period to
allow the device to turn off at the peak of the resonant transition.
Although a voltage is applied across vAB , the voltage of the
transformer primary is clamped near zero until time t3 when the
resonant inductor current becomes equal to the reflected output
current. At this time, the output diodes stop freewheeling, the
secondary is again coupled to the primary, and a power transfer
interval begins. The interval between t0 and t3 represents an
effective loss of duty cycle for this converter. This duty cycle
loss was modeled in [23] as
ΔD =
2nLr
VdcTsw
2Io −
Vo(1 − D)Tsw
2Lo
(5)
where Tsw is the switching period and D is the applied duty
cycle.
Device S5 is turned off at time t4, which stops the transfer
of power and starts the circulation of current. At this time, the
secondary remains coupled to the primary and thus the energy
stored in both the resonant inductor Lr and the output inductor
Lo is used to discharge the effective capacitance of S7. ZVS
for this leading transition occurs across a wider range of power
levels because the required condition is easier to meet—both
because there are now two energy storage elements and because
the current is at its peak value. The current required to achieve
ZVS for the leading leg can be expressed as
iLr
(t4) ≥ Vdc
2Ceff
Lr + (Lo /n2)
. (6)
There is no duty cycle loss associated with a leading leg tran-
sition because there is no freewheeling current in the secondary
and it remains coupled to the primary.
At time t6, switch S7 turns on under ZVS. Current continues
to circulate with a decreasing slope until time t7 when device
S8 turns off. At this time, the primary and secondary again
decouple, the effective duty cycle loss is seen again, and this
sequence is repeated where t7 is analogous to t0 for the other
two devices.
IV. COMPONENT DESIGN AND SYSTEM PACKAGING
The primary focus of the system design was to minimize the
total charger volume and to achieve an order of magnitude in-
crease in power density over the technology currently used in the
2010 model Toyota Prius Plug-in Hybrid. A secondary goal of
the design was to achieve an efficiency of above 94% (the DOE
target outlined in Table I). Additionally, the system was designed
to accept a universal input voltage and deliver a maximum output
power of 6 kW. With these goals in mind, targets for each indi-
vidual power stage were selected to achieve the desired system
level performance. The current and voltage ripple specifications
were selected to balance volume and weight with efficiency.
An additional constraint was included: avoidance of electrolytic
capacitors, specifically on the dc-bus, due to lifetime concerns
and destructive failure modes. The target switching frequency
for the dc–dc converter was selected to be 500 kHz because this
stage contains a greater number of magnetic components that
can be minimized through high-frequency operation and also
because the ZVS operation of this stage will minimize switch-
ing losses. The target switching frequency of the ac–dc stage
was selected to be 250 kHz to maintain compactness while also

TABLE II
ON-BOARD CHARGER INITIAL DESIGN SPECIFICATIONS
minimizing the switching losses for this hard-switching stage.
The design specifications are summarized in Table II.
A. AC–DC Converter Passive Components
The input inductor was designed to limit the high-frequency
ripple current drawn from the grid without significantly impact-
ing the volume and weight of the system. A 5 A peak-to-peak
current ripple, representing roughly 15% of the maximum peak
current, was selected as an acceptable tradeoff between these
two factors. The value of inductance was then calculated using
ΔiLin
(t) =
d(t)Tsw vin(t)
Lin
. (7)
A total input inductance of 80 μH was calculated. This induc-
tance was split between two inductors fabricated on a common
core to improve the magnetic utilization. A ferrite core was used
because of its superior performance at high frequencies. The
coupled inductors were built using planar windings to minimize
the footprint and total volume.
The dc-bus capacitor was sized according to allowable low-
frequency ripple voltage on the dc-bus. The value of capacitance
was calculated using
Cdc =
Po-ac/dc
2πffundV 2
dc(%Vdc-ripple)
(8)
where Po-ac/dc is the output power of the ac–dc stage, ffund is the
fundamental frequency of the input ac voltage, and %Vdc-ripple
is the peak-to-peak voltage ripple at twice the fundamental fre-
quency on the dc-bus as a percentage of the nominal dc-bus
voltage. For this calculation, the nominal dc-bus voltage was
assumed to be 350 V with a desired voltage ripple of 30% of
this value. The very high voltage ripple was selected due to the
relatively large size of commercially available film capacitors
that were utilized for this design in place of electrolytic capaci-
tors. Due to the volume constraints, a final value of 300 μF was
selected from the limited availability of commercial capacitors
that meet this system’s form factor. This capacitance was im-
plemented using two parallel 150 μF metallized polypropylene
film capacitors made specifically for dc-bus applications.
B. DC–DC Converter Passive Components
The resonant inductor was designed according to (3) such
that ZVS could be achieved for the lagging leg whenever the
primary current is at or above 8 A, which represents 40% of the
maximum output current. A resonant inductance of 3.2 μH was
calculated and designed using a ferrite core and a wire wound
strategy. Litz wire was used to reduce the ac resistance caused
by the skin effect.
The turns ratio of the isolation transformer was designed to
provide an adequate step up in output voltage to overcome the ef-
fective duty cycle loss without overstressing the rectifying diode
bridge. The primary-to-secondary turns ratio was designed ac-
cording to
n =
Vout-max
VdcDeff -max
(9)
where Deff -max is the maximum effective duty cycle. A primary-
to-secondary turns ratio of 1:1.5 was selected to balance the two
aforementioned considerations assuming a maximum effective
duty cycle of 80%. The transformer was implemented using a
ferrite core and a planar winding strategy. Particular attention
was given to the layering of the windings to reduce the ac
resistance caused by proximity effects.
The output inductor was designed to limit the output ripple
current occurring at twice the switching frequency. The induc-
tance was designed according to
Lo =
nVdc − Vo
ΔiLo
Deff Tsw
2
. (10)
A calculated inductance of 20 μH gives a maximum peak-
to-peak ripple current of approximately 5 A, which is 25% of
the maximum output current. The output inductor was designed
using a ferrite core with planar windings to minimize volume.
The cutoff frequency of the output filter was designed by
properly selecting the output capacitance. The required capaci-
tance was calculated using
Co =
1
(2πfc )2Lo
(11)
while assuming a cutoff frequency of 25 kHz. A capacitance of
2 μF was calculated and implemented with two parallel 1 μF
film capacitors.
C. SiC Multichip Power Module Packaging
The packaging of SiC power devices intended for operation
at high temperatures requires many unique and challenging con-
siderations [25]–[27]. To address these concerns and to take full
advantage of the many benefits offered by SiC devices, a cus-
tom full-bridge power module was designed by APEI, Inc. The
prototype MCPM (dubbed the X-5) is shown in Fig. 4 along

Fig. 4. APEI, Inc., X-5 full-bridge MCPM with accompanying gate driver.
TABLE III
FUNCTIONAL SPECIFICATIONS OF THE X-5 POWER MODULE
with a U.S. quarter dollar to provide a sense of scale of this
high-density design.
The ground-up design of the X-5 power module started with
the selection of the power devices. A survey of commercially
available SiC power devices was conducted and the Cree CPMF-
1200-S080B MOSFET (1200 V, 20 A) and the Cree CPW4-
1200-S020B (1200 V, 20 A) Schottky diode were determined
to be the best candidates. The number of parallel devices used
in each switching position was then optimized through calcu-
lation and simulation. Next, a metal-matrix composite base-
plate material was selected. A metal-matrix composite offers
a high thermal conductivity and low CTE, which allows for
reliable operation at temperatures in excess of 200 ◦
C. In ad-
dition, the baseplate is very light weight while also having the
structural integrity to allow for direct mounting to a heat sink.
A direct-bond copper (DBC) power substrate and integrated
bus-board were designed with the focus placed on minimiza-
tion of parasitic inductance, capacitance, and high-frequency
ac resistance. High temperature ceramic decoupling capacitors
with good high-frequency performance were mounted directly
on the bus-board to further minimize the inductance in the high-
frequency switching loop and allow for efficient operation with
very little voltage overshoot at high switching frequencies. A
Class 1 dielectric was chosen to provide low effective series
resistance (ESR) and stable capacitance at high temperatures.
A more thorough review of the X-5 module design and charac-
terization are given in [27] and performance specifications are
shown in Table III. It should be noted that the voltage rating of
the module is limited to 600 V only due to the on-board decou-
pling capacitors. Alternative capacitors can be utilized to extend
the voltage rating to 1200 V.
Fig. 5. High-density on-board charger packaging with key components
identified.
D. On-Board Charger Packaging
A conscious effort was made to simultaneously optimize elec-
trical performance, minimize volume, and reduce thermal man-
agement requirements. Power stage components were grouped
in a way to minimize the required power bussing among com-
ponents to reduce bus bar impedance and weight. Three X-5
power modules, each with different device configurations,
were utilized for the system. Module 1 contained two parallel
MOSFETs and one antiparallel Schottky diode per position for
the two lower quadrants (corresponding to switches S3 and S4)
and a single Schottky diode per position for the two high side
quadrants. Module 2 contained two parallel MOSFETs and one
antiparallel Schottky diode in all four quadrants and Module
3 utilized a single Schottky diode in all four quadrants. A heat
sink was chosen to provide optimal heat transfer from the power
stages and magnetics to the ambient environment under minimal
airflow conditions. The heat sink was designed to span the base
of the entire system to maximize heat spreading. Additionally,
the power modules and all of the magnetic components of the
power stage are mounted directly to the heat sink via a thermal
interface material to improve thermal conductivity. A stacked
approach using board-to-board headers was utilized for the gate
driver and control boards. The control board itself was designed
such that large components could fill the voids between board
layers to achieve maximum system density. A rendering of the
system package that highlights individual component placement
is shown in Fig. 5.
A breakdown of the mass and volume of the system is given in
Fig. 6. The magnetics (inductors and transformer) add the most
mass to the system, but they only represent the third largest vol-
ume. The dc-link capacitors provide the second most mass as
well as the second highest overall volume. The heat sink repre-
sents the third largest mass and the largest overall volume using
a rectangular solid approximation. These three components rep-
resent 79% of the total mass and 70% of the total volume of the
system. Because of this, technological advancement for these
three areas should be targeted to further reduce system volume
and weight.

Fig. 6. Breakdown of system components for (a) mass considerations and
(b) volume considerations.
Fig. 7. Full charger system hardware shown with case.
V. EXPERIMENTAL RESULTS
The experimental prototype shown in Fig. 7 was built and
tested to verify proper operation. The first and second power
stages were initially tested independently and optimized for
maximum efficiency. The two stages were then cascaded and
tested as a fully-integrated charger system. A summary of the
power stage components used for the full system is given in Ta-
ble IV. The efficiency measurements, as well as total harmonic
distortion (THD) and power factor, were made with a Voltech
PM6000 power analyser with a 40 MHz sampling rate.
A. First-Stage AC–DC Converter Testing
The bridgeless boost ac–dc converter was first evaluated by
operating it as a simple dc–dc boost converter. This was accom-
plished by modulating MOSFET S3 while holding S4 on and
applying a dc voltage to the input in place of the ac grid voltage.
This mode emulates the normal operation of the ac–dc converter
TABLE IV
SUMMARY OF POWER STAGE COMPONENTS
Fig. 8. Waveforms of the ac–dc power stage when operated with a dc input
and fixed duty cycles with Vin = 240 V, Iin = 20 A, and Vdc = 350 V: (a) S3
turn-on event and (b) S3 turn-off event.
during a positive half-cycle of the grid voltage where only S3 is
modulated and S4 is conducting as shown in Fig. 2. The main
difference in this case is that the input is now dc and not sinu-
soidal. This operating mode is intended only for evaluating the
performance of the power stage and the primary advantage is
that it can be operated with constant duty cycles. The converter
was operated with a dc input voltage of 240 V and the duty
cycle was set to boost to a dc-bus voltage of 350 V. The turn-on
and turn-off transients of the drain-to-source voltage of S3 are
shown in Fig. 8(a) and (b), respectively. A plot of the vds3 rise
and fall times versus inductor current is shown in Fig. 9.
The efficiency of the ac–dc power stage was then evaluated
using the test setup with a dc input voltage as described in
the previous paragraph. This allows for the efficiency to be
optimized around one operating point for the input voltage and

Fig. 9. Device S3 drain-to-source voltage rise times (10%–90%) and fall times
(90%–10%) versus input current with Vin = 240 V and Vdc = 350 V.
Fig. 10. Efficiency versus output power at various switching frequencies for
the ac–dc power stage when operated with a dc input and fixed duty cycles for
Vin = 264 V and Vdc = 350 V.
the dc-link voltage. Setting the input to a dc value of 264 V
approximates grid tied operation with a 264 Vrms input. The
efficiency measured in this manner will be higher than for grid
tied operated because there is no ripple on the dc-bus when a dc
input is applied. However, it is assumed that this operating mode
will provide a rough approximation for the efficiency during grid
tied operation because the switching loss and conduction loss
will be similar. Using this method, a peak efficiency of 98.1%
was found with the target switching frequency of 250 kHz.
This exceeds the goal of 98% for this stage. The switching
frequency was then varied while keeping the same hardware
setup to determine the operational limits of the power stage.
The peak efficiency when operating at 500 kHz was found to
be 97.6% however the increased switching loss reduced the
efficiency more significantly at power levels below 2 kW. The
efficiency curves for various switching frequencies are shown
in Fig. 10.
Fig. 11. Operation of PSFB converter showing (a) ZVS of the leading leg and
partial soft-switching of the lagging leg with a low resonant inductor current
and (b) ZVS for both legs at a higher resonant inductor current.
B. Second-Stage DC–DC Converter Testing
The PSFB converter was tested using a dc power supply
on the input and loaded with a resistive load bank. The con-
verter was first tested to verify proper ZVS operation. ZVS for
the leading leg and partial soft-switching for the lagging leg is
shown in Fig. 11(a) with a low resonant inductor current. ZVS
is achieved for the leading and lagging legs in Fig. 11(b) with
a higher resonant inductor current. This demonstrates how op-
erating conditions have a large impact on ZVS operation of the
lagging leg and a significantly lesser impact on ZVS operation
of the leading leg.
The efficiency of the PSFB converter was then tested by ap-
plying a dc input voltage and a resistive load. The power level
was swept by increasing the load and adjusting the phase shift

Fig. 12. Efficiency versus output power for the PSFB converter at various
switching frequencies for Vdc = 350 V and Vo = 400 V.
to account for the effective duty cycle loss and maintain a con-
stant output voltage. The peak efficiency at the target switching
frequency of 500 kHz was found to be 93.9% with Vdc equal
to 350 V and an output voltage of 400 V. This efficiency at
this operation point was below the goal of 96% and required
the investigation of power stage performance at lower frequen-
cies. Reducing the switching frequency for this converter trades
device switching loss and ac-resistance loss for additional mag-
netics core loss and higher current ripple. Additionally, ZVS
operation of the lagging leg is impaired at lower frequencies
because the output current becomes discontinuous. The switch-
ing frequency was swept down to 200 kHz but not taken any
lower to avoid saturation of the transformer. Overall, a large
improvement in efficiency was observed by operating at a lower
switching frequency. The highest overall peak efficiency was
found at a switching frequency of 200 kHz where it was mea-
sured to be 96.5%, which exceeds the design target. The experi-
mentally measured efficiencies at various switching frequencies
are summarized in Fig. 12.
C. Full Charger System
Closed-loop control was added and the two converters were
cascaded to form the full charger system. The input was grid-
tied with an isolation transformer to protect the measurement
equipment and the output was resistively loaded. The PSFB con-
verter was operated at 200 kHz because this operating condition
resulted in the highest peak efficiency. The ac–dc converter was
also operated at 200 kHz in order to synchronize the ADC sam-
pling and pulsewidth modulated (PWM) gating signals in the
controller even though that stage met the efficiency target at
250 kHz. The input voltage and current, dc-bus voltage, and
output current waveforms are shown in Fig. 13 for an output
power of 3.1 kW. The input current is slightly distorted around
line voltage zero crossings; however, there is very little switch-
ing ripple and the current THD was measured to be 4.6%. The
input current is also well synchronized with the input voltage
and a power factor of 0.996 was measured. The harmonic con-
Fig. 13. Input and output waveforms of the two-stage charger system with
vin = 232 Vrm s , iin = 14 Arm s , Io = 9 Arm s , Vdc = 359 Vrm s , and a
resistive load of 40 Ω on the output.
Fig. 14. Comparison of EN 61000-E-2 harmonic current limits to the proposed
charger input current with vin = 232 Vrm s and iin = 14 Arm s .
tent of the input current was extrapolated from the input current
waveform and the results are compared to the EN 61000-3-2
Class A limits in Fig. 14. The current amplitude at the funda-
mental frequency is 19.9 Apeak, however this isn’t shown in the
figure because the y-axis has been scaled to 2.5 A for the sake
of legibility. The charger meets the standard for the lower order
harmonics however it exceeds the limits for a few higher order
harmonics such as the 15th harmonic.
The resistive load was increased and the output voltage was
held at 400 V to evaluate the efficiency of the system at various
power levels. The efficiency versus output power results are
shown in Fig. 15 for an input voltage of 240 Vrms. The system
was tested up to a peak power of 6.1 kW where the target system
efficiency of 94% was achieved. An overall peak efficiency of
95% was measured at an output power of 3.1 kW. The efficiency
drops off significantly at lower power levels; however, it’s still
greater than 91.5% at an output power of 1.3 kW.

Fig. 15. Efficiency versus output power for the two-stage charger system with
vin = 240 Vrm s , Vout = 400 V, and both power stages switching at 200 kHz.
Fig. 16. Loss distribution for full charger system at an output power of 3.1 kW
with vin = 240 Vrm s , Vout = 400 V, and both power stages switching at
200 kHz.
The distribution of power stage losses was calculated for
the system when operating under the conditions that gave the
maximum efficiency. The diode bridge in module 3 was found to
be the most lossy due to the forward voltage drop of the diodes.
The hard-switching devices in module 1 were the second largest
contributor to loss followed by the isolation transformer. It was
found that the three inductors combined contribute only 6% of
the total system losses. The loss breakdown is shown in Fig. 16
for the 3.1 kW operating point.
The peak power level of 6.1 kW results in a volumetric power
density of 5.0 kW/L, which exceeds the design target. The re-
sulting gravimetric power density is 3.8 kW/L and is within 15%
of the original target. The prototype’s key performance metrics
are summarized in Table V.
VI. CONCLUSION
This work presented a SiC-based high-efficiency, high-
density, on-board battery charging system for future application
in EVs and PHEVs. The operation and design of each converter
TABLE V
PROTOTYPE CHARGER PERFORMANCE SUMMARY
for this two-stage system was described in detail. Additional de-
tails on the packaging of the MCPM and the overall system were
discussed. A prototype was developed and testing results show-
case the functionality of the design. The peak system efficiency
of 95% and a maximum output power of 6.06 kW both exceed
the initial design specifications. The final prototype volumetric
power density of 5.0 kW/L and gravimetric power density of
3.8 kW/kg represent a more than 10× improvement in current
technology used in the 2010 model Toyota Prius Plug-in Hybrid
and a more than 5× improvement in DOE targets for the year
2022. These results clearly demonstrate the potential improve-
ments in system performance and miniaturization that can be
achieved through the use of SiC power devices.
ACKNOWLEDGMENT
The authors would like to acknowledge Toyota Motor En-
gineering and Manufacturing North America for their involve-
ment and support in the development of this charger for the next
generation of Toyota plug-in hybrid EVs.
The information, data, or work presented herein was funded
in part by an agency of the United States Government. Neither
the United States Government nor any agency thereof, nor any
of their employees, makes any warranty, express or implied,
or assumes any legal liability or responsibility for the accuracy,
completeness, or usefulness of any information, apparatus, prod-
uct, or process disclosed, or represents that its use would not
infringe privately owned rights. Reference herein to any specific
commercial product, process, or service by trade name, trade-
mark, manufacturer, or otherwise does not necessarily constitute
or imply its endorsement, recommendation, or favoring by the
United States Government or any agency thereof. The views and
opinions of authors expressed herein do not necessarily state or
reflect those of the United States Government or any agency
thereof.
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Bret Whitaker (S’08–M’13) received the B.S. de-
gree from the University of Arkansas, Fayetteville,
AR, USA, and the M.S. degree from Virginia Poly-
technic Institute and State University (Virginia Tech),
Blacksburg, VA, USA, in 2008 and 2010, respec-
tively, both in electrical engineering.
From 2008 to 2011, he was a Research Assistant at
the Future Energy Electronics Center, Virginia Tech.
In 2011, he joined Arkansas Power Electronics Inter-
national (APEI), Inc., Fayetteville, USA, as a Design
Engineer. His current research interests include the
development of wide-bandgap power electronics for on-board vehicle battery
charging applications, single-phase and three-phase inverters, soft-switching
converters, energy storage systems, and power electronics for renewable energy
applications.
Adam Barkley (S’07–M’11) received the B.S. and
Ph.D. degrees in electrical engineering from the Uni-
versity of South Carolina, Columbia, SC, USA, in
2005 and 2010, respectively.
Dr. Barkley is currently a Senior Power Electronics
R&D Engineer at Arkansas Power Electronics Inter-
national (APEI), Inc., Fayetteville, AR, USA, where
he is involved the complete design (i.e., electrical
design, simulation, layout, fabrication and prototyp-
ing) of various power electronics systems as well as
general technical and programmatic duties. He has
authored or coauthored over ten publications in various refereed journals and
conference proceedings on power electronics and industry applications.
Zach Cole received the B.S. degree in physics from
Northeastern State University, Tahlequah, OK, USA,
in 2003.
From 2005 to 2010, he was a Process Engineer at
Axept where he produced and packaged high relia-
bility MEMS pressure sensors. In 2010, he joined
Arkansas Power Electronics International (APEI),
Inc., Fayetteville, AR, USA, as a Design Engineer.
His current research interests include development
of wide-bandgap power electronics for on-board ve-
hicle battery charging applications and high voltage
power modules. He is currently involved in high-performance multichip power
modules for electric vehicles and novel packaging strategies for wide-bandgap
power electronics.

Brandon Passmore (M’02) received the B.S. degree
in engineering with an emphasis in electrical engi-
neering from Arkansas State University, Jonesboro,
AR, USA, in 2003, the M.S. and the Ph.D. degrees,
both in microelectronics and photonics, from the Uni-
versity of Arkansas, Fayetteville, AR, USA, in 2005
and 2008, respectively.
He was a Postdoctoral Researcher at Sandia Na-
tional Laboratories where he was involved in devel-
oping novel plasmonic- and metamaterial-based pho-
tonic devices for mid-IR applications. He is currently
a Senior Electronics Packaging Engineer at APEI, Inc. where he is the elec-
tronics packaging team leader. He has accumulated over twenty-five refereed
conference and journal publications. At Arkansas Power Electronics Interna-
tional (APEI), Inc., Fayetteville, USA, he is currently involved in a number
of projects, which include developing new wire bondless technologies, a high-
frequency, high temperature wide bandgap MCPM for electric vehicles, high
voltage SiC power packages, and a high-frequency discrete package for a GaN
power HEMT.
Daniel Martin (S’08–M’13) was born in Seoul,
South Korea, in 1986. He received the B.S. and Ph.D.
degrees in electrical engineering from the University
of South Carolina, Columbia, SC, USA, in 2008 and
2012, respectively.
He is currently a Senior Power Electronics
Engineer at Arkansas Power Electronics Interna-
tional (APEI), Inc., Fayetteville, AR, USA, where
he specializes in high-performance wide bandgap
semiconductor-based power converters and high
speed digital controls.
Ty R. McNutt (S’01–M’04) received the Bachelor’s
degree in physics (with distinction) from Hendrix
College, Conway, AR, USA, in 1998, and the M.S.
and Ph.D. degrees in electrical engineering from the
University of Arkansas, Fayetteville, AR, USA, in
2001 and 2004, respectively. His M.S. work focused
on the development of thermal-based data isola-
tion techniques in silicon-on-insulator (SOI) CMOS
for systems-on-a-chip applications, followed by his
Ph.D. work focusing on the characterization and mod-
eling of silicon carbide (SiC) power devices.
He was involved in the development and advancement of wide bandgap tech-
nology. He began his career as a Guest Researcher with the National Institute
of Standards and Technology (NIST) developing advanced SiC power device
models and characterization methods for high-voltage devices. Subsequently,
he was with the Advanced Materials and Semiconductor Device Technology
Center, Northrop Grumman Corporation, Linthicum, MD, where he was in-
volved in designing of high-power SiC and gallium nitride (GaN) devices to
provide performance advantages, such as drastic size and weight savings for
military systems. He then moved to Program Manager with the Advanced Con-
cepts and Technologies Division at Northrop Grumman Corporation, where he
managed a variety of advanced semiconductor programs from materials de-
velopment through device demonstration, in areas such as radiation detection,
power electronics, pulsed power, and microwave devices. He is currently the
Director of Business Development at Arkansas Power Electronics International
(APEI), Inc., Fayetteville, USA. He is a Senior Technical Advisor, Program
Manager, and directs business development, marketing, and sales. He has au-
thored or coauthored more than 60 papers published in various refereed journals
and conference proceedings and holds six patents.
Alexander B. Lostetter (M’89) received the B.S. and
M.S. degrees in electrical engineering from Virginia
Polytechnic Institute and State University, VA, USA,
in 1996 and 1998, respectively, and the Ph.D. degree
in microelectronics from the University of Arkansas,
Fayetteville, AR, USA, in 2003.
He is the President-CEO and Majority Owner
of Arkansas Power Electronics International (APEI),
Inc., Fayetteville, AR, USA. He has authored or coau-
thored over 75 articles and journal papers in the area
of power electronics systems, design, miniaturiza-
tion, and packaging, including two textbook chapters. He has been the prime
investigator or Co-PI on federal, state, and commercial awarded R&D contracts
totaling in excess of $25 million, and he has more than a dozen patent filings
in power electronics and silicon carbide systems. Dr. Lostetter was the PI for
work leading to an international R&D100 Award, in which APEI, Inc.’s “High
Temperature Silicon Carbide Power Modules” was selected as one of the top
100 new technology breakthroughs in the world in 2009 by the international
community and R&D Magazine.
Dr. Lostetter has been recognized as a leader in the engineering and busi-
ness community on a number of occasions, including the 2006 University of
Arkansas Young Engineering Alumni Award, the Top 10 Under 40 Arkansas
Business Leader of the Decade Award by the Arkansas Business Journal in
2006, and winner of the SBA’s Arkansas Small Business Person of the Year in
2012.
Jae Seung Lee received the M.S. and Ph.D. degrees
in electrical and computer engineering from the Uni-
versity of California Davis, CA, USA, in 2004 and
2005, respectively.
From 2004 to 2006, he was with Meggitt Safety
System, Simi Valley, CA, USA. During this period,
he was a Senior Product Engineer with microwave
components for military and commercial aircraft ap-
plication. From 2006 to 2007, he became a Senior
RF Engineer in Advanced Energy Industries, Inc.,
Fort Collins, CO, where he developed an advanced
sensing system for extremely stable 3–5 kW RF power source. Since 2007,
he has been with Toyota Technical Center Ann Arbor, MI, USA. In 2008, he
built a nondestructive millimeter wave material characterization apparatus and
established a millimeter wave laboratory in Toyota Technical Center. He demon-
strated 77 GHz tunable metamaterial in silicon for the first time in the world. He
first introduced phased array technology for future automotive safety radar by
demonstrating fully electronically steering beam at 77 GHz. He currently leads
an ARPA-E awarded project of SiC high-power battery charger for PHEVs. He
also researches on wireless charging technology for EVs and PHEVs energy
transfer.
In 2012, his team awarded DOE VTP program on WPT with ORNL.
Koji Shiozaki received the B.S. in applied chemi-
cal engineering from Tokyo Institute of Technology,
Tokyo, Japan, in 1983.
From 1983 to 1988, he was with the Central Re-
search Laboratory, Sharp Co., Japan. During this
period, he was an Engineer for three-dimensional
stacked semiconductor device, the advanced research
project entrusted from MITI. From 1988 to 2008,
he had been with Toyota Motor Co., Japan, and
participated in automotive semiconductor develop-
ments, such as CMOS, SOI-BiCDMOS, IGBT, SiGe-
BiCMOS, etc. Since 2008, he has been with Toyota Technical Center, Ann Arbor,
MI, where he was involved in the start-up of Toyota Research Institute of North
America. He has been involved in the establishment and management of phased
array radar project, advanced cooling projects for PHV/EV, SiC high-power
battery charger project awarded from DOE ARPA-E, vehicle wireless charging
technology awarded from DOE VTP, etc.
Dr. Shiozaki’s team was awarded the 2013 R&D 100 Awards on Multi-Pass
Branching Microchannel Cold Plate in 2013.

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