A generalized multilevel inverter topology with reduction of total standing voltage

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This paper presents a new multilevel inverter topology with reduced active switches and total standing voltage. The proposed topology can generate a high number of voltage levels in the symmetric configuration. This topology intuitively generates positive and negative cycles without an additional H-bridge unit, which considerably reduces the total standing voltage of the inverter. A cascaded structure is developed from the proposed topology to create higher voltage levels. To show the novelty of the proposed topology, a thorough comparison between the available and the proposed topologies in terms of the number of switches, standing voltages, and dc-sources is presented. Furthermore, he power loss analysis is carried out for various load values. The feasibility of the proposed nine-level inverter is verified with simulation and experimental results.

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A Generalized Multilevel Inverter Topology with Reduction
of Total Standing Voltage
ABSTRACT:
This paper presents a new multilevel inverter topology with reduced active switches
and total standing voltage. The proposed topology can generate a high number of voltage levels
in the symmetric configuration. This topology intuitively generates positive and negative cycles
without an additional H-bridge unit, which considerably reduces the total standing voltage of the
inverter. A cascaded structure is developed from the proposed topology to create higher voltage
levels. To show the novelty of the proposed topology, a thorough comparison between the
available and the proposed topologies in terms of the number of switches, standing voltages, and
dc-sources is presented. Furthermore, he power loss analysis is carried out for various load
values. The feasibility of the proposed nine-level inverter is verified with simulation and
experimental results.
KEYWORDS:
1. Multilevel inverter
2. Inverter
3. Blocking voltage
4. Cascaded structure
5. Reduced power components
SOFTWARE: MATLAB/SIMULINK

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