This profile summarizes the experience of an experienced hardware engineer with skills in silicon and pre-silicon debug, validation planning, technical team leading, x86 CPU and system architecture knowledge, and excellent communication skills. The engineer has over 15 years of experience at AMD and Apple debugging GPUs and CPUs, developing validation plans, leading cross-functional teams, and analyzing silicon failures. Education includes an MS in Computer and Systems Engineering and a BTech in Electronics and Communication Engineering.
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
Working in teams is more effective than individual work, But the main obstacle that any corporate faces is the synchronization between each team, One of the functions that is affected by this obstacle is 'Coding', Working on massive and multidisciplinary projects which need the contribution of several teams specially at the coding phase is opposed by the miss coordination when running the mother code.
So corporate developed some tools to overcome this situation using code version control and Tracker System.
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
Working in teams is more effective than individual work, But the main obstacle that any corporate faces is the synchronization between each team, One of the functions that is affected by this obstacle is 'Coding', Working on massive and multidisciplinary projects which need the contribution of several teams specially at the coding phase is opposed by the miss coordination when running the mother code.
So corporate developed some tools to overcome this situation using code version control and Tracker System.
On the verification of configurable nocs in simulation and hardware emulation...Sameh El-Ashry
This research aims is to propose configurable verification tool-based user scripts based UVM methodology, which are implemented by the author.
Extracting the verification requirements and proposing a novel UVM verification architecture.
By proposing UVM architecture to verify the 2D/3D NOCs with different network topologies, routing algorithms and flow control methodologies.
The architecture supports simulation and hardware emulation platforms.
Simulate/Emulate the configurable verification tool with a Network on Chip Designs.
Introduction to SOC Verification Fundamentals and System Verilog language coding. Explains concepts on Functional Verification methodologies used in industry like OVM, UVM
How to create SystemVerilog verification environment?Sameh El-Ashry
Basic knowledge for the verification engineer to learn the art of creating SystemVerilog verification environment.
Starting from the specifications extraction till coverage closure.
Advances in Verification - Workshop at BMS College of EngineeringRamdas Mozhikunnath
Day 1 of workshop at BMS college of Engineering
Covers SystemVerilog language fundamentals - Language constructs, building blocks, Arrays, Process, Classes
This presentation is about applying test automation to embedded devices. It also contains recommendations on how to handle specific features of embedded devices, such as their “True Real Time” type, a non-PC platforms and absence of a debug port.
Presentation by Yuriy Kozak (Consultant Software Engineer, GlobalLogic, Lviv) and Ihor Semochko (Automation Engineer, GlobalLogic, Lviv), EmbeddedTechTalk, Lviv, 2014.
More details -
http://www.globallogic.com.ua/press-releases/embedded-lviv-techtalk-2-coverage
Embitel’s VLSI team has rich experience in design and validation of complex digital designs, FPGA design services, ASIC design service, chip design and verification, IP Development and SoCs across UK, Germany, France, Sweden, Finland and Netherlands.
On the verification of configurable nocs in simulation and hardware emulation...Sameh El-Ashry
This research aims is to propose configurable verification tool-based user scripts based UVM methodology, which are implemented by the author.
Extracting the verification requirements and proposing a novel UVM verification architecture.
By proposing UVM architecture to verify the 2D/3D NOCs with different network topologies, routing algorithms and flow control methodologies.
The architecture supports simulation and hardware emulation platforms.
Simulate/Emulate the configurable verification tool with a Network on Chip Designs.
Introduction to SOC Verification Fundamentals and System Verilog language coding. Explains concepts on Functional Verification methodologies used in industry like OVM, UVM
How to create SystemVerilog verification environment?Sameh El-Ashry
Basic knowledge for the verification engineer to learn the art of creating SystemVerilog verification environment.
Starting from the specifications extraction till coverage closure.
Advances in Verification - Workshop at BMS College of EngineeringRamdas Mozhikunnath
Day 1 of workshop at BMS college of Engineering
Covers SystemVerilog language fundamentals - Language constructs, building blocks, Arrays, Process, Classes
This presentation is about applying test automation to embedded devices. It also contains recommendations on how to handle specific features of embedded devices, such as their “True Real Time” type, a non-PC platforms and absence of a debug port.
Presentation by Yuriy Kozak (Consultant Software Engineer, GlobalLogic, Lviv) and Ihor Semochko (Automation Engineer, GlobalLogic, Lviv), EmbeddedTechTalk, Lviv, 2014.
More details -
http://www.globallogic.com.ua/press-releases/embedded-lviv-techtalk-2-coverage
Embitel’s VLSI team has rich experience in design and validation of complex digital designs, FPGA design services, ASIC design service, chip design and verification, IP Development and SoCs across UK, Germany, France, Sweden, Finland and Netherlands.
1. Profile Summary
Experienced hardware engineer with good analytical abilities and cross functional experience; post
silicon processorvalidation team lead, CPU&GPU silicon debug, pre-silicon verification, RTL IP
partner support,processorscan analysis,scripting, x86 processorand systemarchitecture,
documentation.
Core Qualifications
* Silicon and pre silicon debug skills
* Validation planning
* technical team lead
* Knowledge of x86 CPU and System architecture
* Excellent written and verbal communication skills
* Adept working in cross-functional teams
Experience
GPU HARDWARE ENGINEER, APPLE, AUSTIN, TX — JAN,2014 - APR,2016
* Debug GPU failures from software applications and validation tests on Apple’s mobile processors
* collate known design issues (ECO & non ECO issues at tape out) prior to silicon arrival, plan and
code necessary scripts to triage silicon issues from processorSCANs, drive debug to root cause
* reproduce silicon failures in RTL/gate simulations or in emulations (Palladium)
MEMBER OF TECHNICAL STAFF, AMD, AUSTIN, TX — JAN/2013 - DEC/2013
* verify CPU to System Traffic (I/O, memory buffer, interrupt, debug logic) routing in x86
processors
* develop test plan, OVM/UVM sequences,test bench components and functional coverage model
for Design For Debug block (Debug State Machine)
* achieve functional coverage goals for Debug block by processortape out
MTS, PRE-SILICON VALIDATION, AMD, AUSTIN, TX APR/2011 - DEC/2012
* prepare and compile RTL blocks for emulation (Palladium), bring up emulation through Reset
* support validation of BIOS, OS boot process and diagnostic tools on Emulator
* plan emulation testing to optimize the use of limited emulation resources
MTS, SILICON VALIDATION ARCHITECT, AMD, AUSTIN, TX DEC/2009-APR/2011
Manoj Panicker
Ph 512-775-2972 mnjpanicker@gmail.com 9928 Wading Pool Path, Austin,TX 78748
2. * produce validation plan for processor’s System Interface, do technical scoping and improve
validation process
* lead a cross functional team of engineers to produce validation plans, lead the validation of Hyper
Transport system interface and L3 cache applying random tests and on chip traffic stallers
* enable the use of on chip debug features for silicon Validation; demonstrated new use cases of on-
chip debug logic, trained engineers
MTS, VERIFICATION, AMD, AUSTIN, TX FEB/2009 - NOV/2009
* plan and verify Debug State Machine; System Verilog/OVM/UVM
MTS, VERIFICATION & SILICON VALIDATION, AMD, AUSTIN, TX JAN/2006 - FEB/2009
* CPU verification of x86 processors; develop directed and random tests to verify CPU -System
Traffic (Hyper Transport I/O bus,CPU to memory traffic, interrupt messaging)
* early silicon validation of x86 processors; triage and debug silicon issues,run silicon and
simulation experiments for failure analysis
* architected a tool that rendered gates’scan data in RTL representation, co-developed the tool in
(perl/C++), the tool reduced debug time and was adopted by all silicon debug teams
* train Verification engineers to analyze silicon failure data
PRODUCT DEVELOPMENT/SENIOR VERIFICATION ENGINEER AMD, AUSTIN AUG/1998– DEC/2005
* verification of x86 embedded processors and chipsets
* develop directed tests (Verilog, x86 assembly), random tests and test bench components in Verilog
and C++
* support System engineers with triage of silicon failures
* root cause silicon bugs
* develop test bench and Hyper Transport bus functional model to support AMD’s Hyper Transport
partner companies
Education
3. University of Houston, Houston
MS Computer and Systems engineering, 1998 : Microprocessors, Computer Arch, Digital Design,
Control Systems
Govt. Engineering College, University of Calicut, India
B.Tech Electronics and Communication Engineering, 1995 : Analog&Digital Electronics, Computer
Arch, Communication Eng
Skills, Tools
* Verilog, System Verilog, Verdi, C++, x86 assembly, Perl, OVM, UVM
* revision control systems; RCS, CVS, Git
* Hyper Transport interconnect, PCIe, DDR, JTAG
* GPU, x86 CPU & System architecture
* Oscilloscope, Logic Analyzer
References
On request