1. 1June 2003
Design of a 17-million Gate
Network Processor
using a Design Factory
Satish Bagalkotkar Satish Iyengar
Methodology/ASIC Logic Design
Gilles-Eric Descamps Subramanian Ganesan Alain Pirson
Infrastructure Physical Design Design Verification
2. 2June 2003
Agenda
Control of timeline
– Five maturity phases
Control of execution
– Goals Definition, Data Capture - Qualification
– Logic Design, Verification
– IP core catalog
– Gates-to-GDSII flow
– Chip Integration / Bring-up
3. 3June 2003
Why did we need a “Factory” ?
Four complex SoC
Company growing by 500% across 3
campuses
Minimal employee ramp-up time
Limited resources
Target Performance (20Gb/s)
4. 4June 2003
Approach
Front-loaded methodology
Decoupling of different aspects of design
– RTL, verification, circuit, back-end, etc
– Each team has its own specific goals
Break down of the design timeline
– Five phases with entry and exit criteria
– Defined maturity for each phase
– Structured progress for monotonic convergence
Early detection of problems requiring trade-offs
7. 7June 2003
Monotonic Convergence
Controlled releases from FE to BE
based on predefined quality metrics
floorplan place route signoff chip
tasks
time
BE HR
BE B3
BE B2
BE B1
BE B0
floodgatefloodgatefloodgate
FE B0
FE B1
FE B2
FE B3
8. 8June 2003
Base 0 / Floorplan
Focus
– Top level chip floor-planning (black-box model)
– Block area and timing budgets
– Feasibility studies (power, clock etc.)
– Performance analysis
Entry Criteria
– RTL 33% coded
– Verification setup completed
Exit Criteria
– FE: 75% RTL coded (90% of these paths meet synthesis timing)
– Verification: 33% of design qualified
– BE: Block sizes and pin assignment
(*) Similar criteria for circuit design, software…
9. 9June 2003
Base 1 / Synthesis
Focus
– Synthesis to meet budgets
– RTL completion
– Block floorplan & placement based timing
Entry Criteria
– 75% functionality coded
– Verification: 33% of tests passing
– 90% of paths meet synthesis timing budget
Exit Criteria
– FE: 95% RTL coded
– Verification: 90% of tests passing
– BE: placement based timing meets within 10%
11. 11June 2003
Base 3 / Timing Closure
Focus
– Post-route timing closure (no violations)
– Close Physical Design of all blocks
– Extensive random testing for corner cases
Entry Criteria
– 100% functionality tested
– All known bugs fixed
– Freeze libraries, tool versions etc.
Exit Criteria
– FE: primarily bug fixes as they arise
• Migrate team members to other activity
– BE: all blocks tapeout ready
12. 12June 2003
Home Run / Tapeout
Focus
– Chip Integration & Verification
– Last minute ECO fixes
– Tapeout !
Entry Criteria
– All blocks are DRC/LVS clean
– Blocks meet all requirements (timing, clock, power etc)
Exit Criteria
– FE: 2 weeks of random testing with no bugs.
– BE: Release GDSII to Foundry
19. 19June 2003
Physical Design Flow
One-Button Gates-to-GDSII block flow
Best of Breed 15+ tools, 60+ steps
Single color-coded GUI
4 exit points – floorplan, place, route,
signoff
Data & results captured, qualified and
published on a web page
21. 21June 2003
Correct-by-construction approach
Top-level Clock H-trees
– Using tunable buffers to reach a 5ps skew
Noise avoidance and correction
Custom-designed power grid
Length based buffer insertion at top-level
Margin based timing closure
Area growth prediction
