This document discusses potential applications of memristor crossbar arrays. It begins by outlining desirable manufacturing goals for memristor crossbars, such as being compatible with standard techniques and materials. It then discusses two types of crossbar designs - nanowire vs microscale wire - and presents a design incorporating pn junctions. Several potential applications are described, including programmable drive waveforms, pattern recognition, field programmable analog arrays, arithmetic optimization problems, and signal mixing. Advantages of using crossbars for these applications include combining memory and processing, adaptability, and efficient solutions to problems not addressed by conventional hardware.
Memristors and their potential applications 2012Md Kafiul Islam
Memristor (Memory-Resistor) which is a 4th basic passive electrical circuit element after resistor, capacitor and inductor, initially proposed by Dr Leon Chua back in 1971, has a promising future in electronics. The potential applications of the use of memristor in different circuits, both analog and digital, have made researchers to think of this device in many applications. This is a literature review of some of the potential applications proposed by the researchers.
Memristors and their potential applications 2012Md Kafiul Islam
Memristor (Memory-Resistor) which is a 4th basic passive electrical circuit element after resistor, capacitor and inductor, initially proposed by Dr Leon Chua back in 1971, has a promising future in electronics. The potential applications of the use of memristor in different circuits, both analog and digital, have made researchers to think of this device in many applications. This is a literature review of some of the potential applications proposed by the researchers.
Every person with an electronics background will be familiar with the three fundamental circuit elements - the resistor, the capacitor, and the inductor. These three elements are defined by the relation between two of the four fundamental circuit variables -
current, voltage, charge and flux.
In 1971, Leon Chua reasoned on the grounds of symmetry that there should be a fourth fundamental circuit element which gives the relationship between flux and charge. He named this circuit element the memristor, which is short for memory resistor. In May 2008, researchers at HP Labs published a paper announcing a model for the physical realization of the memristor.
It is proposed that memory storage devices that has very high data density and computers that require no time for boot up can be developed using memristor based hardware. A new physical quantity which is also introduced associated with memristor. It also solves someunexplained voltage current characteristics observed in certain materials at atomic levels.
you can be friend with me on orkut
"mangalforyou@gmail.com" : i belive in sharing the knowledge so please send project reports ,seminar and ppt. to me .
Memristors are basically a fourth class of electrical circuit, joining the resistor, the capacitor, and the inductor, that exhibit their unique properties primarily at the nanoscale. Theoretically, Memristors, a concatenation of “memory resistors”, are a type of passive circuit elements that maintain a relationship between the time integrals of current and voltage across
a two terminal element. Thus, a memristors resistance varies according to a devices memristance function, allowing, via tiny read charges, access to a “history” of applied voltage. The material implementation of memristive effects can be determined in part by the presence of hysteresis (an accelerating rate of change as an object moves from one state to another) which, like many other non-linear “anomalies” in contemporary circuit theory, turns out to be less an anomaly than a fundamental property of passive circuitry.
Theoretically, Memristors, a concatenation of “memory resistors”, are a type of passive circuit elements that maintain a relationship between the time integrals of current and voltage across a two terminal element.
you can watch this Presentation from
https://www.youtube.com/watch?v=1LO0QPSk-L4&feature=youtu.be
*Contents:
1-What is Memristor?
2-Basic Operation
3-Why Memristor?
4-Memristor Fabrication
5- Memristor Modeling & Emulating
6-Applications of Memristors in
a) Memories
b) Logic and FPGA
c) Neural Networks
d) Analog circuits
Every person with an electronics background will be familiar with the three fundamental circuit elements - the resistor, the capacitor, and the inductor. These three elements are defined by the relation between two of the four fundamental circuit variables -
current, voltage, charge and flux.
In 1971, Leon Chua reasoned on the grounds of symmetry that there should be a fourth fundamental circuit element which gives the relationship between flux and charge. He named this circuit element the memristor, which is short for memory resistor. In May 2008, researchers at HP Labs published a paper announcing a model for the physical realization of the memristor.
It is proposed that memory storage devices that has very high data density and computers that require no time for boot up can be developed using memristor based hardware. A new physical quantity which is also introduced associated with memristor. It also solves someunexplained voltage current characteristics observed in certain materials at atomic levels.
you can be friend with me on orkut
"mangalforyou@gmail.com" : i belive in sharing the knowledge so please send project reports ,seminar and ppt. to me .
Memristors are basically a fourth class of electrical circuit, joining the resistor, the capacitor, and the inductor, that exhibit their unique properties primarily at the nanoscale. Theoretically, Memristors, a concatenation of “memory resistors”, are a type of passive circuit elements that maintain a relationship between the time integrals of current and voltage across
a two terminal element. Thus, a memristors resistance varies according to a devices memristance function, allowing, via tiny read charges, access to a “history” of applied voltage. The material implementation of memristive effects can be determined in part by the presence of hysteresis (an accelerating rate of change as an object moves from one state to another) which, like many other non-linear “anomalies” in contemporary circuit theory, turns out to be less an anomaly than a fundamental property of passive circuitry.
Theoretically, Memristors, a concatenation of “memory resistors”, are a type of passive circuit elements that maintain a relationship between the time integrals of current and voltage across a two terminal element.
you can watch this Presentation from
https://www.youtube.com/watch?v=1LO0QPSk-L4&feature=youtu.be
*Contents:
1-What is Memristor?
2-Basic Operation
3-Why Memristor?
4-Memristor Fabrication
5- Memristor Modeling & Emulating
6-Applications of Memristors in
a) Memories
b) Logic and FPGA
c) Neural Networks
d) Analog circuits
Field of telecommunications has evolved from crudest form of communications to electrical, radio and electro-optical communications. From manual exchange like local battery, central battery exchange, to crossbar switching, director system and to common control systems, telephone communications had started evolving to cater to better and better specifications and needs. Touch tone dial telephone opened a new horizon in the field of end to end signalling. Then came computerised stored program control systems, various multiplexing techniques. With increase in traffic there was a need to study traffic and blocking capabilities....
2011 Protection of a 3.3V Domain and Switchable 1.8V/3.3V I/O in 40nm and 28n...Sofics
2011 Japan RCJ symposium
Today’s advanced technologies’ overdrive transistors cannot always meet the signal speeds of existing standards. This paper describes the issues, solutions and results to build the necessary protection for HBM, MM, CDM and latch-up for a 3.3V domain and 1.8V/3.3V I/O, based only on 1.8V transistors, in a 40nm process. Results of the design ported to 28nm are also presented.
Design and performance analysis of low phase noise LC-voltage controlled osci...TELKOMNIKA JOURNAL
Voltage controlled oscillator (VCO) offers the radio frequency (RF) system designer a freedom to select the required frequency. Today’s wireless communication system imposes a very stringent requirement in terms of phase noise generated in VCO. This study presents an inductive source degeneration technique to improve the phase noise performance of the inductance-capacitance (LC)-VCO. Double cross-coupled topology has been chosen for the proposed VCO. The post layout simulations with the parasitic resistance, inductance, capacitance (RLC) extracted view is carried out with united microelectronics corporations (UMC) 0.18 µm process by spectre simulator of cadence tools. The proposed VCO provides a phase noise
of -124.3 dBc/Hz @ 1 MHz. The tuning range obtained is 19.87% with a centre frequency of 2.46 GHz which makes it suitable for industrial, scientific, and medical (ISM) band applications. It consumes a power of 2.10 mW. Also, a good figure of merit of -189 is achieved. The total layout area occupied is 477×545 µm2.
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1Javed G S, PhD
Topics covered in the course
1. DC Biasing of the circuits
2. Circuits for reference voltage and current generation
-Voltage Regulator
-BGR
-LDO
-V-to-I
3. Precision Current References
4. Opamp design for Analog to digital converters
- OTA
- Buffer
- Unity Feedback OTA
- Layout design strategies – 2stage opamp + CMFB
5. Sense and Return mechanisms in Feedback circuits
- Current and Voltage circuits
6. Sub-Threshold Conduction
- Low voltage Operation
7. ADC Design and Simulation
-Near Nyquist performance of Opamp for ADC Circuits
-Spectral Analysis and No. of FFT Points for simulation
-Simulation time for performance
-Resistors – their variation and Calibration
-Switch design for S/H
-CDAC
8. On-Chip Inductors
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
First order sigma delta modulator with low-power consumption implemented in a...eSAT Journals
Abstract
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits
Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is
necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS
technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and
the power consumption was 5.5 mW under ±1.5V supply voltage .
Index terms: Analog-to-Digital conversion, Delta-Sigma modulation, CMOS technology, Transconductance operational
amplifier.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An approach to design Flash Analog to Digital Converter for High Speed and Lo...VLSICS Design
This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...
Proposals for Memristor Crossbar Design and Applications
1. Proposals for Memristor Crossbar
Design and Applications
Memristors and Memristive Systems Symposium
UC Berkeley November 21, 2008
Blaise Mouttet
George Mason University
2. Desirable Manufacturing Goals to Ease
Adoption of Memristor Crossbars
• Design should be compatible with standard manufacturing
techniques to facilitate wide use and experimentation by
many participants (i.e. universities, research labs, existing
fabs, etc.) without a significant investment in new equipment.
• Design should be easy to integrate with standard electronics
components and materials.
• Design should incorporate materials capable of RHIGH>>RLOW.
• Design should be robust to both temporal and spatial
variation of memristance.
• Design should avoid internal feedback current paths in
crossbar which can limit speed and ability to read resistance
states reliably.
• Design should allow ease of reconfiguration of resistance
states.
3. Nanowire vs. Microscale Wire Crossbars
• Some applications may not require nanowires
to provide competitive solutions in a variety
of areas (e.g. signal processing, pattern
recognition)
• Near‐term implementation is likely to be
easier and more readily adopted using
microscale wires which can avoid the
problems of nanowire defects, addressing,
etc.
4. Ideally, the detected resistance state of a selected crossbar
junction should be independent of other resistance states in the
crossbar.
1 0 0 0
Vread
1
0
0
Low resistance
junction
(i.e. logic 1)
High resistance
junction
(i.e. logic 0)
5. However, this is not the case for simple crossbar designs due to
internal currents.
1 0 0 0
Vread
1
0
0
6. A simple solution compatible with microfabrication
techniques is the incorporation of pn junctions in the
crossbar (taught by Ovshinsky for phase change crossbar
memory in US Patent 4,597,162). One variation of this
solution adapted to bilayer oxide memristive films is as
follows:
A) Film deposition of metal layer and silicon layers
n‐doped polysilicon
p‐doped polysilicon
metal layer (e.g. Al)
SiO2
Silicon wafer
7. B) Etch metal and semiconductor layers to form crossbar columns.
SiO2
Silicon wafer
N
P
N
P
N
P
N
P
Al Al Al Al
8. C) Deposit SiO2 in gaps to provide isolation and planarize surface
D) Deposit memristor oxide bilayer (e.g. TiO2/TiO2‐x)
E) Deposit and pattern top metal layer to form crossbar row wires
Pt
SiO2 SiO2 SiO2
SiO2
Silicon wafer
N
P
N
P
N
P
N
P
Al Al Al Al
TiO2/TiO2‐x
9. Desirable Goals for Memristor
Crossbar Array Applications
• Complement (not conflicting with) existing
technologies and markets to achieve ease of
acceptance
• Identify uses compatible with smaller emerging
markets with potential for high growth (e.g.
FPAAs , commercial robotics, neural interfaces)
• Solve problems for which conventional electronic
hardware and software do not provide efficient
solutions but which memristors can (e.g. pattern
recognition, traveling salesman problem)
10. Op‐amps are well known to be
implemented as summing amplifiers
R1
_
+
RF
Vout = - [V1(RF/R1)+V2(RF/R2)+
V3(RF/R3)+V4(RF/R4)]
R2
R3
R4
V1
V2
V3
V4
12. For an ideal op‐amp:
=−Σ
F ij I I
ij
V V
( −
)
Σ +
= −
i loss
ij ij i
V
out
F
M R
R
( )
V R − = − −
= −Σ Σ
out V V T M V V
( ) ( )( )
F
( ) i loss
ij
ij
ij
i loss
M +
R
ij i
13. To achieve behavior similar to binary logic requires
T(Mij=RHIGH)=0 and T(Mij=RLOW)=1
By setting the fixed column resistors Ri = RF‐RLOW then T(RLOW)=1
is achievable. However, T(RHIGH) is not able to be zero since this
would require RF = 0. Thus a low bit error (LBE) exists and a
tolerable LBE should satisfy:
T(RHIGH)= LBE ≥ 1/[1+(RHIGH‐RLOW)/RF]
Solving for RF produces:
RF ≤ [LBE/(1‐LBE)] (RHIGH‐RLOW)
This inequality sets an upper limit to RF based on a maximum
allowable low bit error and the high and low resistance values of
the memristor.
14. Analysis for memristor (Mij) variation
For an allowable bit sensitivity σ(Mij),
R dM
F ij
ij M
d T M <σ
| ( ) | 2 ij
( )
M R
( +
)
ij i
=
The maximum allowable value of d|T(Mij)| is at Mij = RLOW
and for Ri = RF‐RLOW
dM
R dM
F ij M
( )
( )2 ij
F
ij
LOW F LOW
R
R R R
= <σ
+ −
15. Analysis for memristor (Mij) variation
Combining the previous conditions the optimum range for RF can
be determined based on the memristance sensitivity and low bit
error as:
R LBE
dM
ij R R
( )
( ) 1 F HIGH LOW
ij
LBE
M
−
−
< <
σ
16. Analysis for memristor (Mij) variation
A possible rule of thumb is to set the allowable low bit error and bit
sensitivity in terms of the number of columns of the crossbar (=N).
For example, if all of the crosspoints have a low bit error and sensitivity
of 1/N a total of 1 bit error is produced at the output. The range of RF
may then be expressed as:
NdM R N −
ij F HIGH LOW R R
( )
1/
1 1/
N
−
< <
17. Analysis for memristor (Mij) variation
For large N the above inequality can be approximated to find the
maximum allowable variation in Mij as:
dM RHIGH RLOW
( )
2
N
ij
−
<
In case of relaxing the maximum bit error and sensitivity constraints
to allow for n total bit errors for N columns the above equation
becomes:
2 ( )
dM n RHIGH RLOW
2
N
ij
−
<
19. Problems with Conventional Drive
Waveform Circuits
• In many electronics applications variation of circuit
parameters due to temperature change, aging, etc. require
adjustment of drive waveforms (e.g. LEDs may require a
higher amplitude voltage drive over time to produce a
consistent light output).
• Waveform adjustment is also desirable for mode adjustment
in various applications (e.g. inkjet printheads changing
resolution or drop size often involves timing or amplitude
adjustment of drive signal for heater or piezo.)
• Timing modulation and amplitude modulation circuits
implemented in hardware can require complex circuitry and
have limitations in adaptability and the range of possible
waveforms.
• Software based solutions require a microprocessor which can
be difficult/expensive to miniaturize for several portable
electronics applications
20. Memristor Crossbar Drive Waveform Circuit
Assuming RLOW of memristors << RF, R
1 0 0 0
_
+
RF
|Vout/Vin|≈
RF/R
R
2R
4R
8R
Voltage Level Converter
Shift Register
21. Memristor Crossbar Drive Waveform Circuit
Assuming RLOW of memristors << RF, R
0 1 0 0
_
+
RF
|Vout/Vin|≈
RF/2R
R
2R
4R
8R
Voltage Level Converter
Shift Register
22. Memristor Crossbar Drive Waveform Circuit
Assuming RLOW of memristors << RF, R
0 0 1 0
_
+
RF
|Vout/Vin|≈
RF/4R
R
2R
4R
8R
Voltage Level Converter
Shift Register
23. Memristor Crossbar Drive Waveform Circuit
Assuming RLOW of memristors << RF, R
0 0 0 1
_
+
RF
|Vout/Vin|≈
RF/8R
R
2R
4R
8R
Voltage Level Converter
Shift Register
24. Advantages
• Both timing and amplitude of output waveform
can be adjusted by binary switching of the
memristance states in the crossbar.
• Even with only binary memristance switching, a
very large number of possible drive waveforms
are available (2NxM) (e.g. 10x10Æ1030 states).
• Combined with techniques such as hill climbing
and genetic algorithms has potential for self‐optimizing
drive waveforms and real‐time
adaption of circuitry to effects of aging and
temperature variation.
26. Problems with Conventional Pattern
Recognition Solutions
• Software‐based solutions require time for data
transfer between memory and processor circuits
which causes a lag in responsiveness.
• Hardware solutions can be faster but have limits
in adaptability and limits in the range of patterns
that can be classified.
• Memristors offer a route to a “morphware”
pattern recognition solution combining both
memory storage and data processing in a
common circuit.
35. Advantages
• Output voltage from 1st op‐amp is analogous to
XNOR (bit comparator) function
out ij V = A ΣT M V −V +ΣT M V −V −V
2 ([ ( )( i loss ) ( ij
)( i loss )] ref
) i
i
• Tuning Vref can adjust sensitivity of pattern
comparison and adjust allowable bit error
between resistance states and voltage states.
• Allowing for bit error could potentially be very
useful to applications such as facial recognition
which can require robustness to a large
percentage of bit errors.
37. Problems with Conventional FPAAs
• FPAAs (Field Programmable Analog Arrays)
provide reconfigurability of filter designs useful in
communications and control systems but are
limited in the range of configurable states.
• Lacks ability to electrically tune the resistance
such as provided by memristors to achieve
intermediate frequency states (for
communication apps.) or pole/zero adjustment
(for control apps.)
38. By including memristor crossbar junctions in the input and feedback path of
an op‐amp capacitor array, a transfer function can be tuned to adjust the
gain, pole, and/or zero of a filter.
Memristance programming circuitry
M21 M22 M23 M24 M25
M11 M12 M13 M14 M15 Vout(t)
C
R1 C/2 C/4 C/8
Vin(t)
R2 C C/2 C/4 C/8
Vout(s)/Vin(s) = K(Mij) [1+s/a(Mij)]/[(1+s/b(Mij)]
a(Mij)<<b(Mij) Æ high pass filter
a(Mij>>b(Mij) Æ low pass filter
39. Advantages
• Conversion between low pass and high pass
filter by appropriate selection of on/off states
of Mij.
• Tuning of f‐3dB or pole/zero by adjustment of
memristance state.
• Cascading multiple stages can provide for
tunable bandpass adjustment
• Dynamic PID controllers can be implemented
by connecting multiple stages in parallel.
41. Problems with Conventional Arithmetic
Processor Designs
• Segmentation between memory and
processor circuitry may produce a bottleneck
in speed. New clock independent designs are
desirable.
• Logic based arithmetic is inefficient for some
network optimization problems such as the
traveling salesman problem involving
repeated recalculation of sums
42. Memristor Crossbar Arithmetic Circuit
Assuming RLOW of memristors << R/8
0 1 0 1
_
+
R
Vout
R
R/2
R/4
R/8
Voltage Level Converter
20
21
22
23
Analog output representative of 2+4
43. Memristor Crossbar Arithmetic Circuit
Assuming RLOW of memristors << R/8
1 0 1 0
_
+
R
Vout
R
R/2
R/4
R/8
Voltage Level Converter
20
21
22
23
Analog output representative of 1+3
44. Advantages
• Although op‐amps are slower than logic circuits the
combination of memory and processing in a single
circuit reduces the reliance on a clock.
• May be scalable to provide real time solutions to
network optimization. For example, in a traveling
salesman problem with 100 nodes including 5050
inter‐relational distances, each distance metric can be
stored in a different crossbar column. Comparisons
between different paths between the nodes only
requires changing the bit pattern input to the crossbar
rows and detecting the analog level of voltage output.
46. Problems with Conventional Modulation
Systems
• Increase in portable wireless electronics
requires more efficient uses of spectrum with
techniques such as frequency hopping.
• Simpler but more secure signal encryption
methods are desirable.
47. Back‐to‐back diode memristor crossbar
Silicon wafer
SiO2
Al
N
P
Pt
TiO2/TiO2‐x Pt Pt Pt Pt
SiO2 SiO2 SiO2
SiO2
Silicon wafer
P
N
P
N
P
N
P
N
Al Al Al Al
48. Equivalent circuit at each crossbar junction
VeqB = VinB [(Ri+Mij)/(Ri+Rj+Mij)]+
VinA[Rj/(Ri+Rj+Mij)]
For VinB less than the diode
threshold voltage, the
resistance state of Mij and
voltage state of VinA can be
used to modulate signal
transmission.
VoutA
VinB
VoutB (ZB=∞)
VinA
Ri
Rj
RL
Mij
VeqB
53. Advantages
• Switching of carrier frequencies allow more
efficient use of spectrum and compensation
for crowded channels.
• Potential exist for improved signal encryption
by sharing a randomized memristance
switching pattern between sender and
receiver.
57. Memristor Crossbar Circuit Design for
Sensor Stimulated Emergent Behavior
2nd crossbar array
Differential
Amplifiers
Summing
Amplifiers
V21 V22 V23 V24 V11 V12 V13 V14
Vsen5 Vsen6 Vsen7 Vsen8
Vact5
Vact6
Vact7
Vact8
M11 M12 M13 M14
M21 M22 M23 M24
M31 M32 M33 M34
M41 M42 M43 M44
Analog Sensor Voltages
Analog
Actuator
Voltages
Recursive feedback
between 1st and 2nd
crossbar can potentially
set up a dynamic
memory‐prediction
framework for
intelligence
58. Potential Applications #7 and 8
Neural Interfaces (spike counting and
classification) and Robotics (enhanced
responsiveness for actuator control)
‐To be continued at
NSTI Nanotech Conference and Expo
May 3‐7, 2009
Houston, TX
59. Conclusion
• Thank you to organizers and participants.
• Thank you to Dr. Wei Wang of the College of
Nanoscale Science and Engineering for
information and feedback on FPAAs and
suggestion for error analysis.
• Thank you to Jeff Hawkins for insights on
memory‐prediction framework for intelligence
as documented in On Intelligence